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Field-Induced Generation of Electron Traps in the Tunnel Oxide of Flash Memory Cells Yuri Tkachev Silicon Storage Technology, Inc. (a subsidiary of Microchip Technology Inc.) San Jose, CA, USA
[email protected] Abstract—The processes of trap generation and electron trapping in the tunnel oxide of SuperFlash memory cells have been analyzed. The strongly non-uniform distribution of electric field in the SuperFlash cell allowed us to rule out the electron- or hole-related mechanisms of trap generation. The experimental results of single-trap-induced modulation of the tunneling rate, and the analysis of field and potential distribution in the tunnel oxide, point to the high electric field as a direct cause of electrontrap generation. Keywords— Flash memory, floating gate, electron tunneling, electron trapping, program-erase cycling endurance, memory reliability, oxide degradation.
I. INTRODUCTION The processes of silicon dioxide degradation and breakdown under a high electric field have been extensively studied during the last several decades. Several models were proposed in the attempt to explain the vast amount of experimental data. The two most widely accepted models (generally referred as to E-model and 1/E model) consider the oxide degradation and time-dependent dielectric breakdown (TDDB) as the processes induced by electric field, and by the anode hole injection, resulting from electron Fowler-Nordheim (F-N) tunneling, respectively [1]. The 1/E model fits well the TDDB data at high electric fields, (>10 MV/cm), when electron and hole injection levels are high. At low electric field, when F-N tunneling is negligibly small, the thermochemical E-model seems to provide better data fitting. A unifying approach, combining both E- and 1/E models, has also been proposed [2].
electron- and hole- injection-related processes, and demonstrated the events of the generation of individual electron traps in silicon dioxide, caused exclusively by a high electric field. II. EXPERIMENTAL SETUP For the current study, we used split-gate Flash memory cells, fabricated using SST’s Embedded SuperFlash technology (ESF). The cells from two different technology generations were used: the 0.18 m 1st SuperFlash generation (ESF1) [3], and the most advanced 70 nm 3rd generation (ESF3) [4]. The cell structure and typical operating conditions are shown in Fig. 1. Both generations use interpoly Fowler–Nordheim tunneling from the FG tip (corner) for erase, and hot electron source-side injection for programming. The tunnel oxide is deposited by high-temperature LPCVD process. For most of the cells analyzed, the tunnel oxide thickness was about 150Å. Curve A in Fig. 2 shows a typical dependence of ESF1 cell read current Icell vs. FG potential [5]. After a regular erase, the FG potential is highly positive, and the cell current is mostly defined by the WL transistor. In the weekly erased state (the steep portion of Icell–VFG curve), the conductance of the FG channel is much lower compared to the conductance of the WL transistor and the cell current is controlled by the FG potential. Curve B (Fig. 2) represents the cell read current vs. erase voltage after cumulative erase. The shape of Curve B is similar to that of Curve A, and it can be shown that Curve A may be derived from Curve B by compressing it along the x-axis with a (1–CR) factor, where CR is the coefficient of capacitive
Oxide degradation at high electric field is of particular importance for the floating-gate (FG) memory cells, which use Fowler-Nordheim electron tunneling for erase. Trap generation and electron trapping in the tunnel oxide is the major factor that limits the program-erase cycling endurance of the FG memories. In the current paper, we analyzed the processes of trap generation and electron trapping/detrapping in the tunnel oxide of a SuperFlash® split-gate cell [3]. One of the major differences between the SuperFlash cell and the industrystandard stacked-gate cell is a highly non-uniform distribution of electric field in the tunnel oxide during erase operation. Due to this feature of SuperFlash technology, in some cases we were able to separate the effects of the electric field from the
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Fig. 1. The structure and typical operation conditions of ESF1 (a), and ESF3 memory cell (b). Two cells sharing common source are shown. Electron transfer directions during programming (Cell 1) and erase (Cell 2) are schematically shown by arrows. WL is the word line (select gate), CG is the coupling gate, EG is the erase gate, BL is the bit line, SL is the source line,
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Fig. 2. Icell vs. FG potential (Curve A), and Icell vs. erase voltage (Curve B, cumulative erase, 10 ms, 0.25 V step). Ir1 is the cell read current in deeply erased state.
coupling between the WL and the FG during erase. We define Verase as the voltage applied to the WL during erase, which is required to achieve a certain value of read current Icell. It can be shown that
Verase =
FGVt + ϕ + FTV , 1 − CR
(1)
where FGVt is the “native” threshold voltage of the FG transistor, ij is the FG potential overdrive required to achieve a certain value of read current, and FTV is the tunneling voltage during the measurement of erase curve (Curve B). Program-erase (P-E) cycling-induced electron trapping in the tunnel oxide results in an increase of FTV and Verase. We monitored the “instant” Verase value during program-erase cycling by applying a “weak erase” pulse (8–10 V) after a programming step of each P-E cycle, to bring the cell to the region of its maximum sensitivity to the FG charge (see curve B in Fig.2). The modulations of cell read current Icell after “weak erase” pulse, reflect the corresponding changes of Verase, caused by the trapping and detrapping of electrons in the tunnel oxide. III. RESULTS AND DISCUSSION Figure 3 shows the examples of “fine” trapping kinetics for the ESF1 cell. Typically, the degradation of erase performance (Icell in weakly erased state) has a discrete nature, associated with the trapping of individual electrons in the tunnel oxide [6]. From the non-saturating and power-law dependence of FTV degradation [5], [7], we can conclude that at least a large fraction of electrons causing the above modulations of Verase are trapped by the traps generated in the tunnel oxide during the erase operation in the course of P-E cycling. The single-electron-induced degradation of erase speed in many cases is quite significant, as can be judged from the amplitude of Icell steps (Fig. 3). In some cells, we saw that a single trapped electron can shift Verase by 2V. Such a huge effect of a single charge on the F-N tunneling rate allows us to make two assumptions: 1) the tunneling current in the ESF1 cell is extremely non-uniform with several preferred tunneling paths, and 2) the generated modulating trap is located exactly
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Fig. 3. Kinetics of cell current in erased state during program-erase cycling (3 different cells). Weak erase pulse (9V, 10 ms) was applied at every cycle before Icell measurement.
in the preferred tunneling path, and is very close to the injecting surface. To make a guess about the physical mechanism of the trap generation, let’s look closely at the structure of the ESF1 cell. The TEM picture of a typical cell (Fig. 4(a)) shows the radius of the FG tip to be less than 20Å. We may expect that, in some FG areas, the tip radius may be even smaller, which makes the FG-WL geometry strongly non-planar. Assuming a concentric cylinder approximation (Fig. 4(b)), the electric field distribution between FG and WL is described by the following formula:
E ( x) =
V T ( r + x ) ln(1 + ox ) r
,
(2)
where x is the distance from the FG tip, V is the voltage
Fig. 4. TEM cross section of ESF1 cell, and the approximation of FG-WL geometry by concentric cylinders.
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Fig. 5. (a) A simulated distribution of electric fields in the cylindrical (r=15Å) and in the planar (r=λ) geometry, and (b) The dependence of the electric field at the cathode (FG tip) vs. tip radius.
difference between WL and FG, and Tox is the tunnel oxide thickness. The distribution of electric field in the tunnel oxide for the cylindrical approximation in the case of r=15Å, and the electric field at the cathode (FG tip) as a function of tip radius, are shown accordingly in Fig. 5(a) and 5(b) for Tox=150Å and V=8V. It can be seen that the electric field is strongly nonuniform across the tunnel oxide: at the typical values of r, Tox and V, the field at the FG tip can reach 22 MV/cm, which is more than four times higher compared to the planar case (r=λ), while the field at the anode (WL) is much lower. Low electric field at the WL gate during erase dramatically changes the conditions for anode hole injection (AHI) [8]. Indeed, the barrier for hole tunneling becomes much wider compared to the planar case. The effective suppression of anode hole injection in the ESF1 cell can be clearly seen from the comparison of the erased state Vt distribution for two technologies: ESF1 and stacked-gate NOR Flash. Figure 6(a) shows a distribution of Verase, measured on the 4 Mb array of ESF1 cells. It can be seen that the distribution is unimodal, and is very close to a Gaussian one. Direct measurement of the erased cell Vt on the ESF1 cell is not possible because of cell’s split-gate design, and the lack of a dedicated coupling gate. However, there is a linear relationship between FG potential after erase and Verase. This relationship is demonstrated in Fig. 6(b), using the data from 64 ESF3 cells, which allow the negative erased state Vt to be directly measured.
gate cells after the erase pulse has a relatively large (about 1%) population of the cells, which demonstrate stronger erase compared to the main population (see the inset in Fig. 6(a)). Note that when channel hot-electron injection is used for programming, the Vt distribution of the programmed state is normal and unimodal. The fast erase tail, which is also responsible for the overerase issue in stacked-gate NOR Flash arrays, is associated with the tunnel barrier modulation by the holes, injected from the anode and trapped in the tunnel oxide near the FG-tunnel oxide interface [9]. A similar tail is also observed in both erased and programmed-state Vt, in stackedgate NAND Flash [10], and in EEPROM arrays [11], which utilize F-N tunneling for both erase and programming operations. We consider this AHI-induced Vt tail to be an intrinsic property of F-N tunneling in a planar Si-SiO2 structure. In case of a strong suppression of anode hole injection in non-planar FG geometry, we can reliably exclude any hole-related mechanisms from the trap-generation process in the tunnel oxide of the ESF1 cell. Another mechanism of trap generation may be potentially associated with the energetic electrons. The strong single-trap modulation of the tunneling rate assumes that the generated traps are located very close to the injecting surface, i.e. close to the FG tip. We can estimate the minimum distance from the FG, where the tunneled electron may gain kinetic energy of 2 eV, reported earlier as a threshold energy required for trap generation in the silicon dioxide [12]. The simulated band diagram at typical erase conditions in cylindrical geometry, obtained by integration of electric field (2) is shown in Fig. 7. It can be seen that the tunneling barrier width is about 28Å, and the minimum distance from the FG, where an electron can gain 2 eV above the bottom of the oxide conduction band, is close to 60Å. It is quite unlikely to expect the trap, located that far from the tunneling barrier, to have a large effect on the tunneling current [13]. Based on the above considerations, and on the experimental data on the strong effect of individual traps on the tunneling rate, we may suggest that the electron trap generation in the tunnel oxide of ESF1 cells is not associated with the energetic holes or electrons, but rather is directly caused by the high electric field in the tunneling barrier, in close proximity to the FG tip surface, where the electric field reaches its maximum. A strong modulation of the electron tunneling rate by a single
A typical Vt distribution of NOR Flash array of stacked-
Fig. 6. (a) Distribution of Verase for 4 Mb ESF1 cell array. The inset shows Vt distribution in erased and programmed state for a stacked-gate cell array, from [9]; (b) Linear correlation between Verase and erased state Vt (64 ESF3 cells).
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Fig. 7. Simulated Si-SiO2-Si band diagram for cylindrical FG-WL geometry at erase conditions with r=15Å, Tox=150Å, V=8V.
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local sharp FG/high field spot, which is responsible for this cell’s low Verase. After trapping a single electron on a newly generated trap in this particular spot, the cell becomes “average” and moves to the center of Verase distribution. IV. CONCLUSIONS
Fig. 8. Verase distribution (32 kb) shift over cycling for ESF1 (a) and ESF3 (b) technology
trapped electron is a result of the combination of the following factors. The electric field at the FG tip in the ESF1 cell at erase conditions, is a strong function of the tip radius (see Fig. 5(a)). Because of the distribution of FG poly-silicon grain orientations, there are some local FG areas with smaller tip radii. These local spots have the highest electric field, and conduct a large fraction of electron-tunneling current during erase. A high electric field, which may exceed 20 MV/cm at the FG surface, results in fast (in the ms timeframe) oxide bond breaking, and in the generation of electron traps in the same spot, which conducts a large current. Since the generated electron trap is located exactly in this preferred tunneling path, and is very close to the FG surface (in the tunneling barrier), the trapped electron can very efficiently modulate the tunneling rate in this local spot. It is worth noting that ESF3 cell (Fig. 1(b)), which utilizes corner-enhanced poly-to-poly tunneling for erase, also shows a noticeable single-trap-induced modulation of the erase performance, but the amplitude of these modulations is much smaller compared to ESF1 cell with a sharper FG tip. We associate this difference with the much lower electric field in the ESF3 cell at the FG corner (10-12 MV/cm) [4].
We analyzed the processes of electron trap generation and electron trapping in the tunnel oxide of SuperFlash memory cells. Due to a sharp floating-gate tip (the radius is
