Layout Decomposition for Triple Patterning ... - Semantic Scholar

Outline

Layout Decomposition for Triple Patterning Lithography Bei Yu1

1 ECE

Kun Yuan2 Boyang Zhang1 David Z. Pan1

Duo Ding1

Dept. University of Texas at Austin, Austin, TX USA

2 Cadence

Design Systems, Inc., San Jose, CA USA

Nov. 7, 2011

ICCAD2011 1A.1

Layout Decomposition for Triple Patterning Lithography

Outline

Outline

1

Introduction

2

Algorithm TPL Decomposition Flow Mathematical Formulation and Graph Simplification Semidefinite Programming (SDP) Approximation

3

Experimental Results

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Introduction Algorithm Experimental Results

Overcome the lithography limitations 193nm based lithography tool, hard for sub-30nm Delay or limitations of other techniques, i.e. EUV, E-Beam Double/Multiple Patterning Lithography Original layout is divided into two/several masks (layout decomposition) Decrease pattern density, improve the depth of focus (DOF) Objective: minimize both conflicts and stitches

a1

a

a1 Stitch

c b

c

a2 b

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mask1

b

mask2

a2

c



Triple Patterning Lithography (TPL)

b a

b

Conflicts

c

a

c

Layout is decomposed into three masks Similar but more difficult than 3 coloring problem Why Triple Patterning Lithography (TPL) ? Resolve some native conflict from DPL Reduce the number of stitches Triple effective pitch, achieve further feature-size scaling (22nm/16nm)

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Layout Decomposition

DPL Layout Decomposition Iterative Method (remove conflict → minimize stitch) Local Optimal Cut based methodologies (ICCAD’08, ICCAD’09, ASPDAC’2010) Minimize conflict and stitch simultaneously ILP Formulation (Yuan et. al ISPD’2009) → optimal but slow Heuristic (Xu et. al ISPD’2010) → only for planar layout TPL Layout Decomposition Previously only via layout is considered (Cork et. al SPIE’08)

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TPL Layout Decomposition

Our work is the first systematic study for general layout Mathematical Formulation Novel Color representations Semidefinite Programming based approximation TPL Layout Decomposition is HARDER Solution space is much bigger Conflict graph is NOT planar Detect conflict is not P, but NP-Complete

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Problem Formulation Problem: TPL Layout Decomposition Input: layout and minimum coloring space. Output: decomposed layout, minimize the stitch number and the conflict number. Two Lemmas: Deciding whether a planar graph is 3-colorable is NP-complete Coloring a 3-colorable graph with 4 colors is NP-complete

Theorem 1 TPL Layout Decomposition problem is NP-Hard

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TPL Decomposition Flow Mathematical Formulation and Graph Simplification Semidefinite Programming (SDP) Approximation

Layout Graph and Decomposition Graph Graphs Construction∗ :

f b a

1

Given input layout.

2

Generate Layout Graph (LG).

3

Projection.

4

Generate Decomposition Graph (DG).

c

e

d

Input Layout

* same with Yuan et. al ISPD’09 Two sets of edges: CE: conflict edge. SE: stitch edge.

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f b a

1

Given input layout.

2


3

Projection.

4


c

e

d

Input Layout

* same with Yuan et. al ISPD’09

f b

Two sets of edges:

e

a

CE: conflict edge.

c

SE: stitch edge.

d

Layout Graph

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f b a

1

Given input layout.

2


3

Projection.

4


c

e

e

d

project

f b

Two sets of edges:

e

a c

SE: stitch edge.

c

d

Input Layout


CE: conflict edge.

f b a

d

Layout Graph

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f b a

1

Given input layout.

2


3

Projection.

4


c

e

e

a c

SE: stitch edge.

d

d

project

f b

Two sets of edges:

e

c

d

Input Layout


CE: conflict edge.

f b a

f

b

e1

a d1

c

e2

d2 Layout Graph

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Decomposition Graph




Overview of the TPL Decomposition Flow Input Layout Decomposition Graph Construction Layout Graph Construction Bridge Computation Independent Component Computation ILP / Vector Programming Layout Graph Simplification Output Masks

Resolve Layout Decomposition problem: Integer Linear Programming (ILP) Vector Programming Three graph based Simplifications – improve scalability Vector Programming can be replaced by approximation methods: Semidefinite Programming (SDP) Mapping Algorithm ICCAD2011 1A.1



















Mathematical Formulation

min

X

X

cij + α

eij ∈CE

sij

s.t. cij = (xi == xj )

∀eij ∈ CE

sij = xi ⊕ xj

∀eij ∈ SE

xi ∈ {0, 1, 2}

P

(1)

eij ∈SE

cij is the number of conflicts,

∀i ∈ V

P

sij is the number of stitches

Represent 3 colors using two 0-1 variables (0, 0), (0, 1), (1, 0) Similar to previous DPL works, (1) can be transferred to ILP Solving ILP is NP-Hard problem, suffers from runtime penalty

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Graph Simplification Independent Component Computation Partition the whole problem into several sub-problems Bridge Computation Further partition the problem by removing bridges

a

a

a

a

b

b

b

b

Remove bridge

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Rotate colors to insert bridge




Graph Simplification (cont.) f

f

b a

e

c

Layout Graph Simplification

b

Push the nodes into stack

a

Right layout can be directly colored

c

f

d

(d)

c (g)

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f

c

e d

(e)

f

b a

a

d

a c

f

c (h)

f

b b e a f c

e

a

a c

d

c

e f

(f)

f

f

b

e

f

(c)

b d b e a f c

c

d

c (b)

e

e

a

d

c

(a)

Iteratively remove node with degree ≤ 2

e

a

d

f

b

b

e

b a c

d

e

d

(i)




Vector Programming New representation of colors Three vectors (1, 0), (− 21 ,

√ 3 ) 2

and (− 12 , −

√

3 ) 2

1

(- 2 ,

same color: v~i · v~j = 1

√3 ) 2

(1, 0)

different color: v~i · v~j = −1/2 1

(- 2 ,-

√ 3) 2

Vector Programming: X 2 1 2α X (v~i · v~j + ) + (1 − v~i · v~j ) 3 2 3 eij ∈SE eij ∈CE √ √ 1 3 1 3 s.t. v~i ∈ {(1, 0), (− , ), (− , − )} 2 2 2 2 min

(2)

Equal to Mathematical Formulation (1) Still NP-Hard ICCAD2011 1A.1




Semidefinite Programming (SDP) Approximation Relax Vector Programming (2) to Semidefinite Programming (SDP) SDP: min A • X

(3)

Xii = 1, ∀i ∈ V 1 Xij ≥ − , ∀eij ∈ CE 2 X 0 SDP (3) can be solved in polynomial time Mapping Algorithm Continuous SDP Solutions ⇒ Three Vectors

Mapping Vector Programming Solutions

SDP Solutions

Tradeoff between speed and global optimality

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Example of SDP Approximation

   A=  

0 1 1 −α 1

1 0 1 0 1

1 1 0 1 0

−α 0 1 0 1

After solving the SDP:  1.0 −0.5 −0.5  1.0 −0.5  1.0 X =   ...

1 1 0 1 0

SDP: min A • X



1.0 −0.5 −0.5 1.0

(3)

Xii = 1, ∀i ∈ V

    

1 Xij ≥ − , ∀eij ∈ CE 2 X 0

−0.5 −0.5 1.0 −0.5 1.0

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1

     

2

5 3

4




Example of SDP Approximation

   A=  

0 1 1 −α 1

1 0 1 0 1

1 1 0 1 0

−α 0 1 0 1

After solving the SDP:  1.0 −0.5 −0.5  1.0 −0.5  1.0 X =   ...

1 1 0 1 0

SDP: min A • X



1.0 −0.5 −0.5 1.0

(3)

Xii = 1, ∀i ∈ V

    

1 Xij ≥ − , ∀eij ∈ CE 2 X 0

−0.5 −0.5 1.0 −0.5 1.0

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1

     

2

5 3

4



Experimental Results

Experimental Setting: implement in C++ Intel Core 3.0GHz Linux machine with 32G RAM 15 layouts based on ISCAS-85 & 89 are tested

Layout parser: OpenAccess2.2 ILP solver: CBC SDP solver: CSDP

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Experimental Results – Graph Simplification Runtime Comparison of Normal ILP and Accelerated ILP 10,000

Normal ILP Accelerated ILP

100

0

4

85 5,

S1

2

58 8,

S3

7

93

41

5, S3

88

8, S3

52

,4 S1

88

,5 C7

15

,2 C6

40

,3 C5

70

,5 C3

08

,6 C2

,9

,3

C1

80

C1

99

C8

C4

32

1

55

10

C4

CPU Runtime (s)

1,000

Graph Simplification can save 82% runtime 1 Still maintain the optimality 1 Normal ILP uses Independent Component Computation ICCAD2011 1A.1



Experimental Results – How fast is SDP? Runtime Comparison of Normal ILP and Accelerated ILP 50 45 Accelerated ILP SDP Based

35 30 25 20 15 10

0

4

5, 85

S1

2

8, 58

S3

7

5, 93

8, 41

S3

S3

2

8 ,4 8

S1

8

,5 5 C7

5

,2 8 C6

0

,3 1 C5

0

,5 4 C3

,6 7 C2

5 ,3 5

C1

80

C1

99

C8

32

C4

,9 0

0

8

5

C4

CPU Runtime (s)

40

SDP can effectively speed-up ILP Compared with Accelerated ILP, SDP can save 42% runtime ICCAD2011 1A.1


0

C4 9

ILP 2 SDP ILP 9 SDP C8 ILP 80 SDP C1 ILP ,3 5 SDP C1 5 ILP ,9 0 SDP C2 8 ILP ,6 7 SDP C3 0 ILP ,5 4 SDP C5 0 ILP ,3 1 SDP C6 5 ILP ,2 8 SDP C7 8 ILP ,5 52 SDP S1 ILP ,4 8 SDP S3 8 8, ILP 41 SDP S3 7 5, ILP 93 SDP S3 2 8, ILP 58 SDP S1 4 5, ILP 85 SDP 0

C4 3

Stitch Num and Conflict Num


Experimental Results – How good (bad) is SDP? 250

200 Conflict Num Stitch Num

150

100

50

SDP can achieve near optimal results.

ICCAD2011 1A.1 Layout Decomposition for Triple Patterning Lithography


Experimental Results – Dense Layout

Circuit C1 C2 C3 C4 avg. ratio

SE# 16 38 24 56 -

CE# 247 289 381 437 -

Accelerated ILP st# cn# CPU(s) 1 5 5.5 0 15 17.32 0 14 33.41 9 32 203.17 2.5 16.5 64.9 1 1 1

st# 0 0 0 9 2.25 0.9

SDP Based cn# CPU(s) 6 0.29 16 0.77 15 0.32 32 0.49 17.3 0.468 1.05 0.007

For very dense layout SDP can achieve 140× speed-up.

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Experimental Results – S1488

Stitch number: 0 Conflict number: 1 ICCAD2011 1A.1



Conclusion

First systematic work on triple patterning layout decomposition Mathematical formulation to minimize both stitches and conflicts Novel color representations Semidefinite programming based approximation Expect to see more researches on Triple Patterning Lithography

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Thank

You !

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Appendix – ILP Formulation min

X

cij + α

eij ∈CE

X

sij

(4)

eij ∈SE

s.t. xi1 + xi2 ≤ 1 xi1 + xj1 ≤ 1 + cij1

∀eij ∈ CE

(1 − xi1 ) + (1 − xj1 ) ≤ 1 + cij1

∀eij ∈ CE

xi2 + xj2 ≤ 1 + cij2

∀eij ∈ CE

(1 − xi2 ) + (1 − xj2 ) ≤ 1 + cij2

∀eij ∈ CE

cij1 + cij2 ≤ 1 + cij

∀eij ∈ CE

xi1 − xj1 ≤ sij1

∀eij ∈ SE

xj1 − xi1 ≤ sij1

∀eij ∈ SE

xi2 − xj2 ≤ sij2

∀eij ∈ SE

xj2 − xi2 ≤ sij2

∀eij ∈ SE

sij ≥ sij1 , sij ≥ sij2

∀eij ∈ SE

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