Lecture 02: 68000 Microprocessor Architecture - Gen Ocean

Review of Last Lecture v Evolution of computers

Lecture 02: 68000 Microprocessor Architecture

First generation (vacuum tubes), 1946-1958 Second generation (transistor), 1959-1964 Third generation (integrated circuit), 1965-1970 Fourth generation (LSI/VLSI, Microprocessor), 1971-present

v Microprocessor based systems Textbook:

CPU, memory, timing unit, interrupt circuitry, I/O, peripherals, …

v Microprocessor operation

The 68000 Microprocessor: Hardware and Software Principles and Applications, by James Antonakos, 5th Edition, Prentice Hall, 2004.

Reset Fetch Decode Execute Fetch

v Programming languages HLL, assembly, and machine languages

v Developing software for 68000 microprocessor

Excerpted from lecture notes prepared by Jie Hu, Assistant Professor, Electrical and Computer Engineering Newark College of Engineering New Jersey Institute of Technology

HELLO program

Block Diagram of Macintosh 512K Motherboard Mouse

Processor 68000

Keyboard

I/O Interface 6522

Modem Printer Realtime clock

Serial I/O 8530

Disk drive

Floppy disk controller

v Functional Description of the 68000 v Programming Model of the 68000 v Number Systems and Base Conversion

System bus System ROM

Today’s Lecture

RAM buffers and Mux

PAL decoders Control signals

Dynamic RAM 512KB

Sound logic

v ASCII Table v EASy68K Text I/O

Video logic Speaker

Video display

68000/ColdFire Background v MC68000 introduced by Motorola in 1979. v Notable sightings: Used in the Sun, the first ever workstation Used in the Macintosh, first ever GUI personal computer Used in early versions of PalmPilot PDA v Why 68000 for learning microprocessors? Powerful & simple instruction set Sophisticated interfacing capabilities Able to support high-level language and operating systems Flat memory map (versus segmented memory used in Intel 80x86) The most popular µP in academia

68000/ColdFire Background v Internally, MC68000 has 32 bit data paths and 32-bit instructions interfaces with external components using a 16-bit data bus. So a programmer considers it 32-bit chip while a system designer considers it a 16-bit chip. Hence the “16-/32-bit chip” designation. v The original 68000 was available in 64-bit DIP or 68-pin PLCC. v 68000 family has many versions. 680x0 means 68000, 68008, 68010, 68020, 68030, 68040 and 68060. Newer versions are “upward compatible” with older versions. The family is also affectionately called 68k or MC68k. Most commonly found members are 68000, 68020, CPU32 and ColdFire

1

68000/ColdFire Background

68000 Hardware D4

v The family includes 16-bit peripherals chips. The 68000 can use 68000-type peripherals chips for higher performance or v older 6800-type peripherals for lower cost. ColdFire is the current version ‘RISC’ified 68000 processor core. Smaller, less power used than normal 68020. A ColdFire chip is an embedded processor with integrated peripherals You can find it in some HP laserjet printers v Today,the 68k family is made by Freescale semiconductors.

68000 Microprocessor Pin Layout D4 D3 D2 D1 D0 AS UDS LDS R/W DTACK BG BGACK BR VCC CLK GND HALT RESET VMA E VPA BERR IPL2 IPL1 IPL0 FC2 FC1 FC0 A1 A2 A3 A4

v v v v v

3 2 1 0

CC

2

1 0 2 1 0 1 2 3 4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

68000 CPU

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 GND A23 A22 A21 VCC A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5

68000 Microprocessor Pin Input/Output Signals 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

68000 CPU

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 GND A23 A22 A21 VCC A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5

68000 Microprocessor Pin Signals: Summary v v v v v

D Specifications D D 32-bit data and address registers D AS UDS 16-bit data bus LDS R/W 24-bit address bus DTACK BG 14 addressing modes BGACK BR V Memory-mapped input-output CLK GND Program counter HALT RESET VMA 56 instructions E VPA 5 main data types BERR IPL 7 interrupt levels IPL IPL FC Clock speeds: 4 MHz to 12.5 MHz FC Synchronous and asynchronous data FCA A A transfers A

Supply Voltage/Ground: Vcc, GND Clock: CLK Address bus: A23-A1 Data bus: D15-D0 Asynchronous bus control: Address Strobe (AS), Read/Write (R/W), Upper/Lower Data Strobe (UDS, LDS), Data Transfer Acknowledge (DTACK) Bus arbitration control: Bus Request (BR), Bus Grant (BG), Bus Grant Acknowledge (BGACK) Interrupt control: IPL0, IPL1, IPL2 System control: Bus Error (BERR), Reset (RESET), Halt (HALT) M6800 peripheral control: Enable (E), Valid Peripheral Address (VPA), Valid Memory Address (VMA) Processor status: FC0, FC1, FC2

+5V CLK

D15 –D0

VCC VCC

A23 –A1 FC2

Processor status

R/W

FC0

E VMA

Asynchronous bus control

LDS

68000

DTACK

CPU

VPA

BR BG BGACK

BERR

System control

Address bus

AS

FC1

UDS

6800 peripheral control

Data bus

IPL0 IPL1

RESET HALT GND GND

IPL2

Bus arbitration control Interrupt control

Memory Addressing Space v In 68000 microprocessor, address bus A23..A1 together with !UDS, !LDS form 24-bit addressing space, i.e., 16MB memory space v A23..A1 address a word, and (!UDS, !LDS) selects which byte(s) in the word to be accessed !UDS

!LDS

R/!W

High

High

-

Low

Low

High

Low

Low

D15-D8

D7-D0

Not Valid Data

Not Valid Data

High

Valid Data Bits 15-8

Valid Data Bits 7-0

High

Not Valid Data

Valid Data Bits 7-0

High

High

Valid Data Bits 15-8

Not Valid Data

Low

Low

Low

Valid Data Bits 15-8

Valid Data Bits 7-0

High

Low

Low

Valid Data Bits 7-0*

Valid Data Bits 7-0

Low

High

Low

Valid Data Bits 15-8

Valid Data Bits 15-8*

* These conditions are a result of this implementation and may not appear on other devices

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Virtual Memory Space

68000 Software/Programming Model 78 D5

68000 Microprocessor

Addr (A23..A1), UDS’, LDS’

0x000000 0x000001 0x000002

Data Register

Mem Addr Decoder Address Register

AE 00 00

A0 A1 A2 A3 A4 A5 A6 A7 USP SSP

0

31

0

31

Program counter

0xFFFFFD 0xFFFFFE 0xFFFFFF

31 D0 D1 D2 D3 D4 D5 D6 D7

23

0

PC 15

Status register

Sample Program

0

SR

68000 Programming Model: Status Register User Byte System Byte 15 T

13 -

S

(Control Code Register)

10 -

-

I2

9 I1

8

4

I0

X

0 N

Z

V

C

Extend

Trace bit

Negative

Supervisor state

zero Overflow

Interrupt mask

Carry Condition Codes

68000 Programming Model: Data Register v 8 32-bit data registers: D0 .. D7 v Data types: Byte: 8-bit (7..0) Word: 16-bit (15..0) LongWord: 32-bit (31..0)

v Data access: byte access lower 7..0 bits word access: lower 15..0 bits longword access: whole 32 bits

Interpret Memory Address: Endianness

MSB 31 D0 D1 D2 D3 D4 D5 D6 D7

16 15

LSB 8 7

0

v Endianness: ordering of bytes within a larger object, e.g., word, i.e., how a large object is stored in memory v 68000 is a BIG Endian processor Memory 0x00..00 0x00..10 Big Endian

Little Endian 0x00..13

byte (.B) Word (.W)

LongWord (.L)

3

2

1

register

0

3 0xffffffff

2

1

0

register

3

Endianness: Example v Register value (.L): 0XBDC3A827 bit 31

0x00..00 0x00..10 BD C3 A8 0x00..13 27

0xffffffff

BD C3 A8 27 3 2 1 0

Big Endian

0

byte 0x00..00 27 A8 C3 Little Endian BD

0x00..10 0x00..13

0xffffffff

4