Lecture 13

Dynamic Logic

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Dynamic CMOS q

In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. § fan-in of n requires 2n (n N-type + n P-type) devices

q

Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. § requires on n + 2 (n+1 N-type + 1 P-type) transistors 2

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Dynamic Gate Clk

Clk

Mp

Mp

Out In1 In2 In3 Clk

CL PDN

Out A C B

Me

Clk

Me

Two phase operation Precharge (CLK = 0) – Me is off => no static power Evaluate (CLK = 1) – Mp is off 3 EE141

Dynamic Gate Clk

Clk

Mp

off Mp on

Out In1 In2 In3 Clk

CL PDN

1 Out ((AB)+C)

A C B

Me

Clk

off Me on

Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) 4 EE141

Conditions on Output q

Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.

q

Inputs to the gate can make at most one transition during evaluation.

q

Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL (fundamentally different than static gates)

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Properties of Dynamic Gates q

q q

q

Logic function is implemented by the PDN only § number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels – Sizing the PMOS doesn’t impact correct functionaility. Sizing it up improves the low-to-high transition time (not too critical), but trades-off increase in clock-power dissipation Faster switching speeds § reduced load capacitance due to lower input capacitance (Cin) § reduced load capacitance due to smaller output loading (Cout) § no Isc, so all the current provided by PDN goes into discharging CL

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Properties of Dynamic Gates q

Overall power dissipation usually higher than static CMOS § no static current path ever exists between VDD and GND (including Psc) § higher transition probabilities § extra load on Clk -> higher dynamic power consumption

q

Needs a precharge/evaluate clock

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Issues in Dynamic Design 1: Charge Leakage CLK Clk

Mp

Out CL

A Clk

Me

Evaluate

VOut Precharge

Leakage sources Dominant component is subthreshold current. Dynamic circuits require a minimal clock rate => unattractive for low speed products such as watches, hearing aids..etc. Note: PMOS leakage counteracts leakage of PDN. Output voltage is set by resistive 8 divider composed of pull-down and pull-up paths. EE141

Solution to Charge Leakage Keeper Clk

Mp

A

Mkp

CL

Out

B Clk

Me

Same approach as level restorer for pass-transistor logic. Keeper is made small to allow the strong PDN to lower the Out node substantially below the switching threshold of the next gate (to reduce contention – tradeoff between speed and robustness). The feedback configuration also eliminates static power in CMOS inverter. EE141

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Issues in Dynamic Design 2: Charge Sharing Clk

Mp

Out

A

CL

B=0 Clk

Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness

CA Me

CB

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Charge Sharing VDD Clk

case 1) if ∆V out < VTn

Mp Out CL

A

Ma X

B=0

Clk

Mb

Me

Ca

Cb

C L VDD = C L Vout ( t ) + Ca ( VDD – V Tn ( V X ) ) or Ca ∆ V out = Vout ( t ) – V DD = – -------- ( V DD – V Tn ( V X ) ) CL

case 2) if ∆V out > VTn Ca   ---------------------∆Vout = –VDD  Ca + CL    Boundary condition when ∆Vout=VTn

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Ca VTn = CL VDD −11 VTn

Solution to Charge Redistribution Clk

Mp

Mkp

Clk Out

A B Clk

Me

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) 12 EE141

Issues in Dynamic Design 3: Crosstalk & Backgate Coupling Clk

Mp

A=0

Out1 =1 CL1

Out2 =0 CL2

In

B=0 Clk

Me

Dynamic NAND

Static NAND

A transition in the input (In) may cause the output of dynamic gate Out 1 to drop due to capacitive coupling. This may cause Out 2 not to drop all the way to “0” + could cause static power to be dissipated. If the voltage drop is large enough, the circuit can evaluate incorrectly. 13 EE141

Cascading Dynamic Gates V Clk

Mp

Clk

Clk

Mp Out2

Out1 In

In Clk

Me

Clk

Me

Out1

VTn ∆V

Out2 t

When Out1 > Vtn, Out2 keeps discharging When Out1 < Vtn, Out2 is left at an intermediate level The correct level will not be recovered, since dynamic gates rely on capacitive storage. The reduced Out2 swing, reduces the noise margins and may cause malfunction. The cascading problems arises because the outputs of each gate are precharged to “1”. Setting all the inputs to “0” during precharge addresses this concern. When doing so, all transistors in the PDN are turned off after precharge, and no inadvertent discharging of the storage capacitors can occur during evauation.

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Domino Logic Clk In1 In2 In3 Clk

Mp

1→1 1→0

PDN

Me

Out1

Clk

Mp Mkp

Out2

0→0 0→1

In4 In5 Clk

PDN

Me

The inverter: (a) ensures that all inputs are set to “0” at the end of the precharge phase (b) has a low impedance output, which increases the noise immunity. (c) Can be used to drive a keeper device to combat leakage and charge redistribution.

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Why Domino? Clk

Ini Inj Clk

PDN

Ini Inj

PDN

Ini Inj

PDN

Ini Inj

PDN

Like falling dominos! q q

Since each dynamic gate has a static inverter, only non-inverting logic can be implemented (there are ways to deal with this) Very high speed § Input capacitance reduced 16

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