Lecture 3rd_Parallel interfacing.pdf - Google Drive

Compiled by: Er. Saban Kumar K.C.

Lecture 3rd Chapter 2: Parallel Interfacing with Microprocessor based system (4 hours- 3 lectures) Introduction: In data transmission, parallel communication is a method of conveying multiple binary digits (bits) simultaneously. It contrasts with serial communication, which conveys only a single bit at a time; this distinction is one way of characterizing a communications link. If both channels operated at the same clock speed, the parallel channel would be eight times faster. It is widely used within integrated circuits, in peripheral buses, and in memory devices such as RAM.

After the new newmillennium, millennium, channels between computer After the thethe channels between the the computer a and its peripheral devices have switched from to deviceshave serial data transfer. it would nd its parallel peripheral switched Although from parallel to serialseem da that a parallel cable with multiple lines for data would always yield a faster data transfer rate than a single data line, keeping the bits aligned ta transfer. Although it would seem that a parallel cable with mu in a parallel channel requires more complex electronics. It is nearly impossible to create 16, 32 or 64 ltiple lines for datawould always yield a faster data transfer rate wire traces on a motherboard that are identical in length. Signals on multiple data lines can arrive at than a single data line, keeping the bits aligned in a parallel cha the receiving end at different times and must be synchronized in order to turn each set of eight bits into nnel requiresmore complex electronics. It is nearly impossible t meaningful bytes. In addition, parallel data channels are susceptible to electromagnetic interference o create 16, or 64[1] wire traces on a motherboard that are ide between the 32 wires. ntical inlength. Signals on multiple data lines can arrive at the r

I/O Transfer Synchronization [2]: eceiving end at different times and must be synchronized in ord er toturn each set of eight bits into meaningful bytes. In addition , parallel data channels are susceptible to electromagneticinterf erence between the wires.

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2.1 Methods: i. Simple I/O: Brute-force method:

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Useful when the data timing is unimportant. For input --The microprocessor reads the interface chip and the interface chip returns the voltage levels on the input port pins to the microprocessor. For output --The interface chip places the data that it received from the microprocessor directly on the output port pins.

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This timing waveform illustrates the simple I/O where cross lines represent the time at which a new data byte becomes valid on the output lines of the port. Absences of other waveforms indicate that this output operation is not directly dependent on any other signals. For e.g.: Switch and LED interfacing with Microprocessor ii. Simple Strobe I/O: 

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A strobe signal is used to indicate that data are stable on I/O port pins, useful when the chip and I/O device can keep up with each other. For input -- the interface chip latches the data into its data register using the strobe signal. For output --the interface chip places the data on port pins that it received from the microprocessor and asserts the strobe signal. The output device latches the data using the strobe signal.

For e.g.: we can discuss the ASCII encoded keyboard. When a key is pressed, circuitry on keyboard sends out ASCII code for pressed key on eight parallel data lines and then sends out a strobe signal on another line to indicate that valid data is present on eight data lines. iii. Handshaking: I/O devices accept or release information at much slower rate than the microprocessor. Handshaking is the method that synchronize the I/O device with microprocessor. Handshake data transfer use signal between the microprocessor and the peripheral devices for communicating. Types of handshakes in parallel interfacing: Single handshake & Double handshake. i. Single handshake [3] 

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In single handshake, a peripheral device first sends a "Strobe signal" to the microprocessor to indicate that it is ready to send data. The microprocessor, upon detecting the strobe signal, opens up its input port and receives the data. After receiving data, it sends an "Acknowledge signal" to the peripheral to indicate that transmission has been completed.

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ii. Double handshake: For data transfers where even more coordination is required between the sending system and the receiving system, a double handshake is used. It can have two transfer schemes. a. Input Handshake (Peripheral to Microprocessor):    

The peripheral asserts its line low to ask microprocessor “Are you ready?” The microprocessor raises its ACK line high to say “I am ready”. Peripheral then sends data and raises its line low to say “Here is some valid data for you.” Microprocessor then reads the data and drops its ACK line to say, “I have the data, thank you, and I await your request to send the next byte of data.”

b. Output Handshake (Peripheral from Microprocessor): Microprocessor sends a strobe (STB’) signal and data and peripheral sends acknowledgement (ACK) signal. 2.2 8255 as general purpose programmable I/O device The 8255A is a programmable peripheral interface (PPI) device designed for use in Intel microcomputer systems. Its function is that of a general purposes I/O component to Interface peripheral equipment to the microcomputer system bush. [4] Features: A. Ports of Intel 8255A: 

Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.

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Port B is similar to PORT A.

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Port C can be split into two parts, i.e. PORT C lower PC0−PC3 and PORT C upper PC7−PC4 by the control word.

These three ports are further divided into two groups,  

Group A includes PORT A and upper PORT C. Group B includes PORT B and lower PORT C. Fig: pin diagram of Intel 8255A [5]

B. Operating Modes: i. Bit Set/Reset mode: The BSR mode is used to set or reset the bits in port C. ii. I/O mode

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Mode 0: In this mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit ports. Each port can be programmed in either input mode or output mode where outputs are latched and inputs are not latched. Ports do not have interrupt capability.

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Mode 1: In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as either input or output ports. Each port uses three lines from port C as handshake signals. Inputs and outputs are latched.

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Mode 2: In this mode, Port A can be configured as the bidirectional port and Port B either in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals for data transfer. The remaining three signals from Port C can be used either as simple I/O or as handshake for port B.

C. TTL compatible & improved dc driving capability PIN Description: [6]

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References [1] encyclopedia2, "parallel data transfer," 2017. [Online]. Available: http://encyclopedia2.thefreedictionary.com/parallel+data+transfer. [2] ManjeeraJeedigunta, "Computer Systems," 2017. [Online]. Available: http://blogs.cae.tntech.edu/msjeedigun21. [3] M. Fauzi, "Microprocessor Interfacing- Parallel, Serial," 2017. [Online]. Available: https://www.scribd.com/doc/54755060/Microprocessor-Interfacing-Parallel-Serial. [4] discipline.elcom.pub, "8255 Programmable Peripheral Interface," 2017. [Online]. Available: http://discipline.elcom.pub.ro/amp2/curs/8255_2.html. [5] tutorialspoint.com, "8255A - PROGRAMMABLE PERIPHERAL INTERFACE," 2017. [Online]. Available: https://www.tutorialspoint.com/microprocessor/microprocessor_intel_8255a_pin_description.htm. [6] S. Kaware, "INTERFACING," 2017. [Online].

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