The front-end (Level-0) electronics interface module for the LHCb RICH detectors M. Adinolfi a,1 , J.H. Bibby a , S. Brisbane a , V. Gibson b , N. Harnew a , M. Jones a , J. Libby a,∗ , A. Powell a , C. Newby a , N. Rotolo a , N. Smale a,2 , L. Somerville a , P. Sullivan a , S. Topp-Jorgensen a , S. Wotton b , K. Wyllie c a Sub-department
of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH, United Kingdom
b Cavendish
Laboratory, University of Cambridge, Madingley Road, Cambridge CB3 0HE, United Kingdom c CERN,
CH-1211, Geneva 23, Switzerland
Abstract The front-end (Level-0) electronics interface module for the LHCb RICH detectors is described. This module integrates the novel hybrid photon detectors, which instrument the RICH detectors, to the LHCb DAQ, trigger and control systems. The system operates at 40 MHz with a first-level trigger rate of 1 MHz. The module design is presented and results are given for both laboratory and beam tests. Key words: PACS:
1
Introduction
The LHCb experiment will study the decays of B hadrons produced in pp collisions at a centre–of–mass energy of 14 TeV [1]. The LHC, operating with ∗ Corresponding author Email address:
[email protected] (J. Libby). 1 Now at Department of Physics, University of Bristol, H. H. Wills Physics Laboratory, Tyndall Avenue, Bristol BS8 1TL, United Kingdom. 2 Now at Max-Planck-Institut f¨ ur Kernphysik, Saupfercheckweg 1, 69117 Heidelberg, Germany.
Preprint submitted to Elsevier Science
13 November 2006
an instantaneous luminosity of 2 × 1032 cm−2 s−1 for 107 s/year, will produce 1012 b¯b quark pairs. This large data sample will allow precise measurements of CP –violating parameters in many different B–decay final states. These measurements will overconstrain the Standard Model description of CP violation; any discrepancies will be evidence for new physics. The ability to identify charged hadrons is essential for reconstructing the B ˇ decays of interest. LHCb includes Ring Imaging Cerenkov (RICH) detectors ± ± to identify π and K in the momentum range 1 to 100 GeV/c [2]. There are two RICH detectors with three radiators of differing refractive indices (n). RICH 1 has an aerogel radiator (n − 1 = 0.03) and a gaseous C4 F10 radiator (n−1 = 1.4×10−3 ), which cover the momentum ranges 1–10 GeV/c and up to 65 GeV/c, respectively. RICH 2 has a gaseous CF4 radiator (n − 1 = 5 × 10−4 ) that covers the momentum range up to 100 GeV/c. Fig. 1 shows schematic sections of RICH 1 and RICH 2. ˇ The emitted Cerenkov radiation is focussed and reflected out of the LHCb spectrometer acceptance by spherical and planar mirrors in both RICH detectors. The focal planes are instrumented with Hybrid Photon Detectors (HPDs) [3], which have both the high quantum efficiency and spatial precision required to discriminate between π ± and K ± over the full momentum range. A photoelectron produced in the photocathode of the HPD is accelerated and electrostatically focussed onto a silicon anode segmented into 8192 pixels arranged into a 256 × 32 array. Each pixel is of dimension 62.5 × 500 µm. The custom-buit binary readout ASIC, LHCBPIX1 [4], is bump-bonded to the silicon anode and the complete assembly is encapsulated within the vacuum of the photodetector. The LHCBPIX1 ASIC pre–amplifies and shapes the silicon signals; these are then discriminated at a rate of 40 MHz, which corresponds to the bunch crossing frequency of the LHC. Any signals above the discriminator threshold are considered as hits. The LHCBPIX1 ASIC can operate in two modes. One mode in which all 8192 pixels are readout and another in which the hits in an 8-pixel group are OR-ed together and the result is considered as a single hit. The second mode of operationleads to an effective 32 × 32 pixel array with each pixel being of dimension 500×500 µm. The mode of operation with 1024 pixels is used by LHCb to collect data because it gives the required spatial accuracy with reduced data size. The mode with 8192 pixels is used for calibration and diagnostic running. Any hits are buffered within delay units in LHCBPIX1 ASIC for the fixed 4 µs latency of the first level of the LHCb trigger (Level–0). Accepted data are multiplexed into thirty-two 32-bit words for readout to the front–end electronics (Level-0) interface module. The events are buffered in a 16 deep First In First Out (FIFO) register which allows data from up to 16 consecutive bunch crossings to be accepted. 2
A total of 484 HPDs are used in the RICH detectors, 196 in RICH 1 and 288 in RICH 2. These are mounted in columns of 14 (16) HPDs in RICH 1 (RICH 2). Each Level-0 interface module services two HPDs, therefore, 242 are required to instrument both RICH detectors. Fig. 2 is a photograph of a RICH 2 column. The purpose of the Level-0 interface module is to read out a pair of HPDs and provide the interface to the timing and fast control (TFC) system, the data acquisition (DAQ) system and the experimental control system (ECS). In addition, the interface module provides all low voltage (LV) to the LHCBPIX1 ASIC and the silicon sensor of the HPD. Each Level-0 interface module is situated within the RICH detector volume; this leads to constraints on the dimensions of the board, its radiation tolerance and power consumption. The integrity of the fast signalling required by the 25 ns clock speeds must also be maintained. The module integrates digital, analogue and optical components. The paper is arranged as follows. Section 2 details the overall module design and the functionality of the components. Section 3 presents the results of laboratory and beam tests and the performance of components after irradiation is also discussed. The conclusions are given in Section 4.
2
Module design
A schematic of the Level–0 interface module is shown in Fig. 3. All the major blocks and their interconnections are shown. At the heart of the Level–0 interface module is the Pixel Interface (PINT) FPGA. The other main components are the TTCrx ASIC, analogue PILOT ASIC, GOL serialiser ASIC and the VCSEL (Vertical Cavity Surface Emitting Laser) optical transmitters. All these components, along with their integration, are described in the following sections.
2.1
Board design and layout
The dimensions of the Level-0 board are constrained to be 165 × 1000 × 3 mm3 so that the module fits within the HPD columns along with the other services: the cards to provide LV power and HV power, and cooling plates. Fig. 4 is a photograph of the Level-0 interface module; the density of component integration is visible. The components are mounted on an 18 layer printed circuit board. Data speeds of up to 1.6 Gbits/s are handled by the board. Therefore, many lines are of controlled impedance and limited length to ensure clean rise times, signal source matching and synchronized digital timing across 3
the whole board. Even with ground currents up to 6 A, the routing leads to negligible noise being generated. The I/O’s of the board are as follows. The connection to a HPD is made with a pair of 50–way kapton cables which plug into a minimal insertion force connector 3 . There is an optical receiver 4 for the TFC signals and two VCSEL optical transmitters 5 for the data transfer to the DAQ system. There is also a 40-way IDC connector for the LV power supplies and ECS signals.
2.2
Pixel Interface FPGA
The PINT ASIC is an AX1000 fuse-link Field Programmable Gate Array (FPGA) 6 . The programmability of the PINT FPGA allows it to perform the major functionality of the Level-0 interface module as well as allowing flexibility of design. Fig. 5 is a schematic of the main blocks of the PINT FPGA along with their internal and external interconnections. All HPD data pass through the PINT FPGA, which controls data formatting along with the supervision of all the TFC and ECS signals. The PINT FPGA interprets the global trigger and clock signals received by the TTCrx ASIC (see Section 2.3) to generate the data capture and readout commands for the LHCBPIX1 ASIC. The data packet from the LHCBPIX1 ASIC constitutes thirty-two 32-bit words to describe the hit pattern. These data are formatted within the PINT FPGA with the addition of two 32-bit header words that contain event and HPD identifiers, along with information about the status of the Level-0 electronics. A 32-bit trailer word is added that contains the parity of each column of data; this allows downstream tests of the data transmission integrity to the DAQ system. The PINT also emulates the FIFO of the LHCBPIX1 ASIC, which is a 16 events deep, to attach the correct event identifiers to the data and to identify overflows. The FIFO also controls the data readout sequence. Furthermore, the PINT can be configured to handle data from the LHCBPIX1 ASIC when operating in the mode with 8192 pixels, which is used for testing and diagnostic purposes. The decoding of the TFC signals is also performed by the PINT FPGA to set the run type and to generate calibration test sequences. The other settings of 3
FH12S-50S-0.5 SH, Hirose Elec. Co. Ltd., 1-11, Osaki 5-chome, Shinagawa-ku, Tokyo 141-8586. 4 TRR-1B43-000, TrueLight Corporation, 21 Prosperity Road, I Hsinchu Science Park, Hsin-Chu, Taiwan, R.O.C. 300. 5 ULM-850-05-TN-USMBOP, U-L-M photonics GmbH, Lise-Meitner St. 13, D89081 Ulm, Germany. 6 AX1000, Actel Corporation, 2061 Stierlin Ct., Mountain View, CA 94043, USA.
4
the Level-0 electronics are controlled by JTAG [5] signals that are provided to the Level-0 module by the custom SPECs slave mezzanine board [6], which is situated on an auxiliary LV-supply board. The PINT FPGA interfaces these signals to the other components on the board, some of which have differing signalling requirements: LVDS, CMOS and GTL. The configuration registers of the TTCrx ASIC are addressed with the I2 C protocol [7]. The conversion of the JTAG to I2 C signals is performed by the PINT FPGA. The status of all Level-0 module components and the LHCBPIX1 ASICs can be read via the PINT FPGA to the ECS. All flip-flops and latches are implemented with triple-voting logic to reduce susceptibility to radiation-induced single-event upsets (SEUs). Fig. 6 shows the gate-level triple-voting logic.
2.3
Timing and fast control
On the Level-0 module the TTCrx ASIC [8] decodes the TFC signals, received optically, to construct the clock, Level-0 trigger, calibration and reset signals. The PINT FPGA distributes these signals to the external board components and the HPDs. The TTCrx ASIC generates two additional clock signals, which can be skewed with respect to the 40 MHz clock of the TFC system and each other, by 104 ps increments. The Level-0 module uses one of the skewed clocks to generate the readout sequence of the LHCBPIX1 ASIC and the data transmission to the DAQ system; the offset will be calibrated to maximise the efficiency of each board to compensate for timewalk effects of the LHCBPIX1 ASICs, the time of flight of particles and cable delays. The other skewed clock is used to generate test pulses at the input to the preamplifier of the LHCBPIX1 ASIC for timing calibrations of the readout sequence.
2.4
Optical data output
The formatted data from the PINT FPGA are transferred serially at 1.6 Gbit/s to the rest of the DAQ system via 100 m of 50/125 µm multimode optical fibre. The 32-bit wide parallel data from the PINT FPGA are serialised by the GOL ASIC [9,10]. The data are formatted for Gigabit-link Ethernet transmission, via fibre-optic cables, using 8-bit by 10-bit encoding [11]. The clock input to the GOL ASICs has to have a peak-to-peak jitter less than 40 ps to maintain data integrity. The 40 MHz clock from the TTCrx ASIC that drives the GOL ASICs has a 300 ps peak-to-peak jitter, therefore, a special ”jitter filter” circuit is incorporated into the design. The radiation tolerant QPLL ASIC [12] is used, which is a quartz crystal based phase-locked loop. The layout around the QPLL ASIC is designed to reduce power dissipation to a level that will not increase the jitter above 40 ps. 5
The serialised data from the GOL ASIC is transferred directly to the VCSEL optical transmitter. This commercial device has been developed in collaboration with LHCb to match the GOL ASIC outputs and to ensure an adequate light intensity at the receiver of the off-detector DAQ electronics. Special circuitry is introduced to power the GOL ASICs and VCSELs to prevent poor phase locking of the GOL ASIC and unacceptable biases being applied to the VCSEL when the board is first switched on. The radiation tolerant CRT4T ASIC [10] was used to realise the solution.
2.5
Power supplies
Ten externally generated digital and analogue power supply voltages are routed for either internal use or for the HPDs. The analogue and digital reference planes on the Level-0 interface module are kept separate so that the supplies can be filtered locally. Particular care is taken in the supplies to the TTCrx, QPLL, GOL and LHCBPIX1 ASICs in which extraneous noise could severely degrade the performance. The 80 V silicon bias for the silicon anode of the HPD is routed through the interface module and filtered with respect to analogue ground. The leakage current is less than 1 nA at the nominal bias. The PILOT ASIC [13] provides reference voltages for the LHCBPIX1 ASIC Digital-to-Analogue Convertors (DACs) that provide the GTL references, discriminator threshold references and test-pulse voltage levels. The PILOT ASIC contains a 10-bit Analogue-to-Digital Convertor (ADC) to monitor the reference voltages. The PILOT ASIC also has four inputs that are used for temperature monitoring by platinum resistors placed on the PILOT ASIC itself, the PINT FPGA and the bases of the two HPDs. The PILOT ASIC is controlled with JTAG via the PINT FPGA. The PINT FPGA also routes the results of the monitoring ADCs to the ECS. The PILOT ASICs are calibrated and tested in-house prior to mounting on the Level-0 interface modules.
3
Module performance
To ensure the Level-0 interface modules operate to the required specifications, extensive qualification tests have been performed. The modules have undergone laboratory tests after production to ensure full functionality; these tests are described in Section 3.1. The PINT FPGA has undergone radiation tolerance qualification and these studies are outlined in Section 3.2. Finally, the ˇ performance of Level-0 interface modules when reading out Cerenkov photon signals is discussed in Section 3.3. 6
3.1
3.1.1
Laboratory tests
Signal–to–noise calibration
A crucial specification that the board must meet is to not contribute additional noise to that generated within the LHCBPIX1 ASIC, which would compromise the detector efficiency. The silicon signals for a single photoelectron are around 5,000 e− , though with charge sharing amongst pixels this can be reduced to as low as 2,500 e− [4]. Therefore, the signal size to which the readout electronics must be sensitive is specified to be 2,000 e− , with a channel-to-channel spread less than 200 e− . Furthermore, noise-induced signals should occur at a rate less than 1 in 10,000 events. To measure the pixel thresholds in the LHCBPIX1 ASICs, 100,000 events at each threshold setting of the pixel discriminator are taken. The minimum threshold which satisfies the noise-rate criterion is selected as the operating value for the discriminator. The threshold in terms of number of e− is then calibrated for each pixel using test pulses generated within the LHCBPIX1 ASIC at the input to the preamplifier. The magnitude of the test pulse is controlled by two reference voltages provided by the PILOT ASIC. The signal is varied from 0 to 2000 e− in 100 e− increments. One hundred events are taken at each point and the efficiency, defined as the number of hits registered by the pixel divided by the number of calibration pulses sent, calculated. The efficiency as a function of test-pulse magnitude is fit with a cumulative error function 7 (S-curve). The mean of the S-curve, which corresponds to 50% efficiency, is taken as the e− threshold of each pixel. An example of a threshold distribution for the 1,024 pixels read out with a Level-0 interface module is shown in Fig. 7; the mean and r.m.s. of 1,027 and 77 e− , respectively, is typical. A production cohort of fifty boards is tested in this manner and the r.m.s.’s of pixel measurements from all the boards are compared. Any boards with r.m.s. greater than three standard deviations above the mean r.m.s. are considered noisy and would be excluded from mounting in the RICH system. A distribution of threshold widths for one production cohort is shown in Fig. 8. Of the 150 boards produced and tested so far, none have been found to compromise the thresholds of the LHCBPIX1-ASIC discriminators. The one outlier in Fig. 8 was the result of a dry solder joint between the PCB and the Hirose connector. Once the joint was repaired, the board passed this test.
R∞ 2 2 1 The cumulative error function is defined as erf (Q) = −∞ √2πσ e(Q−µ) /2σ dQ, where Q is the charge and µ and σ are the mean and width, respectively.
7
7
3.1.2
Optical transmission tests
As described in Section 2.4 the HPD data are transferred optically to the rest of the LHCb DAQ system. The data transmission integrity has been studied in detail [14]. The optical attenuation of the 100 m long fibres providing the Level–0 interface module-to-DAQ link has been measured, including all interconnections of the fibres. Fig. 9 is a schematic of the link with all the interconnections indicated. Fig. 10 shows the power output from the twelve 100 m test links as a function of of the GOL ASIC current used to drive the VCSEL; this current is approximately proportional to the optical power produced by the VCSEL. Also shown are the maximum and minimum power expected given the attenuation specification of the fibre and connections. All measured values lie within the expected range. At the proposed operating current for the GOL ASIC of 2 mA, the optical power from the link is well within the 0.03 to 0.65 mW dynamic range of the optical receiver 8 of the DAQ electronics. The bit error rate (BER) in the data transmission is specified by LHCb requirements to be less than 10−12 . The BER is measured by counting any errors flagged by the 8-bit by 10-bit encoding with the DAQ electronics. Given the very low rates of BER it is safe to assume that an error in an 8-bit word is induced by a single bit error. Tests were run with 1013 bits transferred from the Level–0 module and the single bit errors counted. For the nominal transmitter settings no errors were detected. Running a test until such errors were observed may have taken several weeks or months of continuous running. Therefore, to expedite the tests, an optical attenuator was introduced to the fibre optic link and the attenuation was increased until errors were observed. Measurements of the BER at several different attenuations are shown in Fig. 11. The BER is then extrapolated linearly to the attenuation of the final system. This indicates that the BER for the Level–0 interface module optical link system will be less than 10−15 . This rate does not include any radiation induced errors which are discussed in Section 3.2.
3.1.3
Thermal testing
Four production boards were operated in an environmental control chamber to test their performance as a function of temperature. The temperature was cycled from ∼ 20◦ C to 60◦ C, well above the operational temperature of the RICH system, while the boards were transmitting test patterns generated by the PINT FPGA. The cycles took 3 to 4 hours. No component failures or data transmission errors occurred. One board had its temperature elevated to 80◦ C where it continued to operate successfully. 8
HFBR782, Agilent Technologies Inc. Headquarters, 395 Page Mill Road, Palo Alto, CA 94306, United States.
8
Every Level-0 interface module produced is baked for 12 hours at 50◦ to stress the board and accelerate early failure of weak solder joints on the board. Any failures are identified during the tests described in Section 3.1.1.
3.2
Radiation tests of the PINT FPGA
The anticipated maximum radiation dose to be received by a Level–0 interface module is 20 krad over the 10 year lifetime of LHCb. The TTCrx, GOL, QPLL, CRT4T and PILOT ASICs have been tested successfully beyond this dose. Hence, the PINT FPGA was the only component that had to be tested specifically for the Level–0 interface module. The ACTEL AX1000 FPGA, on which the PINT ASIC has been implemented, has been radiation tested with γ-ray and heavy ion exposures [15] and neutron exposures [16]. However, no tests had been performed with charged particles, which are expected to dominate the dose received in the LHCb RICH detectors. Therefore, a dedicated test was performed using a 68 MeV proton beam at the Cyclotron Research Centre at Louvain-la-Neuve, Belgium. Four AX1000 FPGAs were programmed with three 8-bit 40-deep shift registers. These utilised around 25% of the devices’ flip-flops, which is equivalent to the fraction used by the PINT FPGA. The same test sequence was supplied to all three registers at 40 MHz; two-third majority voting at the end of the registers identified any radiation-induced single-event upsets (SEUs) in the device. The integrated dose received and the number of SEUs observed for each FPGA are given in Table 1. The results indicate that approximately one SEU would be expected over the 10 year lifetime of LHCb. There were no pathological failures of the FPGA observed during this test nor those presented in Refs. [15] and [16]. FPGA
Integrated flux
Dose
SEUs
(1011 p/cm2 )
(kRad)
1
1.6
20
0
2
1.6
20
1
3
1.9
24
3
4
12.5
156
6
Total
17.6
220
10
Table 1 The results of the radiation tests of the ACTEL AX1000 fuse-link FPGA. The flux of protons, the dose and number of SEUs observed for each FPGA and the total are given.
9
3.3
Beam tests
Pre-production boards with near identical layout and PINT FPGA firmware to the final production module have been evaluated in a test beam. Photon signals ˇ from a prototype Cerenkov detector in an identical configuration to RICH 2 were read out with HPDs operating at 40 MHz [17]. Three modules read out ˇ an array of six HPDs which detected Cerenkov rings from CERN PS beams of 10 GeV/c charged pions and electrons . Both N2 and C4 F10 were used as ˇ Cerenkov radiators. The integrated distribution of HPD hits from ∼ 100, 000 π ± events with the C4 F10 radiator is shown in Fig. 12; the superposition of ˇ Cerenkov rings is clearly visible. The number of photoelectrons per event for a N2 ring centred on a single HPD was found to be ∼ 10, which was in good agreement with the number predicted by a GEANT4 [18] simulation. These tests demonstrate the excellent performance of the Level-0 interface module in a realistic system environment.
4
Conclusions
The Level-0 interface module for the LHCb RICH detectors has been described. This module integrates a pair of HPDs to the LHCb DAQ and control systems. Rigorous laboratory tests show that the modules match the noise, radiation and data quality specifications. The excellent performance has been ˇ further corroborated by beam tests where single Cerenkov photon signals have been detected efficiently.
5
Acknowledgements
The authors would like to thank Paolo Moreira for his assistance with the TTCrx, GOL and QPLL ASICs, Giovanni Anelli and David Price for assistance with the PILOT ASIC testing and our LHCb collaborators who worked on the RICH test beams. We would like to thank Vincent Bobillier, Jorgen Christiansen and Richard Jacobsen for advice and assistance throughout the design and production of the module. We would also like to thank the reviewers of the Level-0 interface module design: Jorgen Christiansen (Chair), Vincent Bobillier, Dominique Breton, Guido Haefli, Paolo Moreira and Richard Jacobsen. 10
References
[1] LHCb Technical Proposal, LHCb Collaboration, CERN/LHCC 98-4 (1998); LHCb Reoptimized Detector Design and Performance, LHCb Collaboration, CERN/LHCC 2003-040 (2003). [2] LHCb RICH Technical Design Report, LHCb Collaboration, CERN/LHCC 2000-0037 (2000). [3] M. Moritz et al., IEEE Trans. Nucl. Sci. NS-51 (3) (2004) 1060. [4] K. Wyllie et al., Nucl. Instr. and Meth. A 530 (2004) 82. [5] IEEE Std 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture, http://standards.ieee.org/reading/ieee/std public/description /testtech/1149.1-1990 desc.html. [6] D. Breton et al., A Serial Protocol for the Experimental Controls System of LHCb Experiment, https://lhcb.lal.in2p3.fr/Specs/Documentation/Specs4.0.pdf. [7] I2 C bus specification, Philips Semiconductors document, 9398 393 40011. [8] J. Christiansen, A. Marchioro, P. Moreira and T. Toifl, TTCrx V3.0 Reference Manual, CERN/EP/MIC 1999, http://ttc.web.cern.ch/TTC/TTCrx manual3.0.pdf [9] P. Moreira et al., Proceedings of the 7th Workshop on Electronics for LHC experiments, CERN-2001-005 (2001) 145. [10] P. Moreira et al., GOL Reference Manual, http://proj-gol.web.cern.ch/proj%2Dgol/manuals/gol manual.pdf [11] A. X. Widmer and P. A. Franaszek, IBM J. Res. Develop., Vol. 27 No. 5 (1983). [12] P. Moreira, QPLL Manual, http://ttc.web.cern.ch/TTC/TTCmain.html#QPLL. [13] A. Kluge et al., Proceedings of the 7th Workshop on Electronics for LHC experiments, CERN-2001-005 (2001) 95. [14] A. Powell, Overview of the RICH Optical Data Link and Evaluation of the Optical Attenuation, CERN-LHCb-2006-003 (2006). [15] J. J. Wang et al., IEEE Trans. Nucl. Sci. NS-50 (6) (2003) 2158. [16] iRoC Technologies, Overview of iRoC Technologies’ Report: Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances. http://www.actel.com/documents/OverviewRadResultsIROC.pdf . [17] M. Adinolfi, Nucl. Instr. and Meth. A553 (2005) 328. [18] S. Agostinelli et al., Nucl. Instr. and Meth. A506 (2003) 250.
11
(b)
(a)
Fig. 1. Schematic sections of (a) RICH 1 and (b) RICH 2.
12
Fig. 2. A photograph of a fully integrated column for RICH 2. Eight Level-0 interface modules service sixteen HPDs. The modules are centrally placed and connected directly to the HPDs, which are on the left-hand side of the column.
13
Data TFC signals Power supplies
JTAG control signal I2C control signal TFC fibre Kapton cables
QPLL and crystal Data fibres to DAQ
TTCrx
GOL1 and VCSEL GOL2 and VCSEL
Pixel Interface FPGA (PINT)
2×CRT4T
SPECS slave
Power supply filters
Analogue PILOT
Base power supply
Fig. 3. A schematic of the Level-0 interface module.
14
HPD1 HPD2
Fig. 4. A photograph of the Level-0 interface module. The numerically labelled components are: (1) TTCrx ASIC, (2) GOL serialisers, (3) QPLL, (4) PINT FPGA, (5) Analogue PILOT ASIC, (6) Truelight optical receiver, (7) VCSEL optical transmitters and (8) Hirose connectors.
15
Power supplies and filters
JTAG
JTAG PINT interface
PILOT: DAC and analogue references
GOLsand and GOLs optical optical transmitter transmitter
TTCrx
TTC decoder
Link test pattern generation
Control from FIFO JTAG level translator
Calibration and trigger
FIFO with bunch counters and event type
32×32-bit data words and 3×32-bit header and trailer words
Latch
HPDLHCBPIX1 LHCBPIX1ASICs ASICs HPD
Fig. 5. A schematic of the main blocks of the PINT FPGA and its interaction with other components. The key of connection types is given in Fig. 3
16
A
Output
B
C
Fig. 6. The gate-level implementation of the triple-voting logic used by the PINT. If two or more of A, B and C are 1 then the output is 1.
17
Entries / 20 e-
120
Mean
1027
RMS
76.59
100 80 60 40 20 0 600
700
800
900
1000
1100
1200
1300 1400 Threshold (e- )
Fig. 7. The distribution of pixel thresholds measured for a typical LHCBPIX1 ASIC and Level–0 interface module.
18
Entries / 25e-
25
χ2 / ndf = 4.289 / 4 Constant 17.79 ± 3.45
20 Mean
89.74 ± 5.91
Sigma
29.85 ± 5.79
15
10
5
00
50
100
150
200
250
300 350 RMS (e - )
Fig. 8. The distribution of threshold-distribution r.m.s’s for a cohort of production Level–0 interface boards tested with the same LHCBPIX1 ASIC.
19
Fig. 9. A schematic of the fibre optic link between the Level-0 interface module and the off-detector electronics. The various interconnections and fibre lengths are indicated.
20
0.9 Channel 1
0.8
Channel 2 Channel 3
Optical Power (mW)
0.7
Channel 4 Channel 5
0.6
Channel 6
0.5
Channel 7 Channel 8
0.4
Channel 9
0.3
Channel 10 Channel 11
0.2 Channel 12 Max Theory
0.1
Min Theory
0 0
2
4
6
8
10
12
GOL Bias Current (mA)
Fig. 10. The output power for 12 prototype optical data links including all connections as a function of the GOL ASIC current that drives the VCSEL. The minimum and maximum expected from the component tolerances are also shown.
21
χ2 / ndf Gradient Offset
log(Bit Error Rate)
-10 -10.5
94.09 / 4 -4.169 ± 0.1384 -67.14 ± 1.888
-11 -11.5 -12 -12.5 -13 -13.6
-13.4
-13.2
-13
Additional Attenuation (dB)
Fig. 11. The measured BER as a function of optical attenuation of the link for the Agilent receiver used on the RICH off-detector electronics.
22
ˇ Fig. 12. The Cerenkov ring measured by an array of 6 HPDs read out with 3 Level–0 interface modules. The radiator used was C4 F10 and ∼ 100k π ± events are superimposed.
23
