Linear Averaged and Sampled Data Models for Large Signal Control ...

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LINEAR AVERAGED AND SAMPLED DATA MODELS FOR LARGE SIGNAL CONTROL OF HIGH POWER FACTOR AC-Dc CONVERTERS __________________________________________ LS AUTHORS)

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K. Mahabir G. Verghese

A.ptoor.6

LIDS-P-1968

Technical Report,

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AFOSR-88-0032 2304/Al 61102F

Thottuvelil A. Heyman

oftGAZATO NAMEl(S) AND A0OAISS(AS)

Massachusetts Inst of Tech. Lab. for Electromagnetic & Eectronic Systems CAmbridge, MA 02139

L.PtRORMMA ORGAN"ZTiaON Digital Equipment Corp.REOTNmI Maynard.

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IEEE Power Electronics Specialists Conference, San Antonio, June 1990 LIDS-P-1968

LINEAR AVERAGED AND SAMPLED DATA MODELS FOR LARGE SIGNAL CONTROL OF HIGH POWER FACTOR AC-DC CONVERTERS K. Mahabir"

G. Verghese"

J.Thottuvelil +

A. Heyman +

Laboratory for Electromagnetic and Electronic Systems, MIT + Digital Equipment Corporation, Maynard.

Abstract

This paper shows that the Lzrg signal behavior of a popular family of high power fa tor c to dc power conditioners can be analysed via linear models, by uing squared output voltage as the state variable. The state equation for a general (constant power plus resistive) load is obtained by a simple dynamic power balance. T'ime invariant or periodically varying controllers, acting at the time scales of the line or switching periods respectively, can then be designed from the resulting averaged or sampled data models. Simulations and experiments corroborate the results. 1.

Introduction

Recently, there has been much work on designing control schemes for high power factor ac to dc converters, Scbjecht 111-13) discusses various topologies and control schemes for such converters. Subsequent work has largely focused on the scheme shown in Fig.1, using a boost converter whose input voltage v,,,(t) is the rectified ac waveform. The inner current loop specifies the switching sequence for the transistor to regulate the input current i,,(t) around a reference id(t) that is proportional to the input voltage. The outer voltage loop varies the proportionality constant k from cycle to cycle, to regulate the output voltage v,(t) about the desired level, Vj, Several recent papers discuss different approaches to designing the inner and outer loops. Hense and Mohan [4) use a hysteretic current control loop, and implement the voltage control loop digitally, using a simple PI (proportional-integral) controller, but some modeling aspects ae left unclear. Williams [5] designs a controller using the small signal 'transfer function' between commanded input current and output voltage. While his analysis contains insight into the operation of the circuit, it is mathematically incorrect since itisbased on Laplace transform operations on equations with time varying coefficients, even though the conditions for quasistatic analysis do not hold. A correct small signal averaged model and associated control design are provided by Ridley 161.

The present paper develops large signal linear models

for the voltage loop. Specifically, we develop continuous time averaged models at the time scales of the switching period and the input period, and also derive their sampled data counterparts. These models yield efficient simulations, and enable the simple design of control schemes that permit recovery from large perturbations away from the operating point. Section 2 describes the operation of the inner current loop shown in Fig. I. Section 3 presents continuous time averaged and sampled data models for the dynamics of the outer voltage control loop. The con. tinuous time averaged models are verified in Section 4 by compariion with both the results of SPICE implementations of the models and experimental results for an actual ac-dc converter. Section 5 discusses the use of a sampled data model to design a digital controller for the outer loop, including PI control, and presents simulation resuts for the behavior of the full closed loop system. 2.

Current Loop Operation

The current loop is responsible for obtaining the high power factor by drawing a resistive current from the ac line. Any current mode control scheme may be used. The operation of one such scheme is illustrated by the simulation in Fig. 2. At the beginning of every switch. ing period, every Ts seconds, a decision ismade to have the transistor on or off, as required to force the inductor current towards the switching boundary, i:,,(t). This is a compromise between the usual constant frequency discipline and hysteresis band control. It provides a natural control implementation, given that the control is exercised periodically, and was shown in (71 to be efective in digital sliding mode control of the buck-boost converter. The commanded input current, i,ha(t), is set according to: i,(t)

k(t)v,(t)

(1)

E. where k(t) is determined by the voltage control loop. In usual practice, k(f) is held constant (or approximately

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costant) for the duration of the rectified input's period, T L. For the simulation in Fig. 2, we have assumed a constant power load, P and chosen parameter values as follows:

be considered constant over any interval of length TL, the resulting "TL-averaged" model is given by the linear first-order description

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The block diagram in Fig. 3(a) shows the transfer func-

L = 600,uH TS = IOpsec

C = 940pjF vi.(9) = Vlain(120si)l

P =

dy(t)/dt =-y()

V = 200volts

The value of k(t) in Fig. 2 equals 0.055. The power factor during this line cycle is calculated to be 0.977. The running average, i(t), of the input current over an f:-_T. n(u7)d7. It is interval T$ Is defined by tit) = reasonable to assume, when the current loop is working well, that i(t) = i,,,(t) = k(t)v(t). This will be a standing assumption in what follows,

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Voltage Loop Dynamic.

In this section, we obtain dynamic models for the outer control loop. We assume the load comprises a parallel of a constant power load P and a -esistor combination c b i ois R.

(3)

tion representation of (3). Notice that the term involving k 2(t) in (2) has disappeared, because our assumption of slowly varying k(t) causes the average value of d[k 2 (t)vj2.j/dt to be negligible. Even if k(t) is not slowly varying and this average is not negligible, it is often true that the term Ldtk 2 (t)v? 1/dt contributes little to the power balance in (2), because L Is small The model (3) already suffices to design linear controllers (e.g. PI controllers) for Large deviations in y(t) or F. To exploit the linear model ahove, the linear controller needs to operate on the squared output voltage. Otherwise a linear controller that acts on 0. itself can be designed on the basis of a small-signal linearization of (3), good control as innRde Ridiey [61 oto hngo u then ilas1) [5], but n Willims 6 and a only guaranteed for small perturbations of 0. from its desired nominal value, Vd. The linearized model is easily

To maintain sinusoida waveforms in each input cycle, we must keep k(t) constant over each cycle. Under this condition, it is natural to look for sampled data models and controllers. To obtain an SDM on the time scale of the input period T L, we can integrate (2) or (3) over T L, assuming that k(t) is essentially constant over intervals of length TL. The "TL-SDM" that results from (3) under the assumption that RC >> TL is shown below, with k(t) in the nt cycle denoted by k[n] and y(t) at the beginning of the n"%cycle by y[n]:

(t)]/dt(2)

This already shows that the use of vo(t) as the state variable, instead of the more common vo(t), leads to an essentially linearfirst-order model for large signal behavior. This observation has also been made by Sanders [8]. The model (2) corresponds, in effect, to averaging a switched model over the switching period, and we shall refer to it as the "Ts-averaged" model. Other averaged and sampled data models (SDM's) can be obtained from (2). If v.(t) is taken as the state variable, (2) is a nonlinear description; linearization yields a small signal pemodel, which possibilities is the starting riodically discussion of control (5]. point for Williams' varying

yIn+ nC)

1

- -/n

+

(Vkjn]-2P)

(4) (

Continuous Time TL-Averaged Models

the inner control successfully Hence, assuming sit) at that its comunanded value loop ,,,ft), the dymaintains namics of the boost converter is completely described by the single linear, time invariant difference equation (4), with state yinj and control kin]. If the input frequency

To obtain an averaged model on the time scale of the input period, average (2) over T L,, using the runninj average defined by 0(t) = . f -TL" w(u)du. Denote v.2 by 1. If the input frequency ripple in v.(t) is small, then V :. Assuming that k(t) varies slowly enough to

t,[n], tie squared ripple in v.(t) is small, then yjn] output voltage at the beginning of the nih cycle. If t'.{n], rather than v.[nJ, is taken as the variable to be modeled, we obtain a nonlinear model. Its linearization is a small signal time invariant model that turns out to be the same

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Sampled Data Models

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-

derived from (3) and is shown in Fig. 3(b). The tildes () denote perturbations from nominal. We have not represented the effects of perturbations in the line voltage amplitude V, since these are normally compensated 2 for by a feedforward that makes k proportional to I/V .

Continuous Time Ts-Averaged Model Ignoring switching frequency ripple in the output voltage, v.(t), and assmning that the inner curient loop maintains i(t) = k(t)v, i(t), conservation of power for the boost converter yields: - P 1 = k 2 (t)]/dt =kit)v,(t) - 2Ld[k 2 t)i 1 2

+ j(V k(t)

(5)

Using the models we have developed, It is quite straightforward to design a good PI compensator for this circuit, using either t.2(t) or v.(t) as the feedback signal. The particular test results shown in Fig. 4, however, correspond to using only integral compensation, with "= -. 076 J Vdt. Integral control contributes nothing to the damping of transients here, and is a very poor control cho4.e in this case, even though it provides insensitiv-

Note that zin] is not restricted to be small. An SDM at the time scale of the switching period is derived in a similar manner, by integrating (2) over the switching period Ts. Assuming that k(!) is constant over Ts, and that RC >> Ts, we get the "Ts-SDM" shown below. The time index q denotes the switching period, whereas the time index n in the TL-SDM denotes the input period

ity to constant disturbances (such as load uncertainties). However, the large oscillatory transients that result allow us make a clearer comparison with the predictions of ourtomodels than would have been possible with the small transients produced by good PI compensation. Our lnear averaged models (2) and (3) were derived a load comprising a constant power component P in parallel with a resistor R. The models can easily be extended to hand:. & c,u. source lcd., as In the test circuit, but then would no longer be linear. This is because a constant current load I. contributes the term -Ilv.(t) to the right side of the power balance equation (2), and this term involves V/VRt rather than v.(t). For the transients in Fig. 4, however, v,2(t) does not deviate excessively from Vd, so not much error would be incurred 3 t{)by its linearization at v!(t) if we replaced -I.V',(

as what Williams [5) obtains through heuristic and not vmy satisfying arguments. The regulation of v. about VI'can be accomplished by regulating v.2 about V1, as we show in Section 5. For oar purposes there, it is useful to develop an alternative model, using the state variable tin] defined by =

zjnI

v!in] - Vj

Combining (4) and (5) yields tin + 11 =

(

) tn

-

+ V 2T kin]

2T) -

+assuming

V2:

+ b1[r7]k[q] + b2[171kt'1] z[w, + 1] = z[,7j 2PTs

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(7)

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_

where the time varying input gains are given by:

2V I.vd _ I 2

2 V,

-

2(t) V.

(9)

The current source therefore behaves, to a first order (8approximation, as the parallel combination of a constant 2 2power load I.Vd/ and a resistor 2Vd/I,. ThL sin(2,r(q + 1)Ts/TL) - sin(2lrulTs/TL)]l Linearity of the model is not as important for simula- 2, "tion as for control design, so for the simulations in Figs. - ' Sand 6 we have used the nonlinear extensions of (2) and 5/TL). tsin2(i(,i+ 1)Ts/TL) - sinV(2T 6071 = C +-(3) that incorporate the current source load. However, differences are expected if the substitution significant no = Note that in steady state, the TL-SDM .# fes z[n+ 1 used instead, with a linear model. The results (9) is in and state te Wy cyclt. has a the Ts-SDM Zn . However, in Figs. 5 and 6 were obtained using SPICE implemendoes not satisfy ziq + 1] = z~i]. tations of the (extended) models; their 1st;ngs are given 4. Model Verification in the Appendix. The output voltage v.(t) is fed back, in both cases, through the same integral compensator used In this se)tion we compare the continuous time averfor the test circuit. aged models (2) and (3) with each other and with experThe match between the responses of the Ts-averaged imental data from a test circuLit model in Fig. 5 and the TL-averaged model in Fig. 6 The test circuit uses a Micro Linear ML 4812 power is excellent. Unlike Fig. 2, neither of these simulafactor controller chip to implement the control functions tions represents the details of the switching frequency shown in Fig. 1. The parameters of the test circuit are ripple, so they are very efficient to run. The TL-averaged L = lmH C = 410pF V = vx x 120volts model does not model the input frequency ripple either. so the corresponding simulation can take larger time The load is a square-wave current source switching besteps than the Ts-averaged model, for the same accutween 0.2A and 0.4A at a frequency of 0.5Hz. The output racy. The damping and oscillation frequency are what voltage is to be regulated at V = 386volts. we would expect from (3) for a resistive load of value bl',7

=

V1 -C Ts

3

R = 2Vd/I, = 3.86Kfl. For this load, the decay time constant for v,(t) under integral compensation is cornputed to be 0.63 sec, and the oscillation period is 75.5 ms. which are consistent with Figs. 5 and 6. T'he frequency of the oscillatory transients in Figs. 5 and 6 matches that of the test circuit transient in Fig. 4, but the damping is larger for the test circuit. This is probably the result of losses in the test circuit that have not been modeled.

The constant b is chosen to place the pole zi, = I - b at a desired location. Placing the pole at z,= 1/2 and initiating the output voltage with a 50% initial perturbation away from equilibrium results in the sampled output voltage transient shown in Fig. 8 for the model (13). The output voltage starts at v. = 173 volts and requires approxiniately 8 input periods to attain the desired level of Vj = 346 volts. The corresponding control signal r[n] is also shown. Before connecting the voltage loop to the current loop, S. Control Design the range of values of kin] specified by the voltage loop must be checked for consistency with the range allowed The design of an analog control (e.g. PI control) for by the current loop. If kin] is too large, then the inductor tam el Isnoar (3) tslin ee at tne. Fcorl eaw current will be unable to rise fast enough to follow the saple, it Is not bard to see that the P1 control law cmaddcrets()=ktv,() nti xml e p(t)vi,o(t. Inthis example commanded current better than I = -. 013[0.19. + f11odt] will perform much K = .055 results in the current response shown in kiln ] -pure integral control on the circuit in Section 4. The prepinteg otrol onme thuare-we crt nuSetio 4. dT Fig. 2. Further simulations demonstrate that for kin] < response to the same square-wave current source load as .5. the input current is able to follow its commanded .5lte inpt c uent l, follo its cinded before is shown in the TL-averaged simulation in Fig. 7. value iu(l) Consequently, for kin) in the vicinity of K Since analog control design is relatively familiar, we do nodiscuss itfurther here. Instead, we now illustrate theperform as expected. In desgno dif italrtro sheresa, weinowil the t n particular, for the transient in Fig. 8, the current loop design of digital control schemes, using the T -SDM in will perform as desired. (6) with a constant power load and the parameter values Figure 9 shows a detailed simulation of the response in Section 2. The controllers will feed back and regulte of the full closed loop system to an initial 50% perturbav, rather than vo. In steady state, z~n + 1] =in] = 0, tion away from the desired output voltage level, Vd = 346 so the constant control kin] = K required to maintain volts. As predicted by the sampled data voltage loop simequilibrium in steady state is seen from (6) to be: ulation in Fig. 8, the transient has decayed in about 8 K = 2P/V2 (10) input periods. In Fig. 9, each input period TL is approximately equal to 830 switching periods Ts. The power which varies as I/V 2 . However, we only know the non-ifactor corresponding to each cycle of the current response ial load power PN and the actual power is P = PN + . in Fig. 9 is shown in Fig. 10. The power factor in steady Consequently, let K = 2PN/V 2 . Rewriting the control state is close to the power factor of the open loop reas kin] = K + %In] reduces the state equation (6) to: sponse in Fig. 2. TL 2TL Figure 11 illustrates the response of the full closed loop zfn + 1] = zin) + kn) (-C)pr (11) system to an unanticipated step change in output power at t = 2000. At that time, Pis stepped from 0 to IPN, so that the power in the load steps by 50% from 1100 watts State Feedback to 1650 watts. The output voltage attains a new cyclic steady state, but exhibits a dc offset of approximately 30 Specifying the control to be in state feedback form, volts, or 9%. [n] = n] (12) State Feedback with Integral Control

( )

yields the closed loop model

In order to correct for the effect of such uncertainties in the load power, integral control must be incorporated into the voltage loop control scheme, as shown in Fig. 12. The state equations for the outer loop are given by:

2T. r[n + I]= (1 - b)zln] -

r

'

(13)

Note that rjn] is inversely proportional to V. The solution for zIn] is given by the standard variation of constants formula in discrete time: z[n]

qjn + 1] [n + 1]

(1 - b)"z[0J +

(1 - b)"-1-1

=

=

q[n] + n] (15) -bq[n] + (1- bp)rln] - (-L)7(16)

The pole locations of this system are given by: +

(14)

ZP

4

=

(I - bp/2) 1

(bp/2) - bj

(17)

Seleting the "best" bp and II is complicated by the limitations on the control kfnJ noted earlier. For the purpose

of demonstrating the performance of the outer loop withL

=

integral control, the poles will be placed at zp This chuice result: in a small enough kin] and a reasonhlv fast rpsponse. The response of the preceding second order sampled data model for the voltage loop, after a 50% perturbation in output voltage, is shown in Fig. 13. It has approximately the same settling time and a slightly greater overshoot than the first order voltage loop response in Fig. 8. The response of the full dosed loop system with in. tegral control to a 50% initial perturbation in output voltage is shown in Fig. 14 and is consistent with the sampled data outer loop response in Fig. 13. The output voltage reaches its desired level of 346 volts in approximately 8 line periods with a peak overshoot of about 40 volts. The response to a 50% step change in load power at t = 2000 is shown in Fig. 15. With integral control, the output now recovers and requires a settling time of only 8 line periods. 6.

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Vd Figure 1: Boost Converter with Current and Voltage Control Loops

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might be value in feeding back and regulating the squared output voltage of high power factor ac-dc converters. This would permit linear controllers to handle large per. turbations in the output voltage, as demonstrated in Sec. tion 5. The required control functions would compare in

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The models we have developed suggest that there

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style and complexity with what is presently available on single-chip controllers. It may also be of interest in future work to study the use of periodic controllers [2], using the models (2), (7) or (8). Apart from suggesting new control possibilities, our development clarifies the relationships among different modeling and simulation approaches for such converters.

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Acknowledgment

I/.Y Work partially supported by DEC, by the Air Force Offce of Scientific Research under Grant AFOSR-S& 0032, and by the MIT/Industry Power Electronics Collium. The authors would like to thank David Chin of DEC for his probing questions and other help. Correspoodence may be addressed to George Verghese, Room 10-469, MIT, Cambridge, MA 02139, Tel (617) 253-4612.

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References [1' M.F. Schlecht, "A Line Interfaced Inverter with Ac. tive Control of The Output Current Waveform", PESC, 1980, pp.234-241.

Figure 3: Transfer Function Representation of TL.-Averaged Model (a) Large Signal (b) Small Signal

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Figure 4: Transient Response of Test Circuit with Integral Control

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Figure 11: Response ofFull Closed Loop System to Step

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F'ure 9: Response of PuFl Closed Loop System to Initia Perturbation

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Loop System with

121 M.F. Schlecht, "Time-Varying Feedback Gains for Power Circuits with Active Waveshaping", PESC, 1981. pp.5 2 -59 .

131M.F. Schiecht, "Novel Topological Alternatives to the Design of a Harmonic-Free Uytility/DC Interface", PESC, 1983, pp.206-216.

[41 C.P. Henze and N. Mohan, "A Digitally Controlled AC to DC Power Conditioner that Draws Sinusoidal input Current", PESO, 1986, pp 531-540.

151 J.B. Williams, "Design of Feedback Loop in Unity Power Factor AC to DC Converter", PESC, 1989, pp.95 9 -96 7 . "~(0

[6] R.B. Ridley, "Average Small-Signal Analysis of the Boost Power Factor Correction Circuit", VPEC Seminar, 1989, pp.108.120

171S.R Sanders, G.C. Verghese, and D.F. Cameron, no

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"Nonlinear Control Laws for Switching Power Converters", 25th IEEE Conference on Deciand Control, Athens, December, 1986, also in Control-Theory and Advanced Technology, 5, Dec. 1989. S.R. Sanders, "Effects of Nonzero Input Source Impedance on Closed-Loop Stability of a Unity Power Factor Converter", PCIM-Power Conversion,

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Los Angeles, Oct. 1989.

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Figure 1S: Response of Full1 Closed Loop System with Integral Control to Step Change in Load

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APPENDIX SPICE Inputs Listing df T.averaged Model

vurs 1 Wc 1.0 aISK a 12 Of 0 hilty gala aed, outpst xi 1: : 160 & i. Is I.* .09M. s

in..muco am m5 W? P01 STACK " LiM leis of WKlUli*531 test CiSCSit (with Mod"'" " vales@) - aeastaat Curres$ lead MUACa56 an 0. 170. 00. 5056OfW 0 1 34 a063 ,M i t

*

i** 0 kov]X**2

Stage

AO .A3M0

OWN-I) 11. 10.0 2- VIC .wlou nin *l-a211.5, ITL4010M0 V& MW01~m (s40) 1(1) TOO0 1(2) TOO5

V623) 1(50.53

SPICE Imput Listling of Tj,.averaged Model

is

51YM 0 21 PI1.1() 10 02 00. 0. 0. 0. 1. *1662 1 2 0 PO1.1(W 2 0 0. 0. 1. 21.2 019 * C1002) (M*3.2) GMU2 0 13 MY .(2) 12 0 10 0 0. 0. 0. 0. 1. L13 1.0 1X GEY 21 013 00.5 0 731 teatmt-currest lead. too YCC5. wit l5 i Sfl1flh 21 0 pely(2) 40 0 30 0 0. 0. 0. 0. 1. 121U5 30 0 P01. 0.2 0.4 3.175 1005 100 1. 2. Urn=A 80 0 19 iga210 PC 0. 1513 0 25 i 2. law as2a01s C 250a 4109 10148.2 * Cquare reetla vG** wSee cm 40 0 PLM) 25041 00. 1um -IMa "a5 40 0 UP 41 0 PO1.1(2) 40 0 40 0 0. 0. 0. 0. 1. Up 410am 1C 0 Output fediback Si 44 04"01.

nus oom wr pown gsis 0 1imuutes of m~ies test gircalt (Wlu Modified 0 Vale") - cameteat-eit?it Is" 1U 10 mc I"0 LIE 1 0 10 0 Y1e.2 (no welue8) EDM 100 pelv(l) 1 00. 0. 1. MmV 10016o e* h'tase2

ErfM 11 0 P01.1() 10 0 2 00D. 0. 0. 0. 1. w1 et& * o fe cosn-ars leA. ee v. ULDA11 U PLT) 15053000C. 0. 0. 0. 1. IfLOAO 30 0 F01.5 0.2 0.4 1750 10M5 100s 1. 2. Uinoa 30 a 1x MW32 12 016 0 (0"0010900e2 fv 3'D0 0 VTM 12 021 00. 16 -10 Is 30 0um 31 21 0 POL.7() 20 0 15 0 0. 0. 0. 0. 1. no2 0 u cis @41ow IBM is o too 0631 0 is15201.

22 so04.72 Ur 50 12 0. 47W IC-4.91 1.1S so00 52 a 0 1040" 1031 0 be 6.0 ..650 06. 0

is ic OuptfebcVI15 1VSC 194"5s n 44 s s 325so0 4.739

" (matIplle gin 0 1.lt3/UAsae* (21M3) * Dame) " wee. boull a teielee resister few Wltlpliuf. Se "1 0 resistance usned to SWive currest referoae if lime 1"4. 313 cmmmt trumaf Ome priinl7 to #s.ene"" turms retie. M04 *Soame a surmet-Sraaferm barden resister a 320 a0 0.0120

11 61 500 0 U50 548125 SI 0t a VC.0 WOE asO 35D6.0 441so~ u5 12 (tipllew gels * amt/taINO * (31/32) * aesz) 0 torn. bmis a terastlea resister ferwimtilier. * Saeft a rueletme uined to &wive rres reoe.. tm ia.Us. SuIM w gursim trafeme primary to e 6#468Mi tura tis. sAd a bass" a rettr~ae buden resister, is 2 0162 0 0.0120 301to merle I eaPr 41ermasnt itng P e Ole uts u.cl o.M. se

=20

0to

IC i=4

0.01s A0.1

(to s p mpenre vavewem. UM1 00 0 2 0 1 00. 0. 0. 0. 1, 21M so 0 is -80=1 JW1s51 2 a4 aW 2 Is 3. iwewtsag iap"t. 2 is 1,31*5ipn mepS, a Is eve. 01. -10= 3 si gond. &4is s00aste a*te Up 90311) NOS .30W. 3.n 1 2 1644 ~ ~~11A 000 10.-3 0. 0 GOOD ~ ~ slwM5idls& ~ ~ **" ~ efsI $a".~ ~~ 111.4.1000 S. 0010011. -OPTIONS s so41m a(in) dads" plse * 0 1 Slew (S)VOT mPWa m1 S I 1 2 1. is 303as (Cl - 1/(we1) al a a i67.817 * n.Y.

.ilyci

10