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Linearized Programming of Memristors for Artificial Neuro-Sensor Signal Processing Changju Yang and Hyongsuk Kim * Department of Electronic Engineering, College of Engineering at Chonbuk National University, 567 Baekje-daero, Deokjin-gu, Jeonju-si, Jeollabuk-do 54896, Korea; [email protected] * Correspondence: [email protected]; Tel.: +82-63-270-2477 Academic Editor: Vittorio M. N. Passaro Received: 18 July 2016; Accepted: 11 August 2016; Published: 19 August 2016

Abstract: A linearized programming method of memristor-based neural weights is proposed. Memristor is known as an ideal element to implement a neural synapse due to its embedded functions of analog memory and analog multiplication. Its resistance variation with a voltage input is generally a nonlinear function of time. Linearization of memristance variation about time is very important for the easiness of memristor programming. In this paper, a method utilizing an anti-serial architecture for linear programming is proposed. The anti-serial architecture is composed of two memristors with opposite polarities. It linearizes the variation of memristance due to complimentary actions of two memristors. For programming a memristor, additional memristor with opposite polarity is employed. The linearization effect of weight programming of an anti-serial architecture is investigated and memristor bridge synapse which is built with two sets of anti-serial memristor architecture is taken as an application example of the proposed method. Simulations are performed with memristors of both linear drift model and nonlinear model. Keywords: weight programming; complimentary action; anti-serial architecture; linearity weight programming; complimentary action; anti-serial architecture; linearity

1. Introduction Memristor is a new circuit element postulated by Leon Chua in 1971 [1] and fabricated recently by the Stanley Williams group [2] from Hewlett-Packard (HP). It exhibits excellent features of both memory [3–6] and neuromorphic applications [2,7–11]. For memory applications, it is nonvolatile and has an extremely small size of a few nanometers [3–5]. For neuromorphic applications, it has features of pulse-based operation and adjustable resistance, which are ideal for tuning the synaptic weights of neuromorphic cells [2,7–10,12,13]. A convenient way of programming a memristor with a certain value is by applying a rectangular voltage pulse whose magnitude of voltage is constant during pulse period and zero during non-pulse period. However, the variation of its resistance is a nonlinear function of the applied voltage pulse width even it is a linear model. We call the resistance of memristor memristance. Fortunately, when two memristors with opposite polarities are combined together, the nonlinearity of memristance is reduced dramatically due to the complementary action of two memristors. Kim et al. presented an efficient weighting circuit for synaptic operation by building a bridge structure combining two opposite anti-serial memristor circuits [7]. Waser’s group reported a fabrication result of complementary resistive switch (CRS) consisting of two back-to-back (anti-serial) memristive elements for the construction of large passive crossbar arrays by solving the sneak path problem [14]. Later, the CRS architecture has been further investigated via an analytical approach [15]. T. Liu et al. also reported the Current-Voltage (I-V) characteristics

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Waser’s group reported a fabrication result of complementary resistive switch (CRS) consisting of two back-to-back (anti-serial) memristive elements for the construction of large passive crossbar arrays by 16, solving the sneak path problem [14]. Later, the CRS architecture has been further Sensors 2016, 1320 2 of 15 investigated via an analytical approach [15]. T. Liu et al. also reported the Current-Voltage (I-V) characteristics of antiparallel resistive switches (APRS) that strongly depend on the parameters of of antiparallel resistive [16]. switches (APRS) that strongly depend on the parameters of the individual the individual switches switches [16]. In this paper, we propose a linearized programming method utilizing an anti-serial In this paper, we propose a linearized programming method an memristor anti-serial architecture. architecture. To program a target memristor, the same type of a utilizing subsidiary is prepared To program a target memristor, the same type of a subsidiary memristor is prepared and connected to and connected to the target memristor in series with opposite polarity. Since composite the target memristor in series with opposite polarity. Since composite memristance of the anti-serial memristance of the anti-serial circuit is a constant value, the current through the circuit is constant. circuit is a that constant value, the current through theindividual circuit is constant. It follows thatfunction the memristance It follows the memristance variation of the memristor is a linear of pulse variation of the individual memristor is a linear function of pulse width since the memristance variation width since the memristance variation is a linear function of charge. is a linear function ofofcharge. The principle such linear programming is explained theoretically and verified via The principle of such programming theoretically andisverified viaelement simulations simulations in this paper.linear Section 2 describesis aexplained reason that memristor a useful for in this paper. Section 2 describes a reason that memristor is a useful element for building a neural building a neural synapse. Section 3 demonstrates nonlinearity in programing of a memristor with synapse. Section 3 demonstrates nonlinearity in programing of a of memristor with rectangular voltage rectangular voltage pulses. To resolve the nonlinearity problem voltage controlled memristor, an pulses. To resolve the nonlinearity problem of voltage controlled memristor, an anti-serial architecture anti-serial architecture is proposed in Section 4. Simulation results to support the proposed idea are is proposed in Section 4. Simulation to support the proposed idea are provided in Section 4. provided in Section 4. Section 5 is the results conclusion. Section 5 is the conclusion. 2. Memristor as a Promising Element for the Implementation of Neural Synapses 2. Memristor as a Promising Element for the Implementation of Neural Synapses In biological neural systems, each neuron is connected to other neuron through a synapse In biological systems, connected other neuron through a synapse between them. Aneural synapse is a each very neuron specialisplace in a to neural cell, where memory andbetween analog them. A synapse is a very special place in a neural cell, where memory and analog multiplication multiplication are performed. Figure 1 shows input and output connections of a biological neuron are performed. Figure 1 shows input as and output connections biological where inputs where inputs (dendrites) are denoted “b” and output (axon)ofisadenoted as neuron “a”. Typically, about (dendrites) are denoted as “b” and output (axon) is denoted as “a”. Typically, about 10,000 inputs 10,000 inputs (dendrites) are connected at a single neuron. Thus, the same number of synaptic (dendrites) are connected at a single neuron. the same number ofnumber synapticofweights needed in in weights is needed in a neuron. Therefore, theThus, implementation of huge neural is synapses a neuron. Therefore, the implementation of huge number of neural synapses in a chip is a big roadblock a chip is a big roadblock for the development of an artificial neuron system. To make matters worse, for the development artificial neuron system. To make one 2. synaptic circuitthe is one synaptic circuit of is an composed of many transistors as matters shown worse, in Figure Therefore, composed of many transistors as shown in Figure 2. Therefore, the implementation of an artificial implementation of an artificial neural system that mimics a biological neural system is seemingly far neural system that mimics a biological system is seemingly far beyond our reach with the beyond our reach with the current circuitneural technologies. current circuit technologies.

Figure 1. Inputs and outputs of a biological neuron where inputs (dendrites) are denoted as “b” in the figure and outputs (axons) are denoted as “a”. Since one synapse is connected at each input (dendrite), a huge number of synaptic weights are composed at a neuron.

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Figure 1. 1. Inputs Inputs and and outputs outputs of of aa biological biological neuron neuron where where inputs inputs (dendrites) (dendrites) are are denoted denoted as as “b” “b” in in Figure the figure and outputs (axons) are denoted as “a”. Since one synapse is connected at each input the figure and outputs (axons) are denoted as “a”. Since one synapse is connected at each input Sensors(dendrite), 2016, 16, 1320 3 of 15 huge number number of of synaptic synaptic weights weights are are composed composed at at aa neuron. neuron. (dendrite), aa huge

Figure Figure2. 2.An Ananalog analogmultiplier multiplieremployed employedto toimplement implementCellular CellularNeural NeuralNetworks Networks[17,18]. [17,18]. Figure 2. An analog multiplier employed to implement Cellular Neural Networks [17,18].

Figure 333 shows shows aaastructure structureof ofaaamemristor memristorfabricated fabricatedsuccessfully successfullyby byHP HP[2]. [2]. In In an an HP HPTiO TiO222 Figure Figure shows structure of memristor fabricated successfully by HP [2]. In an HP TiO (Titaniumdioxide) dioxide)memristor memristormodel model[2], [2],an anundoped undopedregion regionwith withhighly highlyresistive resistiveTiO TiO222and andaaadoped doped (Titanium (Titanium dioxide) memristor model [2], an undoped region with highly resistive TiO and doped region with a highly conductive oxygen vacancy TiO 2−x layer are sandwiched between two platinum region layer are sandwiched between two platinum region with with aa highly highlyconductive conductiveoxygen oxygenvacancy vacancyTiO TiO2− 2−x platinum x layer electrodes. When When aa voltage voltage or or current current signal signal is is applied applied to to the the device, device, the the border border line line between between the the electrodes. When electrodes. device, border line between the doped and and undoped undoped layers layers shifts as function ofofthe the applied voltage oror current. In consequence, consequence, the doped undoped layersshifts shiftsas asaaafunction functionof the applied voltage current. In consequence, doped applied voltage or current. In the resistance between the two electrodes is altered. Figure 3b,c are equivalent circuits. the resistance between electrodes is altered. Figure equivalent circuits. resistance between the the twotwo electrodes is altered. Figure 3b,c3b,c areare equivalent circuits.

(a) (a)

(b) (b)

(c) (c) Figure 3. 3. (a) Structure Structure of TiO22 memristor, memristor, TiO2−x 2−x and TiO2 layers are sandwiched between two Figure andand TiOTiO 2 layers are sandwiched between two Figure 3. (a) (a) StructureofofTiO TiO2 memristor,TiO TiO2− x 2 layers are sandwiched between platinum electrodes. When a voltage/current is applied, its memristance is altered; (b) (b) equivalent equivalent platinum electrodes. When a voltage/current is applied, itsitsmemristance two platinum electrodes. When a voltage/current is applied, memristanceisisaltered; altered; (b) equivalent circuit and (c) symbol of the Memristor. circuit and and (c) (c) symbol symbol of of the the Memristor. Memristor. circuit

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In the TiO2 memristor, a thin titanium dioxide (TiO2) layer and a thin oxygen-poor titanium dioxide (TiO2−x) layer are sandwiched between two platinum electrodes. When a voltage or current is In the TiO2 memristor, a thin titanium dioxide (TiO2 ) layer and a thin oxygen-poor titanium applied to the device, the resistance between the two electrodes is altered. dioxide (TiO2−x ) layer are sandwiched between two platinum electrodes. When a voltage or current is The memristor is defined [7] by applied to the device, the resistance between the two electrodes is altered. d dt The memristor is defined [7] by v(t )  R(t )i (t )   i (t ) (1) dt dq dϕ dt v ( t ) = R ( t )i ( t ) = · i (t) (1) dt dq at time t. Thus, the resistance can be where ϕ(t) and q(t) denote the flux and charge, respectively, interpreted as the slope at the operating point = at time t on the memristor _ curve. If the where ϕ(t) and q(t) denote the flux and charge, respectively, at time t. Thus, the resistance can be curve is nonlinear; the resistance will vary with the operating point. _ interpreted as the slope at the operating point q = qQ at time t on the memristor ϕ_ q curve. If the ϕ_ q ( ) , the resistance of the memristor, called the Since the flux ϕ is defined by ( ) = curve is nonlinear; the resistance will vary with the operating point. Rt memristance, , can be controlled by applying a voltage or current signal across the memristor, Since the flux ϕ is defined by ϕ (t) = −∞ v (τ ) dτ, the resistance of the memristor, called the where memristance, M, can be controlled by applying a voltage or current signal across the memristor, where

d  R  M  dϕ R = M = d q dq

( q  ) (qQ ·QϕQ Q)

(2) (2)

Equation (2) shows that a memristor is a kind of resistor that is variable depending upon an Equation (2) shows that a memristor is a kind of resistor that is variable depending upon operation point on a charge and flux plane. In this sense, it is a programmable resistance. an operation point on a charge and flux plane. In this sense, it is a programmable resistance. Let the input of a memristor be a current and the voltage across the memristor be the output of a Let the input of a memristor be a current and the voltage across the memristor be the output of single memristor circuit as shown in Figure 4. Then, according to Ohm’s law, the voltage output is an a single memristor circuit as shown in Figure 4. Then, according to Ohm’s law, the voltage output is analog multiplication between the current input and the resistance of a memristor as in Equation (3). an analog multiplication between the current input and the resistance of a memristor as in Equation (3). v  iM (3) v = i×M (3)

Figure Memristor as as an an ideal ideal element elementfor foraaneural neuralsynapse synapsewhere wherevoltage voltageacross acrossthe thememristor memristorisisa Figure 4. 4. Memristor amultiplication multiplication between an input current and a memristance. between an input current and a memristance.

Therefore, memristor is, in fact, an analog multiplier. Note that the resistance of a memristor is is is programmable. It distinguished from from that that of of an an ordinary ordinaryresistor resistorininthe thesense sensethat thatitsitsresistance resistance programmable. follows thatthat thethe resistance of of a memristor is iscalled thethe memristance of ofa It follows resistance a memristor calledmemristance. memristance.Since Since memristance can amemristor memristor canbebealtered altered(programmed) (programmed)by byinput input voltage/current voltage/currentand andan an analog analog multiplication is performed within withina single a single device, the memristor an ideal for the performed device, the memristor is knownisasknown an ideal as element for theelement implementation implementation of synapses. of synapses. 3. Nonlinearity Nonlinearityin inMemristor Memristor In the the TiO TiO22 memristor, memristor, aa thin thin TiO TiO22 layer layerand andaathin thinoxygen-poor oxygen-poorTiO TiO 2−x sandwiched 2− x layer are sandwiched between two platinum layerare are referred referred to to as un-doped, platinum electrodes. electrodes. The TiO TiO22 layer and the the TiO TiO22−x −x layer and doped layers, respectively. respectively. When a voltage or current is applied to the device, the dividing line between the TiO layersshifts shiftsas asaafunction functionof ofthe the applied applied voltage voltage or or current. current. As As aa result, TiO22 and TiO TiO22−x −xlayers the resistance between between the the two two electrodes electrodes is is altered. altered.

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Let D and w denote the thickness of the sandwiched area and the doped area (oxygen deficient area) in the TiO2 memristor, respectively, and let RON and ROFF denote the resistances at high and low dopant concentration areas, respectively. The relationship between the flux and the charge of the TiO2 memristor is given by [2]  ϕ(t) = Ro f f

      w0 RON µv RON RON 2 q(t) 1 + −1 − q ( t ) + ϕ0 1 − D ROFF ROFF 2D2

where µν is the dopant mobility and w (t) /D is the state variable x. The memristance M of a memristor can be computed with M = M=

dϕ = Ro f f dq

 1+

w0 D



RON −1 ROFF



−

µv RON D2

dϕ dq

(4)

as

 1−

RON ROFF



 q(t)

(5)

Assume that the applied input is a current i(t), then, Equation (5) is  M = Ro f f

w0 1+ D



RON −1 ROFF



µv RON − D2



R 1 − ON ROFF

Z

 i (t)dt

(6)

The derivative of Equation (6) with respect to time gives µv RON dM (t) = − Ro f f dt D2



R 1 − ON ROFF

 i (t)

(7)

It follows from Equation (7) M (t)

µv RON dM (t) = − Ro f f dt D2

 1−

RON ROFF

 v(t)

(8)

Assume that a constant voltage V is applied as an input voltage. Integrating both sides of Equation (8) results in   M ( t )2 µv RON RON = C − Ro f f 1− V·t (9) 2 ROFF D2 where C is the constant of integration. It follows from Equation (9) that M (t) can be written as, s     µv RON RON M (t) = 2 C − Ro f f 1− V·t ROFF D2

(10)

Equation (10) exhibits a fact that memristance is a nonlinear function of time t. Thus, programming the memristor with an arbitrary value is very difficult. Differently from the linear drift model described above, the nonlinear phenomenon appears often at the boundaries of nano-scale devices; with even the small voltage applied across nanometer devices, a large electric field is produced, and, therefore, the ion boundary position is moved in a non-linear fashion in nano-scale devices [14]. Several different types of nonlinear memristor models have been investigated [11,19,20]. One of them is the window model in which the state equation is multiplied by window function Fp (w), namely dw(t) R = µv ON i (t) Fp (w) dt D

(11)

where p is an integer parameter and Fp (w) is defined by  w 2p Fp (w) = 1 − 2 − 1 D

(12)

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This is called the nonlinear drift model or memristive model. It is difficult to find the solution This is called the nonlinear or memristive model. is difficult to findnumerically the solution as satisfying both Equations (11) anddrift (12) model analytically. However, w (t)Itcan be computed

( ) can be computed numerically as  w 2p  RON 2p ∆q + w(t) (13) w(t + ∆t) = µv RON 1 − 2wD − 1  1 2 1 w(t  t )  D    (13) v    q  w(t )  D   D   where ∆q is the charge increment fed to the memristor during the time interval ∆t and computed by where qthe is the charge increment fed to the memristor during the time interval Δt and computed by integrating input current as Z satisfying both Equations (11) and (12) analytically. However, 

integrating the input current as

∆q = I (t)dt = I∆t q   I (t )dt  I t Substituting the value of w from Equation (7) in Equation (8), we get

from Equation  get  (7) in Equation (8), we  RON ROFF R RON M≈ w0R 1 − R + R K∆q × Fp (w) R1 − OFF DM  ON w 1RONOFF   ON D K q  F ( w) 1  OFF  ROFF

(14)

(14)

Substituting the value of

D

0



RON 

p

D



ROFF 

(15) (15)

The current voltage relationship can be obtained as The current voltage relationship can be obtained as

 v(t) =

    ROFF RON ROFF RON    RON K∆q × Fp(w)ROFF1 −  w0 RON 1 −   ROFF + i (t) t )OFF   D K q  Fp ( w)  1    i (R Dv(t )   D w0 R1ON R D R 



ON





OFF

 

(16)

(16)

Figure 5 shows thethe graphs vs. time timeand andthe thememristance memristance time charge Figure 5 shows graphsofofthe thememristance memristance vs. vs.vs. time charge of of the the nonlinear models memristors pulseisisapplied. applied.The The memristance is more nonlinear modelsofof memristorswhen when aa rectangular rectangular pulse memristance is more nonlinear about time than that asthe thenumber numberp pbecomes becomes smaller, nonlinearity nonlinear about time than thatofofcharge. charge.In Inaddition, addition, as smaller, thethe nonlinearity increases. OnOn the theinteger integerp pincreases, increases, model tends the linear increases. theother otherhand, hand, as the thethe model tends to thetolinear model.model.

Memristance(kΩ )

(a)

t

  i ( )d 0

(b) Figure 5. Memristance variation of a nonlinear memristor of (Equation of Window function) about:

Figure 5. Memristance variation of a nonlinear memristor of (Equation of Window function) about: (a) time; (b) charge when a rectangular pulse is applied. (a) time; (b) charge when a rectangular pulse is applied.

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4. Linearization in Memristor Programming with Anti-Serial Architecture 4. Linearization in Memristor Programming with Anti-Serial Architecture Anti-serial memristor circuit is a circuit of two memristors in serial connection with opposite Anti-serial memristor circuit is a circuit of two memristors in serial connection with opposite polarities as shown in Figure 6. When a positive voltage (or current) signal is applied to a circuit polarities as shown in Figure 6. When a positive voltage (or current) signal is applied to a circuit with two memristors connected in series, but with opposite polarities, then the memristance of M1 with two memristors connected in series, but with opposite polarities, then the memristance of M1 decreases, whereas the memristance of M2 increases. As a result, the composite memristance decreases, whereas the memristance of M2 increases. As a result, the composite memristance becomes becomes constant, due to their complementary action [21]. constant, due to their complementary action [21].

(a)

(b) Figure memristors connected M1 and and M2 M2 connected connected Figure 6. 6. Memristor Memristor circuit circuit with with two two memristors connected anti-serially. anti-serially. (a) (a) M1 back opposite polarities polarities using using M3 M3 and and M4. M4. back to to back back in in series; series; (b) (b) serial serial connection connection with with opposite

Let us assume that the polarity of M1 is the same as that of the predefined reference polarity, Let us assume that the polarity of M1 is the same as that of the predefined reference polarity, and the polarity of M2 is opposite to that of the reference. If charge q(t) is injected into the positive and the polarity of M2 is opposite to that of the reference. If charge q(t) is injected into the positive terminal of the composite device, it acts as positive charge for M1, whereas it acts as negative charge terminal of the composite device, it acts as positive charge for M1, whereas it acts as negative charge for M2. Thus, for M2. Thus, qq((tt)) q2q(2t()t )= − (17) (17) Similarly, i.e., oppositetotothe thereference, reference, i.e., Similarly, the the sign sign of of flux flux ϕ2 (2 t()t )isisopposite

c(2t()t )= − ϕ2 ((t t)) ϕc2 2 as

(18) (18)

Thus, flux  (t ) and  (t ) of memristor M1 and M2 can be written as functions of charge q(t), Thus, flux ϕ11(t) and ϕ2 (2t) of memristor M1 and M2 can be written as functions of charge q(t), as n h  i ϕ1 (t) = Ro f f  q(t) w1 + RwD01 RR on − 1   on  1 o f f o 1 (t )  Roff  q (t )µ1R 01 v on D  R Ron  1 −off R   q(t)2 + ϕ1 (0)  − 2D2 of f

ϕ2 ( t ) = R o f f

 R   R  i 1  onR q (t ) 2   1 (0)  h v on 2  w   02 on q(t) 21D+  D RoffR  − 1 o f f   o v Ron + µ2D 1 − RRon q(t)2 − ϕ2 (0) 2

(19)

(19)

n





of f

w R

(20)



 (t )  R  q (t ) 1  02  on  1   The total flux ϕC (t) is the sum2 of ϕ1 off (t) and ϕ2 (Dt). Roff     

(20) When two memristors are assumed to be identical, and they are in the stable composite   v Ron  Ron  2 1  memristor  q (t )    2 (0) memristance state, the flux of the composite becomes 2   2D 

Roff 



" !# w R on 0  ( t )  ( t )  ( t ) is the The total flux C ϕCsum (t) =of2Ro1f f q(tand ) 1 +2 . −1 (21) D Roand ff When two memristors are assumed to be identical, they are in the stable composite memristance state, the flux of the composite memristor becomes

by differentiating Equation (21) with respect to q(t), as MC  Sensors 2016, 16, 1320

where,

  w R    dC (t )  2  Roff 1  0  on  1    2M O   dq(t )      D  Roff

(22) 8 of 15

 w R  Roff 1  0  on  1  .   D Roff   by w0 . Furthermore, the memristance of the composite memristor can be obtained

is the composite memristance, and

is a constant value of

where w01 = w02 = differentiating (21)(22) withisrespect to q(t), as Note that inEquation Equation a constant, since all the related parameters of

Let M2 is a target MTarget is

( " From memristor to program. dϕC (t) w = 2 Ro f f 1 + 0 MC = dq(t) D

Equation!#) (6), the expression Ron −1 = 2MO Ro f f

are constant. of memristance (22)

 w  R   i 0 ON  1  vRON 1  RON  i(t )dt h   1 M R         where, MC is the compositetarget memristance, M0 is a constant value of Ro f f 1 + wD0 RRon − 1 . off  Dand 2 R R OFF  of f  OFF  D   

Note that MC in Equation (22) is a constant, since all the related parameters of M0 are constant. Let M2 isvoltage a target memristor to V program. From Equation (6), i(t) the during expression of memristance when a rectangular pulse with volt is applied, current a non-zero pulse M is Target can be computed as     Z  RON w0 RON µv RON 1− Mtarget = Ro f f 1+ −1 − i (t)dt (23) D ROFF ROFF V D2

(23) period

i t  

when a rectangular voltage pulse with V volt is applied, M O current i(t) during a non-zero pulse period can be computed as V Plugging Equation (24) into Equation (23), (24) i (twe ) = obtain MO   w  R  v RON  RON  V  0(23),ON Plugging Equation M (24) into Equation we obtain R target off  1 D  ROFF  1  D 2 1  ROFF  M O t         w0 RON µv RON RON V M = R 1 + − 1 − 1 − t target ff parameters of the oright sideDof Equation (25) are except ROFF ROFF MO time D2 constant

(24)

(25)

(25) All the t. Therefore, it is a linear function of time. Comparing Equations (25) with (10) which is a nonlinear equation about time All the parameters of the right side of Equation (25) are constant except time t. Therefore, it is t, programing a memristor with Equation (25) is much easier than with Equation (10). a linear function of time. Comparing Equations (25) with (10) which is a nonlinear equation about To program a targeta memristor memristor with this method, the same a subsidiary memristor is time t, programing with Equation (25) is much easier thantype with of Equation (10). Toconnected program a target with this method, same type of apolarity subsidiary prepared and to thememristor target memristor in seriesthe with opposite as memristor in Figure 7. Since is prepared and connected to the target memristor in series with opposite polarity through as in Figure composite memristance of the anti-serial circuit is a constant value, the current the7.circuit is Since composite memristance of the anti-serial circuit is a constant value, the current through the constant. It follows that the memristance variation of the individual memristor is a linear function of circuit is constant. It follows that the memristance variation of the individual memristor is a linear pulse width since the memristance variation is a linear function of charge. function of pulse width since the memristance variation is a linear function of charge.

7. Proposed linearized programming methodwith with anti-serial anti-serial architecture. It isItaiscircuit of of two Figure 7.Figure Proposed linearized programming method architecture. a circuit two memristors in serial connection with opposite polarities. Though the individual behavior of memristors in serial connection with opposite polarities. Though the individual behavior of memristance variation of two memristors is nonlinear about time, it becomes linear in an anti-serial memristance variation memristors is nonlinear about time, it becomes linear in an anti-serial connection due to of thetwo complementary action of two memristors with opposite polarities. connection due to the complementary action of two memristors with opposite polarities.

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5. Application of the Anti-Serial Memristor Architecture to the Weight Programming of a Memristor Bridge Synapse Sensors 2016, 16, 1320

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Anti-serial connections of memristor circuit are utilized to build a memristor bridge weighting Application Anti-Serial Memristor Architecture the Weight Programming of sets of anti-serial circuit [7], 5.which can of betheprogrammed linearly due totothe cooperation of two a Memristor Bridge Synapse memristor circuits. Anti-serial connections of memristor circuit are utilized to build a memristor bridge weighting The memristor bridge circuit consists of four identical memristors with different polarities circuit [7], which can be programmed linearly due to the cooperation of two sets of anti-serial ( ) is applied at the input, the indicated in Figurecircuits. 8. When a positive or a negative pulse memristor memristor bridge is circuit consists or of four identical linearly memristors with different polarities memristance ofThe each memristor increased decreased depending upon its polarity. For indicated in Figure 8. When a positive or a negative pulse V t is applied at the input, ( ) in instance, when a positive pulse is applied as input, the memristances of M1 and M4 (whose the memristance of each memristor is increased or decreased linearly depending upon its polarity. polarities are forward-biased) will decrease. On the other hand, the memristances of M2 and M3 For instance, when a positive pulse is applied as input, the memristances of M1 and M4 (whose polarities are reverse-biased) will It follows that the voltage ofatM2node A (with (whose polarities are forward-biased) willincrease. decrease. On the other hand, the memristances and M3 (whose polarities are reverse-biased) will increase. follows thatathe voltage Vinput A A at node respect to ground) becomes larger than the voltage atItnode B for positive signal pulse. In (with respect to ground) becomes larger than the voltage VB at node B for a positive input signal pulse. this case, the circuit produces a positive output voltage representing a positive synaptic In this case, the circuit produces a positive output voltage Vout representing a positive synaptic weight. weight.

Figure 8. An application of the proposed anti-serial anti-serial memristor circuitcircuit to the implementation of Figure 8. An application of the proposed memristor to the implementation of neural networks. With two different types of anti-serial memristor circuits, synaptic weights of neural neural networks. With two different types of anti-serial memristor circuits, synaptic weights of networks can be programmed linearly about time when a direct current DC voltage signal is applied neural networks can be programmed linearly about time when a direct current DC voltage signal is for the programing of a neural synapse. applied for the programing of a neural synapse.

On the other hand, when a negative strong pulse is applied, the memristances are varied in the opposite direction and the voltage at node B becomes larger than that at node A. In this case, the circuit the other hand, when a negative strong pulse is applied, the memristances are varied produces a negative output voltage Vout representing a negative synaptic weight.

On in the opposite direction and the voltage at node B becomes larger than that at node A. In this case, the 6. Simulation circuit produces a negative output voltage representing a negative synaptic weight. The linearity in programing with several memristor circuits such as single and anti-serial circuit has been tested. The memristor models employed for these simulations are a linear drift model of HP 6. Simulation TiO2 [2] and a nonlinear model with window function with p = 1 [16]. When want to program a memristor a certain memristance the easiest is The linearity inwe programing with severaltomemristor circuitsvalue, suchone as ofsingle andways anti-serial circuit by applying a constant voltage or current for a certain length of time. If memristance variation about has been tested. The memristor models employed for these simulations are a linear drift model of time is linear, the desired value of memristance can be programmed easily since the programmed HP TiO2 [2]memristance and a nonlinear withtowindow function with p = 1 [16]. would bemodel proportional the width of a voltage pulse. shows the memristance variation time when a constant voltage of one 1 V isof applied When we Figure want9to program a memristor toabout a certain memristance value, the easiest ways to a TiO memristor model. Though the memristance curve is linear about charge, it is non-linear is by applying a 2constant voltage or current for a certain length of time. If memristance variation about applied time (pulse width) as shown with a solid line in Figure 9. Such a nonlinearity about time about timemakes is linear, the desired value of memristance can be curve programmed easily since the the programing of a memristor difficult. The desirable memristance is the dotted line.

programmed memristance would be proportional to the width of a voltage pulse. Figure 9 shows the memristance variation about time when a constant voltage of 1 V is applied to a TiO2 memristor model. Though the memristance curve is linear about charge, it is non-linear about applied time (pulse width) as shown with a solid line in Figure 9. Such a nonlinearity about time makes the programing of a memristor difficult. The desirable memristance curve is the dotted line.

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Figure 9. Nonlinear variation of the memristance about time of TiO2 memristor model when a

Figure 9. Nonlinearvariation variation of memristance aboutabout time oftime TiO2 of memristor model when a constant Figure 9. Nonlinear ofthe the TiO2 memristor model when a constant voltage (rectangular pulse) ismemristance applied. voltage (rectangular pulse) is applied. constant voltage (rectangular pulse) is applied. Figure 10 shows a memristance variations of two memristors in the proposed anti-serial Figure 10shows shows aa7memristance variations of source twoof memristors in Upon the proposed anti-serial connection connection Figure when a constant voltage is applied. applying aproposed constant voltage Figure 10 in memristance variations two memristors in the anti-serial in Figure 7 when a constant voltage source is applied. Upon applying a constant voltage source to source to the anti-serial circuit, the subsidiary and target memristors are cooperating in connection in Figure 7 when a constant voltage source is applied. Upon applying a constant voltage the anti-serial circuit, the subsidiary and target memristors are cooperating in complimentary fashion. complimentary fashion. The resultant memristance variation is linearized about time as shown in source to the anti-serial circuit, the subsidiary and target memristors are cooperating in The resultant memristance variation is linearized about time as shown in the figure. the figure.

complimentary fashion. The resultant memristance variation is linearized about time as shown in the figure.

Figure 10. Linear variation of memristance when a constant voltage source is applied to the proposed anti-serial connection of two memristors.

Simulations demonstrate the in programming the memristor memristor bridgeto synapse circuit Simulations to demonstrate the linearity linearity in programming the bridge synapse circuit Figure 10. Linear to variation of memristance when a constant voltage source is applied the proposed have also been been performed. the memristance memristance variation variation of each memristor memristor of of anti-serial anti-serial memristor memristor have also performed. Ifmemristors. the of each anti-serial connection of twoIf circuit is linear, the voltage change at each node of the circuit is supposed to be linear. In circuit is linear, the voltage change at each node of the circuit is supposed to be linear. In consequence, consequence, the weight of the memristor bridge synapse can be programmed linearly since the the weight of the memristor bridge programmed the linearly since thebridge memristor bridge Simulations to demonstrate the synapse linearitycan in be programming memristor synapse circuit memristor bridge synapse circuit isdifferent composed of of two differentcircuits. sets of anti-serial circuits. circuit is composed of two sets anti-serial havesynapse also been performed. If the memristance variation of each memristor of anti-serial memristor Figure 11 11shows showsa weight a weight programming scenario where Figure is the changes of two programming scenario where Figure 11a is 11a the changes of two voltages circuit isFigure linear, theVn)voltage change at each node of the circuit isapplied supposed to be linear. In voltages (Vp and at middle points starting with 15.6 kΩ. When +1 V is for a long time as in in (Vp and Vn) at middle points starting with 15.6 kΩ. When +1 V is applied for a long time as consequence, the weight ofofthe memristor bridge synapse can be400 programmed linearly since Figure 11e, and the Figure 11e, memristances memristances of M1 M1 and and M4 M4 are are reduced reduced gradually gradually until until 400 Ω Ω is is reached reached while while M2 M2 and memristor synapse circuit memristance is composed of two sets of of memristance anti-serial circuits. M3 are arebridge keptwith with highest kΩ.different The change is a nonlinear M3 kept its its highest memristance 15.6 15.6 kΩ. The change of memristance is a nonlinear function Figure 11 shows a weight programming scenario where Figure 11a is the changes of function about timethis during thisThen, period. Then, −1 V is afterwards, applied afterwards, the memristances of two about time during period. when −1when V is applied the memristances of M2 and M2 are and M3 reduced linearly while those of M115.6 andincreased M4 When are increased M2,M1, M3M4 M1, M4 voltages (Vpreduced andare Vn) at middle points starting with kΩ. +1 M2, V isuntil applied for aand long time M3 linearly while those of M1 and M4 are until M3 and reach the as in reach the minimum and maximum values, respectively. Then, when +1 V is applied again, the Figure 11e, memristances ofvalues, M1 and M4 are reduced gradually 400again, Ω is the reached while M2 minimum and maximum respectively. Then, when +1 V isuntil applied memristances of and memristances of M2 and M3 are increased while those of M1 and M4 are decreased linearly. M3 are kept with its highest memristance 15.6 kΩ. The change of memristance is a nonlinear M2 and M3 are increased while those of M1 and M4 are decreased linearly. 11b shows thethis changes of voltages Vp and are the voltages at the middle points of of function Figure about time during period. Then, when −1Vn V which is applied afterwards, memristances two anti-serial circuits during the period of Figure 11a. As seen in the middle of the figure, voltage M2 and M3 are reduced linearly while those of M1 and M4 are increased until M2, M3 and M1, M4 changes linearly about time due to the linear change of memristances in Figure 11a. As the result, the

reach the minimum and maximum values, respectively. Then, when +1 V is applied again, the memristances of M2 and M3 are increased while those of M1 and M4 are decreased linearly. Figure 11b shows the changes of voltages Vp and Vn which are the voltages at middle points of

at the middle where graphs are almost linear though some nonlinear regions can be seen at the end of the curves. Since weighting operations are performed only in the linear region at the center as indicated with a box, linear programming can be performed with the proposed anti-serial architecture. Meanwhile Figure 12b is the variations of memristances when the programming signal is applied at individual memristors. As seen in the figure, the memristance changes as functions11of Sensors 2016, 16, 1320 of 15 time are highly nonlinear in all the range of the curves.

M 1  M 4  400 M 2  M 3  15.6k 

Figure 11.11. Linear programming of the memristor bridge synapse thatthat is composed of two different Figure Linear programming of the memristor bridge synapse is composed of two different types of antiserial linear memristors. (a) (a) variation of memristances; (b)(b) changes of voltages Vp Vp andand types of antiserial linear memristors. variation of memristances; changes of voltages Vn;Vn; (c) (c) difference of middle voltage (Vp(Vp − Vn); (d) (d) weight changes of the memristor bridge synapses; difference of middle voltage − Vn); weight changes of the memristor bridge synapses; and, (e) (e) wide pulse forfor programming. and, wide pulse programming.

Figure 11b shows the changes of voltages Vp and Vn which are the voltages at middle points of two anti-serial circuits during the period of Figure 11a. As seen in the middle of the figure, voltage changes linearly about time due to the linear change of memristances in Figure 11a. As the result, the voltage difference of middle voltage (Vp − Vn) is also linear as in Figure 11c and finally, weight changes of the memristor bridge synapses becomes also linear as in Figure 11d. The effect of the nonlinearity of memristor models to the performance of our memristor circuit has also been investigated. Figure 12a shows the memristance variations for each memristor of anti-serially connected non-linear memristor circuit. It is assumed that M1 and M2 have initial values of 15.6 kΩ and 400 Ω, respectively. When a positive DC input with +1 V is applied at the anti-serial circuit, the memristance of M1 is reduced and that of M2 is increased. Observe the region

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at the middle where graphs are almost linear though some nonlinear regions can be seen at the end of the curves. Since weighting operations are performed only in the linear region at the center as indicated with a box, linear programming can be performed with the proposed anti-serial architecture. Meanwhile Figure 12b is the variations of memristances when the programming signal is applied at individual memristors. As seen in the figure, the memristance changes as functions of time are highly Sensors 2016,in 16,all 1320 12 of 15 nonlinear the range of the curves. Linear Region 16 14 12 10

M1

8 6

M2

4 2 0

0.5

1

1.5

2

2.5

time(s) 1V (a)

(b) Figure 12. Linearized variation of memristance at the middle of the graph when a constant voltage Figure 12. Linearized variation of memristance at the middle of the graph when a constant voltage source is applied at an anti-serial connection of two nonlinear memristors (a) and nonlinear variation source is applied at an anti-serial connection of two nonlinear memristors (a) and nonlinear variation of memristance of individual memristors for comparison when the programming signal is applied at of memristance of individual memristors for comparison when the programming signal is applied at each memristor individually (b). each memristor individually (b).

Comparing Figure 12a and b, the memristances of anti-serial memristors are linearized Comparing 12a and the memristances significantly thanFigures those without the12b, anti-serial connection. of anti-serial memristors are linearized significantly than those without the anti-serial connection. The effect of weight programming of memristor bridge synapses with non-linear model of The effect of weight programming memristor bridge synapses non-linear of memristors is also investigated. Figure 13 of shows parameter variation of a with memristor bridgemodel synapse memristors is also investigated. Figure variation of anecessary memristor bridge synapse while the programming input signal as13 inshows Figureparameter 13e is applied. All the arrangements are the same as the linear memristor case in Figure 11 except that nonlinear memristors are employed. Observe the memristance especially in Figure 13a and weight variation in Figure 13d at the time periods of [5.355, 6.247] s and [8.318, 9.209] s are all linearized very much.

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while the programming input signal as in Figure 13e is applied. All the necessary arrangements are the same as the linear memristor case in Figure 11 except that nonlinear memristors are employed. Observe the memristance especially in Figure 13a and weight variation in Figure 13d at the time Sensors 2016, 1320 6.247] s and [8.318, 9.209] s are all linearized very much. 13 of 15 periods of 16, [5.355,

M 1  M 4  400 M 2  M 3  15.6k 

Figure 13. 13. Linearized Linearized programming memristor bridge synapse which is composed of Figure programming of of thethe memristor bridge synapse which is composed of two two different of anti-serial non-linear memristors. variation memristances;(b) (b)changes changes of of different typestypes of anti-serial non-linear memristors. (a) (a) variation ofofmemristances; voltages Vp and Vn; (c) difference of middle voltage (Vp − Vn); (d) weight changes of the memristor voltages Vp and Vn; (c) difference of middle voltage (Vp − Vn); (d) weight changes of the memristor bridge synapses; synapses; and, and, (e) (e) wide wide pulse pulse for for programming. programming. bridge

7. Conclusions Conclusions 7. In neuromorphic applications time is In applications of of memristors, memristors,aalinear linearprogramming programmingofofmemristance memristanceabout about time important. InIn this paper, wewe proposed a method utilizing anan anti-serial architecture. is important. this paper, proposed a method utilizing anti-serial architecture. Anti-serial architecture connection of two with opposite polarities. It exhibits Anti-serial architectureisisa serial a serial connection of memristors two memristors with opposite polarities. It linearization in programming due to a complimentary action of two memristors; when the memristance exhibits linearization in programming due to a complimentary action of two memristors; when the memristance of one memristor increases, the other decreases. Since composite memristance of the anti-serial circuit is a constant value, the current through the circuit is constant. It follows that the memristance variation of the individual memristor is a linear function about pulse width since the memristance variation is a linear function of charge. Our proposed idea of linear programming of a memristor is by employing an additional

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of one memristor increases, the other decreases. Since composite memristance of the anti-serial circuit is a constant value, the current through the circuit is constant. It follows that the memristance variation of the individual memristor is a linear function about pulse width since the memristance variation is a linear function of charge. Our proposed idea of linear programming of a memristor is by employing an additional subsidiary memristor with an opposite polarity when programming a target memristor is needed. When programming a target memristor is needed, a subsidiary memristor with an opposite polarity is prepared so that the subsidiary and target memristors construct an anti-serial architecture. The validity of the proposed idea has been proved with linear drift model of HP TiO2 memristor. In addition, it has been applied in building a memristor synapse circuit that is composed of two different sets of anti-serial architectures. Due to the anti-serial architecture, weights have been programmed linearly about applied pulse width. The proposed architecture has also been tested with memristor models of highly nonlinear characteristics. Memristances of the anti-serial memristor circuits and weights of memristor bridge synapse circuits are all linearized significantly around zero memristance and zero weight regions, respectively. Acknowledgments: This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2013R1A2A2A01068683, NRF-2016R1A2B4015514) and the Brain Korea 21 PLUS Project, National Research Foundation of Korea. Author Contributions: Changju Yang designed the circuits, performed the experiments and conducted the data analysis. All authors wrote the paper. Conflicts of Interest: The authors declare no conflict of interest.

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