Luis Parrilla, Encarnación Castillo, Antonio García, and Antonio Lloris. Department of Electronics and Computer Technology, University of Granada.
Intellectual Property Protection for RNS Circuits on FPGAs Luis Parrilla, Encarnación Castillo, Antonio García, and Antonio Lloris Department of Electronics and Computer Technology, University of Granada 18071 GRANADA (Spain) {lparrilla,ecastillo,agarcia,lloris}@ditec.ugr.es
Abstract. A new procedure for Intellectual Property Protection (IPP) of circuits based on the residue number system (RNS) and implemented over FPL devices is presented. The aim is to protect the author rights in the development and distribution of reusable modules (IP cores) by means of an electronic signature embedded within the design. The presented protection scheme is oriented to circuits based on the RNS but can be easily extended to systems implemented on programmable devices. As an example, a 128-bit signature is introduced into a CIC filter without affecting performance and negligible area increase.
1 Introduction The increasing complexity in digital IC designs, combined with the hard competition in the electronics market, is leading to substantial changes in design strategies, directed to minimize the development time and costs. These strategies [1] are based on the use of reusable modules (IP cores) and provide precious competitive advantages. This makes new challenges not yet considered to arise, one of the main being the intellectual property protection of those shared modules, being necessary to provide mechanisms to the author for claiming intellectual property rights. The usual procedures for IPP in media and hardware support [2] consist of hiding a signature (watermark) that is difficult, if not impossible, to change or remove. In our approach, an MD5 [3] digital signature is introduced in the design, with appropriate techniques for embedding and extracting this signature in RNS-based systems. This is possible due to the RNS particularities [4], that have traditionally been exploited for performance enhancement and have made RNS particularly wellsuited for FPL implementation [5-6] with an extensive use of the look-up tables available in programmable technologies.
2 Protection by Used Table Spreading on FPL The key idea lies in “spreading” all the possible bits of the digital signature through non used cells of look-up tables included in the RNS-based design. The fact that these J. Becker, M. Platzner, S. Vernalde (Eds.): FPL 2004, LNCS 3203, pp. 1139–1141, 2004. © Springer-Verlag Berlin Heidelberg 2004
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tables are part of the design makes extremely difficult the possibility of an attacker finding these signature bits. Thus, problems related with previous IPP methods based on the use of tables or logic elements not in use are solved [2,7] and, as the signature embedding is performed in the high-level design description stage, this method is more secure than other IP protection techniques that rely on Place&Route modifications. The steps in the signature embedding process are: 1. The selected signature is stored in a public domain document. 2. MD5 is used to convert the signature in a bit stream or digital signature. 3. This bit stream is partitioned in blocks. 4. These blocks are embedded into empty positions of look-up tables, or signature memory positions (SMP). 5. The signature extraction stream (SES) detection hardware is included in the design. There is not a fixed algorithm for spreading the bits, this will depend on each particular design, but this extra effort makes harder to change or remove the embedded signature. The signature extraction process consists of applying the SES to the circuit, which will make each one of the SMPs to be addressed, instead of the memory position that the normal RNS hardware would point to. During a few clock cycles, the output system is each one of these signature bit blocks. The extraction process thus require some extra hardware.
3 Design Example: CIC Filter A 3-stage CIC decimation filter [8] was chosen as study case for embedding a 128-bit signature. It includes 2C-to-RNS conversion, four parallel RNS CIC channels and εCRT-based RNS-to-2C conversion [9]. Design examples were implemented using the Xilinx Virtex-II device family. Table 1 shows results for the conventional RNS-based CIC filter and the signed RNS-based CIC filter proposed in this paper. Analysis of these results shows that the area increase for the signed filters is less than 6% while throughput penalization is negligible. In fact, there is a small performance increase that can be explained because of a better Place&Route effort by the design tool. It must also be noted that the area increase is a fixed quantity for this signature length, so for more complex applications the area increase will be even less noticeable. Table 1. Summary of simulation results Speed grade -6 -5 -4
RNS-based CIC filter SLICEs Fmax (MHz) 420 420 420
106.85 101.34 88.63
SLICEs 445 445 445
signed RNS-based CIC filter Area increase Fmax (MHz) Speed reduction 5.95% 5.95% 5.95%
107.19 103.50 91.26
-0.32% -2.13% -2.97%
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4 Conclusions This paper describes a procedure that exploits empty memory positions in the look-up tables used in RNS-based hardware to embed a digital signature in RNS-based circuits. This allows its IPP usage for IP cores since it is extremely difficult to detect and/or remove this signature. An RNS-based CIC filter was used to embed a 128-bit signature with negligible penalties in both performance and area. Furthermore, the procedure described can be easily extended to any FPL hardware using look-up tables. In the case that the design to sign does not force the use of look-up tables, it is still possible to map into tables part of the design not included in the critical path, so the proposed method may be applied. Further work will be directed to this issue, as well as to the optimization of the resources and security of the embedded signature.
Acknowledgements. Authors wish to acknowledge financial support from the Dirección General de Investigación (Spain) under project TIC2002-02227. CAD tools and supporting material were provided by Xilinx Inc, trough Xilinx University Program agreements.
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