Load Balancing Among Photolithography ... - Semantic Scholar

JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 24, 379-391 (2008)

Load Balancing Among Photolithography Machines in the Semiconductor Manufacturing System*

1

ARTHUR M. D. SHR1,2, ALAN LIU1 AND PETER P. CHEN2 Department of Electrical Engineering and Center for Telecommunication Research National Chung Cheng University Chiayi, 621 Taiwan E-mail: [email protected]; [email protected] 2 Department of Computer Science Louisiana State University Baton Rouge, LA 70803, U.S.A. E-mail: {mshr1; pchen}@lsu.edu

We propose a Load Balancing (LB) scheduling approach to tackle the load balancing issue in the semiconductor manufacturing system. This issue is derived from the dedicated photolithography machine constraint. The constraint of having a dedicated machine for the photolithography process in semiconductor manufacturing is one of the new challenges introduced in photolithography machinery due to natural bias. To prevent the impact of natural bias, the wafer lots passing through each photolithography process have to be processed on the same machine. However, the previous research for the semiconductor manufacturing production has not addressed the load balancing issue and dedicated photolithography machine constraint. In this paper, along with providing the LB approach to the issue, we also present a novel model, Resource Schedule and Execution Matrix (RSEM) – the representation and manipulation methods for the task process patterns. The advantage of the proposed approach is to easily schedule the wafer lots by using a simple two-dimensional matrix. We also present the simulation results to validate our approach. Keywords: dedicated photolithography machine constraint, load balancing, resource schedule and execution matrix, semiconductor manufacturing, photolithography

1. INTRODUCTION Semiconductor manufacturing systems are different from traditional manufacturing operations, such as a flow-shops manufacturing system in assembly lines or a job-shops manufacturing system. In a semiconductor factory, one wafer lot passes through hundreds of operations and the processing procedure takes a few months to complete. The operations of semiconductor manufacturing incrementally develop an IC product layer by layer. A “Re-Entrant Lines” model has been proposed to provide the analysis and design of the semiconductor manufacturing system [1, 2]. These scheduling policies have been proposed to deal with the buffer competing problem in the re-entrant production line, as they pick up the next wafer lot in the queue buffers as the machines become idle. Received January 9, 2006; revised September 21, 2006; accepted January 23, 2007. Communicated by Suh-Yin Lee. * This research was partially supported by the U.S. National Science Foundation grant No. IIS-0326387 and U.S. AFOSR grant No. FA9550-05-1-0454. This research was also supported in part by the Ministry of Economic Affairs under the grant No. 96-EC-17-A-02-S1-029 and the National Science Council under the grants No. 96-2752-E-008-002-PAE and 95-2221-E-194-009.

379

ARTHUR M. D. SHR, ALAN LIU AND PETER P. CHEN

380

Wafers

Wafer Start

Wafers at some layers skip this operation ?

Diffusion or thin film Chemical, Physical Deposition Ion implant

.

Photolithography Photolithography Load Balancing and Constraint (Figure 2)

How many layers depend on the type of the products

Etching

Wafers at some layers skip this operation

Chemical mechanical Polish (CMP) & Other operations 1 105 105 105 015 105 105 105 05 6 6 6 6 6 6 2 2 2 2 2 2 2 a1 a1 b1 b1 b1 b1 7a1 7a1 7a12 7Vcc1 7a1 7a1 7a1 6 7 3 b1 3 b2 3 b2 3 b2 36 3 b1 3 b1 3 b1 Vcc1 Vcc1 b2a2 b2a2 b2 4 Vcc1 4Vcc1 8a2 4 Vcc1 8a2 4Vcc1 8a2 4 b2 8a2 4Vcc1 8a2 4 b2 8a2 GND GND GND GND GND GND GND b3a3 b3 a3 b3 a3 b3 a348GND b3a3 b3 a3 b3 a3 b3 a3 8 0b4 0b4 0b4 05 1 0a4 05 0a4 05 b4a41b4 a41b4 5 5 5 1a4 5 1a4 5 a4 1b4 1 b41a4 6a1 6a1 6a1 2 a1 2 2 2 2 2 2 2 06 06 06 0 b1 0 b1 0 b1 0 6 b1a2 a1 b1 a1 b1 a1 b1 a106 7a2 7a2 7a2 7 7a2 7a2 7a2 7 3b1 3 3 3 3Vcc1 3 Vcc1 3Vcc1 3 Vcc1 b2 b2 b2 a2 Vcc1 Vcc1 Vcc1 Vcc1 b2 b2 b2 b2 8a3 8a3 8a3 8 4 GND 4GND 4 GND 4GND 4 GND 8a3 4GND 8a3 4 GND 8a38 4b2 b3 b3 b3 b3 a3 b3a3 b3 b3 b3 GND 0b4 0b4 0b4 05 5 1a4 5 1a4 5 a4 1 b4a4 10b4 5a4 10b4 5a4 10b4 5a4051 b41a4 6 6 6 2 2 2 2 2 2 2 b1a1 b1 a1 b1 a1 b1 a106 0b1 06 06 06 a1 a1 a1 a106 b1 b1 b1 7a2 7a2 7a2 7 7a2 7a2 7a2 72 3 Vcc1 3Vcc1 3 Vcc1 3Vcc1 3Vcc1 30Vcc1 3Vcc1 30Vcc1 b2 b2 b2 b2 a2 b2 a2 b2 b2 b2 8a3 8a3 8a3 8 8a3 8a3 8a384 GND 4GND 4 GND 4GND 4GND 4 GND 4GND 4 GND b3a3 b3 b3 b3 b3a3 b3 b3 b3 b4a4b4a4b4a4b4a4 b4a4b4a4b4a4b4a4 0

0

0

0

0

0

0

Products

0

Fig. 1. Process flow of semiconductor manufacturing.

Fig. 1 shows the concept of the process flows of a semiconductor manufacturing system, which is a re-entrant production line. The operations of semiconductor manufacturing repeatedly make an IC product layer by layer. The dedicated machine constraint is in the photolithography process area. A factory’s performance can be measured by the mean and variance of the manufacturing process time for products. The manufacturing lead-time, called the cycle time, is the time from when the wafer lot is released to the production line to the time the wafer lot completes the process and exits the production system. Each wafer lot, when it starts, will assign an estimated time of exiting the factory, which will be committed to the customer. Reducing the variance of the cycle time can improve the ability to meet the delivery dates or due dates that have been committed to customers. A small variance of cycle time means the system can accurately predict the time a product will complete production. Some efficient scheduling policies have been proposed to reduce the mean and variance of product cycle time [2, 3]. Many problems of the current scheduling approaches, such as queuing network modeling, include the need to abstract from actual work status off-line and the inability to respond rapidly to dynamic changes and uncertainty in the environment. The reason for this is that the differences in operators, machines, and materials, as well as equipment breakdown, will affect the effectiveness of a job. Such random variation is a consequence of events beyond our immediate control [4]. Moreover, it is difficult to have algorithms for scheduling models that transform the massive influx of data from equipment, products and process status into information for making decisions or providing reasonable and acceptable scheduling strategies. Although these scheduling policies or methods have been developed and applied in the semiconductor factories, there is still much effort for manually rescheduling some special wafer lots in a semiconductor manufacturing system. Motivated by the problems above, we have proposed the Load Balancing (LB) scheduling approach to handle the load balancing issue. The LB approach achieves the load balancing by scheduling the wafer lots at the first photolithography stage to a suitable photolithography machine according to, not only the slack time of each wafer lot, but also the current load factors of the photolithography machines. The paper is organized as follows. We describe the issue of load balancing among photolithography machines and dedicated photolithography machine constraint in section

LOAD BALANCING AMONG PHOTOLITHOGRAPHY MACHINES

381

2. Section 3 presents the proposed LB approach to this issue. Section 4 states the simulation results that validated our scheduling method. Section 5 discuses the conclusion and our future work.

2. LOAD BALANCING AMONG PHOTOLITHOGRAPHY MACHINES The constraint of having a dedicated machine for the photolithography process is one of the new challenges introduced in photolithography machinery of the semiconductor manufacturing systems due to natural bias. Natural bias will impact the alignment of patterns between different layers. A study considered different process control policies, including the machine dedication policy, in their simulation study for semiconductor manufacturing and reported that the scheduling policy with machine dedication had the worst performance of the photolithography process [5]. The machine dedication policy is similar to the dedicated photolithography machine constraint we are discussing in this paper. The smaller the dimension of the IC products, the more difficult they will be to align between different layers. This is the case especially when we move on to a smaller dimension IC for high technology products. The wafer lots passing through each photolithography stage have to be processed on the same machine. The purpose of the dedicated machine constraint is to prevent the impact of natural bias and to keep a good yield of the IC product. Fig. 2 describes the dedicated photolithography machine constraint. When wafer lots enter photolithography process stages, with the dedicated machine constraint and the wafer lots dedicated to machine X, they need to be processed by or wait for machine X. The wafer lot cannot be processed by other machines, e.g., machine Y, even if Y is idle. On the other hand, when wafer lots enter into those non-photolithography process stages, without this machine constraint, the wafer lots can be processed by any machines of A, B or C as long as it becomes idle. (1) Dedicated Machine Constraint

(2) No Constraint

Wafer lots Busy

idle

Machine X

Machine Y

Machine Z

Photolithography Stages

Machine A

Machine B

Machine C

Other Stages

Fig. 2. Dedicated photolithography machine constraint.

The load balancing issue is derived mainly from the dedicated photolithography machine constraint. If we randomly schedule the wafer lots to arbitrary photolithography machines at the first photolithography stage, then the load of all photolithography machines might become unbalanced. This happens because once the wafer lots have been scheduled to one of the machines at the first photolithography stage, they must be assigned to the same machine in the subsequent photolithography stages until they have passed the last photolithography stage. Therefore, any unexpected abnormal events or the

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breakdown of one machine will cause a pile-up of many wafer lots waiting for the machine and would be a critical loss to the factory. The photolithography process is the most important process in semiconductor manufacturing since the yield of IC products is always dependent on a good photolithography process. At the same time, the process can also cause defects. Not surprisingly, the performance of the factory will rely on the photolithography machines. Recently, a study concerning the load balancing issue developed a load balance allocation function by applying a dynamic programming method to the machine constraint in the photolithography machines [6]. Two approaches used simulations to model the photolithography process; one of them proposed a Neural Network approach to the photolithography scheduling problem [7]. The other decided the wafer lots assignment of the photolithography machines at the time when the wafer lots were leased to the manufacturing system to improve the load balancing problem in the photolithography area [8]. However, the researchers’ proposed scheduling methods did not concern the dedicated photolithography machine constraint. The load balancing issue is the main contributor to the complexity and uncertainty of the semiconductor factory. The load balancing among photolithography machines is also today’s most important challenge to improve productivity and fulfill requests for customers. The unbalanced load among photolithography machines will result in some of the photolithography machines becoming idle and remaining so for a while, due to the fact that no wafer lots can be processed. Meanwhile, the other will always be busy while many wafer lots in the buffer limited to this machine are awaiting processing. As a result, some wafer lots will never be delivered to customers on time, and the performance of the factory will decrease. To practically solve the issue of load balancing, the wafer lots of an unbalanced load semiconductor factory usually need to be switched from the highly congested machines to the idle machines. This process takes much time and relies on experienced engineers to manually handle alignment problems of the wafer lots with a different situation off-line. It is inefficient to determine which wafer lot and machine need to be switched one lot at a time and this process cannot meet the fast-changing market of the semiconductor industry either. Most semiconductor manufacturing factories apply the Least Slack (LS) time policy in their scheduling system [9]. The LS policy is defined as: Sk(w) = Dk(w) – ζk,i

(1)

where w is a wafer lot, and k and i are stages. The symbol ζk,i in Eq. (1) is an estimate of time remaining for a wafer lot w currently in stage i, until it reaches the buffer of stage k. Dk(w) represents the due date of wafer lot w to k. Suppose k is the last stage, then Sk(w) is the slack time for the wafer lot w at i with an estimate of the time remaining until the wafer lot w currently in i exits the system. Whenever a machine located at some production area becomes idle, it scans the buffers catered to it by the production area, and chooses the wafer lot w that has the smallest slack time to service next. The LS policy gives highest priority to a wafer lot w whose slack time Sk(w) is the smallest. We note that the entire class of LS policies has been proved stable [2, 10].


383

However, two simple examples explain why the issue of the unbalanced load to photolithography machines happens if we only apply the LS time scheduling policy in the semiconductor manufacturing with the dedicated photolithography machine constraint. Suppose that there are two wafer lots wx, wy dedicated to photolithography machines X and Y in the photolithography process area with slack time Sk(wx), Sk(wy), and Sk(wx) < Sk(wy). The two wafer lots wx and wy are the only wafer lots in the queue buffer of the photolithography process; therefore according to the LS policy, wx should be processed by photolithography machines first. However, machine Y is available first instead, and then only wy could be processed on Y but wx could not. Therefore, wx could not be processed on time to maintain its slack time at this photolithography stage, while wy will be processed first without the highest priority for this photolithography process. Therefore, the LS policy cannot be a stable scheduling policy for the semiconductor manufacturing system with the dedicated photolithography machine constraint. The other example follows: Suppose that machine X is available and all the other machines are busy. However, many wafer lots are waiting at the queue buffer of the other machines, yet no wafer lots are in the queue buffer of machine X. Therefore, in order to keep machine X running and follow LS policy, the next unlimited wafer lot at the first photolithography stage will be processed by X. Under normal conditions, all these lots processed by X have a bigger slack time than other wafer lots which are still waiting for other busy photolithography machines. These wafer lots will slow down and stay a longer time than the estimated cycle time at non-photolithography stages according to the LS policy. Therefore, to avoid machine X being idle, we overload the machine. The machine X is a bottleneck machine when the overload wafer lots return at the next photolithography stage in this reentrant production line. We call this event “thrashing”.

3. LOAD BALANCING SCHEDULING APPROACH We apply the Load Balancing (LB) scheduling approach to the dedicated photolithography machine constraint in semiconductor manufacturing. The proposed LB scheduling approach uses the Resource Schedule and Execution Matrix (RSEM) as a tool to represent the temporal relationship between the wafer lots and the machines during each scheduling step [11-13]. First, the RSEM spans all the wafer lots as two-dimensional matrices to represent the activities of tasks in the factory. Second, the LB scheduling approach obtains some value of factors from the RSEM. The factors are the summary of count or sum of the rows or columns by the RSEM. The final step is to execute the scheduling. Our proposed LB scheduling approach assigns each wafer lot at the first and unconstrained photolithography stage to a suitable photolithography machine. The rule for the assignment is to select a wafer lot with the biggest wait steps to the smallest load photolithography machine. After that, these wafer lots will be put into the queue buffer of their assigned photolithography machine. As soon as these wafer lots have been assigned, the LB scheduling approach starts to schedule a wafer lot for each photolithography machine. This part of the scheduling task is to select the wafer lot with the biggest wait step in the queue buffer of each photolithography machine. This part of the LB scheduling approach is similar to the scheduling method used by the Least Slack time method. We can also

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introduce new wafer lots or cancel the orders (wafer lots) within the scheduling process. We use an example to demonstrate the approach. After obtaining the process flow for customer product from the database of semiconductor manufacturing, we can use a simple program to transform the process flow into our matrix representation. For a typical factory, there exists thousands of wafer lots and hundreds of process steps. We start from transforming the process pattern of each wafer lot into a task matrix. Suppose, we let rk represent the machines in the semiconductor manufacturing system; for example, the symbol r2 (k = 2) represents the photolithography machines. We use different numbers of rk together, e.g., rk, rkrk, or rkrkrkrk, …, for the task patterns to represent different process times of different photolithography or non-photolithography stages. The symbol r2x in the matrix entry [i, j] represents the wafer lot ti needs from the photolithography machine mx at sj with dedicated machine constraint, while rk (k ≠ 2) in the matrix entry [i′, j′] represents the ti′ needs from the machine type k at sj′ without dedicated machine constraint. There is no assigned machine number for the photolithography machine before the wafer lot has passed the first photolithography stage. Suppose that the required resource pattern of ti is as follows: r1r3r2r4r5r6r7r2r2r4r5r6r7r7r9r1r3r2r2r2r2r4r5r6r7r3r2r2r2r6r6r7r5r5r9 and starts the process in the factory at sj. We will fill its pattern into the matrix from matrix entry [ti, sj] to [ti, sj+35], which indicates that the total number of the steps for ti is 35. The following matrix shows the process pattern of this wafer lot ti. Two examples are used to demonstrate two different situations, with or without dedicated machine constraint, which will be depicted in the matrix. Consider the dedicated machine constraint in the first example is as follows: one wafer lot ti+1 is in the matrix having the same required resource pattern as ti but starts at s3. The wafer lot ti+k in the matrix starts from s8, and then it requires the same type of resource, the photolithography machine, but does not have the same (number) machine at the step s11. This represents that ti+1 needs the machine m1, while ti+k has not been dedicated to any machine yet. An example without dedicated machine constraint is as follows: at s12, two tasks, ti+1 and ti+k, might compete for the same resource r4 if the resource of r4 is not enough for them at that time s12. s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 .. .. .. sj .. .. sm . ti r1 r3 r2 r4 r5 r6 r7 r2 r2 r4 r5 r6 r7 r7 r9 r1 r3 r2 r2 r2 r2 .. .. ti+1 r1 r3 r2 r4 r5 r6 r7 r21 r21 r4 r5 r6 r7 r7 r9 r1 r3 r2 r2 r2 r2 .. .. ti+k .. r1 r3 r2 r4 r6 r5 .. .. .. .. .. .. .. .. .. .. .. The LB scheduling approach will use the summarized value of each dimension as the factors for the scheduling rules. For example, we can determine how many steps ti needs in order to be processed by counting the task pattern of ti dimension in the matrix. We can also realize how many wait steps ti has by counting wk from the start step to the current step of ti’s dimension in the matrix. Furthermore, if we count the rkx in sj dimension, we can know how many tasks will need the machine x of rk at sj. Let W be the set of all wafer lots in the system and the formulae of some factors are as follows:


385

How many tasks will need the resource rk at sj?

∑ {1| Matrix[ti , sj] = rk}.

RR(rk, sj) =

(2)

ti ∈W

How many tasks will wait for the resource rk at sj? WR(rk, sj) =

∑ {1| Matrix[ti , sj] = wk}.

(3)

ti ∈W

How many wait steps did ti have before the current step? W (ti ) =

current step

∑

j = start

{1| Matrix[ti , sj] = wk}.

(4)

How many steps will ti have? Steps(ti ) =

end step

∑

j = start

{1| Matrix[ti , sj] ≠ Null}.

(5)

The LB scheduling approach needs one specific factor, L, for its scheduling rule. L is defined as the wafer lots limited to the photolithography machine, p, multiplied by the remaining layers of photolithography stage these wafer lots have. L is a relative parameter, representing the load of the machine and the wafer lots limited to one machine compared to other machines. The larger L means that more required service from wafer lots is limited to this machine. Suppose that Wp is the set of all the wafer lots dedicated to the photolithography machine, p, and R(ti) is the remaining layers of the photolithography machine for ti; the definition and formula of the factor L will be as follows:

Lp =

∑

ti ∈ W p

{ti × R(ti )}.

(6)

The LB scheduling approach uses these factors to schedule the wafer lot to a suitable machine at the first photolithography stage which is the only photolithography stage without the dedicated machine constraint. Suppose we are currently at sj, and the scheduling task will start from the photolithography machine. We check if there are any wafer lots waiting for the photolithography machines at the first photolithography stage. The LB scheduling approach will assign the photolithography machine, p, with smallest Lp for them one by one. After that, these wafer lots will be dedicated to a photolithography machine. For each photolithography machine, p, the LB scheduling approach will select one of the wafer lots in Wp with the largest W(ti). The factor Lp of p will be updated after these two processes. The wafer lots in Wp that cannot be allocated to p at sj will insert a wait step, w2, for them in their process pattern. For example, at the step s11, ti has been assigned to m1; therefore, ti+1 will have a w2 inserted at s11, and all the following required resources of ti+1 will shift one step. The following matrix shows the situation.


386

ti ti+1′ ..

s9 s10 s11 s12 s13 .. .. r21 r4 r5 r6 .. w2 r21 r4 r6 ↑ → → →

s14 .. r7 r5 →

..

..

sj

..

.. ..

.. ..

..

..

sm

All the other types of machines will have same process without the need to be concerned with the dedicated machine constraint. Therefore, we assigned one of the wafer lots ti, which has the largest W(ti), then the second largest one, and so on for the machine rk. Similarly, the LB scheduling approach will insert a wk for the wafer lots that are not assigned to any machines of machine type rk (k ≠ 2) at the current step. Therefore, W(ti) represents the delay status of ti. We use the RSEM to represent complex tasks and allocate resources by the simple matrix calculation. This reduces much of the computation time for the complex problem. The RSEM provides two kinds of functions; one is that we can follow the predefined rules from expert knowledge to obtain the resource allocation result at each step quickly by some summarized factors from the task matrix. The other is that we can predict the bottleneck or critical situation quickly by executing proper steps forward. This can also evaluate the predefined rules to obtain better scheduling rules for the system at the same time.

4. SIMULATION RESULTS We have implemented a simulation program in java and have run the simulations on the NetBeans IDE 4.1 [14]. We have done two types of simulations for the LS and the proposed LB approaches. For simplifying the simulation to easily represent the scheduling methods, we have made the following assumptions: y y y y

Each wafer lot has the same process steps and quantity. Each photolithography stage has the same process time. There is no breakdown event in the simulations. There is unlimited capacity for non-photolithography machines. Table 1. Average processed steps difference between LS and LB-steps (LS-LB).

Layers Machines

8

9

10

11

12

13

14

15

Average

6 7 8 9 10 11 12 13 14 15 Average

30.00 30.80 32.45 19.82 16.51 17.72 17.81 18.15 17.85 19.06 22.02

35.95 36.03 36.73 30.12 21.17 20.26 20.65 20.85 21.55 21.70 26.50

40.51 40.15 39.52 39.40 30.46 23.88 23.64 24.56 24.55 24.34 31.10

46.42 45.28 44.03 45.11 42.58 31.51 26.86 27.45 27.70 28.18 36.51

51.82 50.27 50.15 47.00 48.29 42.04 34.55 30.66 29.75 32.27 41.68

56.49 56.76 55.44 53.13 52.54 51.82 40.56 34.66 33.08 34.25 46.87

64.23 62.05 57.74 57.59 57.84 56.42 53.79 42.41 37.37 37.76 52.72

71.63 64.88 62.43 61.40 61.72 61.53 62.41 55.94 42.89 39.23 58.41

49.63 48.28 47.31 44.20 41.39 38.15 35.03 31.84 29.34 29.60


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Table 2. Average processed steps difference between LS and LB-percentage

( LS - LB ) LS

%.

Layers Machines

8

9

10

11

12

13

14

15

Average

6 7 8 9 10 11 12 13 14 15 Average

14.5% 22.5% 35.5% 26.7% 23.5% 25.1% 25.4% 25.9% 25.6% 27.0% 25.17%

14.1% 20.1% 30.5% 33.5% 27.0% 26.3% 26.9% 27.4% 28.1% 28.3% 26.23%

13.1% 18.0% 23.8% 33.1% 33.0% 28.4% 28.5% 29.6% 29.6% 29.5% 26.67%

12.9% 16.7% 22.1% 30.4% 37.4% 32.8% 30.0% 30.8% 31.1% 31.5% 27.57%

12.7% 16.2% 21.0% 25.9% 34.2% 37.3% 34.1% 31.9% 31.6% 33.4% 27.84%

12.2% 15.8% 20.0% 24.3% 30.4% 37.7% 36.1% 33.2% 32.7% 33.6% 27.60%

12.3% 15.3% 18.3% 22.5% 28.5% 34.3% 40.1% 36.5% 34.1% 34.7% 27.66%

12.5% 14.5% 17.3% 21.3% 25.9% 32.2% 39.5% 41.2% 35.9% 34.3% 27.47%

13.04% 17.42% 23.56% 27.22% 29.99% 31.78% 32.57% 32.05% 31.08% 31.55%

To represent the different capacity and required resource demand situation for a semiconductor factory, we take into account the different photolithography machines and the wafer lots with different photolithography layers in the simulation program. Our simulation is set with 6 to 15 photolithography machines, 8 to 15 photolithography layers, and 500 wafer lots. The wafer arrival rate between two wafer lots is a Poisson distribution and we run ten-iteration for each simulation. The summary of these simulation results is shown in Tables 1 and 2. In the task patterns, the symbol r represents the non-photolithography stage; and r2 represents the photolithography stage. The basic task pattern for 8 layers is: “rrr2rrrrr2rrr rrrrrr2rrrrrr2rrr2rrr2rrr2rrr2rr”. Then the task pattern for each added layer after 8 layers is: “r2rr”. Therefore, the task pattern for 9 layers is: “rrr2rrrrr2rrrrrrrrr2rrrrrr2rrr2rrr2rr r2rrr2rrr2rr”, the task pattern for 10 layers is: “rrr2rrrrr2rrrrrrrrr2rrrrrr2rrr2rrr2rrr2rrr2r rr2rrr2rr”, …, and the task pattern for 15 layers is: “rrr2rrrrr2rrrrrrrrr2rrrrrr2rrr2rrr2rrr2 rrr2rrr2rrr2rrr2rrr2rrr2rrr2rrr2rr”. The task matrix for 15 layers looks as follows: Task Matrix (15 photolithography layers) t1 t2 ti

s1 ………………………………………………………………………………… rrr2rrrrr2rrrrrrrrr2rrrrrr2rrrr2rrr2rrr2rrr2rrr2rrr2rrr2rrr2rrr2rrr2rrr2rr rrr2rrrrr2rrrrrrrrr2rrrrrr2rrrr2rrr2rrr2rrr2rrr2rrr2rrr2rrr2rrr2rrr2rrr2rr

sm

rrr2rrrrr2rrrrrrrrr2rrrrrr2rrrr2rrr2rrr2rrr2rrr2rrr2rrr2rrr2rr……

t500

Both LB and LS approaches are applied to the same task matrix during each simulation generated by the LB scheduling approach described in section 3. The result of the simulation, as described in detail in the following subsections, shows the advantage of the LB approach over the LS approach under different numbers of machines by the average of the different photolithography layers, and under different number of layers by the average of the different photolithography machines.


388

4.1 Different Photolithography Machines

The simulation result of different machines indicates that when the capacity of the photolithography area in the manufacturing system is overloaded, i.e., the number of the photolithography machines is less than or equal to 12 in this simulation, the LB approach performs better than the LS approach with more photolithography machines. The outperformance of the LB approach climbs from 13.04% to 32.57%, and from 6 to 12 photolithography machines. When the capacity is under-loaded, the advantage of the MSS approach will decrease, but the performance of the LB approach is still better than the LS approach. The advantage of the LB approach is 32.05%, 31.08%, and 31.55% for 13, 14, and 15 photolithography machines, respectively. The simulation result is shown in Fig. 3 (a). Steps

%

60

40% 49.63

50

48.28

47.31

44.20

40

27.22%

29.99%

30% 41.39

23.56%

30

31.78% 32.57% 32.05% 31.08% 31.55%

38.15

35.03

31.84

17.42%

20

Step

13.04%

20% 29.34

29.60 10%

%

10 0 6

7

8

9

10

11

12

13

14

(a) Simulation-different machines.

Steps

%

70

27.47%

60 50

25.17%

26.23%

26.67%

27.57%

27.84%

58.41

41.68

30

30%

27.60% 27.66% 52.72

40

20

0% 15 Photo machines

20%

46.87

36.51 26.50

31.10

Step

%

10%

22.02

10 0 8

9

10

11

12

13

14

0% 15 Photo Layers

(b) Simulation-different layers. Fig. 3. Simulation results − different photolithography machines and layers.

4.2 Different Photolithography Layers

On the other hand, the simulation result of different layers indicates that the LB approach performs better than the LS approach with more photolithography layers. However, there is no significant difference with different photolithography layers. The outperformance in percentage of the LB approach is between the minimum, 23.75%, to the maximum, 25.01%. Such simulation result is shown in Fig. 3 (b).


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We applied the LS and LB for these two photolithography machines to select the next wafer lot in the simulations. When the wafer lot needs to wait for its dedicated machine, we insert a “w” in the process pattern of the wafer lot to represent the situation. After finishing the simulations, we count the numbers (“rk” and “wk”) in the pattern of wafer lots to realize how many steps they used. We ran ten iterations for both Simulation I and II. Fig. 3 shows the simulation results. Although the simulations are simplified, they reflect the real situation we met in the semiconductor factory. With the constraint of the photolithography machine and applying LS, two machines become load-unbalancing during the simulations. Moreover, the thrashing phenomenon happened in the simulations. It’s not difficult to extend the simulation with more machines, wafer lots, and stages. Moreover, we can use different numbers of “r2” (e.g., “r2”, “r2r2”, or “r2r2r2r2”) together for the task patterns to represent different process time for different photolithography stages. In the simulations, the more constrained photolithography stages the wafer lots have, the better the LB approach is than the LS method.

5. CONCLUSION To provide the solution to the issue of load balancing among photolithography machines and the new dedicated photolithography machine constraint, the proposed Load Balancing (LB) scheduling approach based on Resource Schedule and Execution Matrix (RSEM) has been presented. The simulations have shown that the proposed LB approach is better than the traditional Least Slack (LS) time method. In addition, the architecture of the RSEM is easy for practicing other manufacturing problems in the area with a similar constraint. In future work, we want to apply machine learning to set the weight of factors automatically depending on the status of the production line. Some experienced managers can only set the weight of factors according to their special needs manually. Moreover, in order to speed up the load balancing status, we need to develop a strategy for transferring wafer lots from congested machines to other machines, e.g., a machine that is recovering from a long-term breakdown or a new machine joined in the production system. The rules for which wafer lots will be transferred between machines should be included in the scheduling system as well.

ACKNOWLEDGEMENT The authors would like to thank the anonymous reviewers for their valuable comments and helpful suggestions. A. Shr is grateful to Ms. Victoria Tangi and Ms. Erin Sinclair for English proofreading.

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2. P. R. Kumar, “Scheduling manufacturing systems of re-entrant lines,” Stochastic Modeling and Analysis of Manufacturing Systems, in D. D. Yao ed., Springer-Verlag, New York, 1994, pp. 325-360. 3. S. C. H. Lu, D. Ramaswamy, and P. R. Kumar, “Efficient scheduling policies to reduce mean and variance of cycle-time in semiconductor manufacturing Plants,” IEEE Transactions on Semiconductor Manufacturing, Vol. 7, 1994, pp. 374-385. 4. W. J. Hopp and M. L. Spearman, Factory Physic: Foundations of Manufacturing Management, McGraw-Hill Press, New York, U.S.A., 2000. 5. E. Akcalt, K. Nemoto, and R. Uzsoy, “Cycle-time improvements for photolithography process in semiconductor manufacturing,” IEEE Transactions on Semiconductor Manufacturing, Vol. 14, 2001, pp. 48-56. 6. T. Miwa, N. Nishihara, and K. Yamamoto, “Automated stepper load balance allocation system,” IEEE Transactions on Semiconductor Manufacturing, Vol. 18, 2005, pp. 510-516. 7. A. Arisha and P. Young, “Intelligent simulation-based lot scheduling of photolithography toolsets in a wafer fabrication facility,” in Proceedings of the 36th Conference on Winter Simulation, 2004, pp. 1935-1942. 8. L. Mönch, M. Prause, and V. Schmalfuss, “Simulation-based solution of load-balancing problems in the photolithography area of a semiconductor wafer fabrication facility,” in Proceedings of the 33rd Conference on Winter Simulation, 2001, pp. 1170-1177. 9. S. Kumar and P. R. Kumar, “Queuing network models in the design and analysis of semiconductor wafer fabs,” IEEE Transactions on Robotics and Automation, Vol. 17, 2001, pp. 548-561. 10. S. H. Lu and P. R. Kumar, “Distributed scheduling based on due dates and buffer priorities,” IEEE Transactions on Automatic Control, 1991, pp. 1406-1416. 11. A. M. D. Shr, A. Liu, and P. P. Chen, “A load balancing scheduling approach for dedicated machine constraint,” in Proceedings of the 8th International Conference on Enterprise Information System, Vol. 2, 2006, pp. 170-175. 12. A. M. D. Shr, A. Liu, and P. P. Chen, “A heuristic load balancing scheduling method for dedicated machine constraint,” in Proceedings of the 19th International Conference on Industrial, Engineering & Other Applications of Applied Intelligent Systems, LNAI 4031, Springer-Verlag, Berlin Heidelberg, 2006, pp. 750-759. 13. A. M. D. Shr, A. Liu, and P. P. Chen, “A load balancing method for dedicated photolithography machine constraint,” in Proceedings of IFIP International Federation for Information Processing, Information Technology for Balanced Automation Systems, Vol. 220, 2006, pp. 339-348. 14. NetBeans IDE, http://www.netbeans.org/.


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Arthur M. D. Shr (施明德) received his M.S. and Ph.D. degrees in Electrical Engineering from National Chung Cheng University, Chiayi, Taiwan, in 1997 and 2006, respectively. He received an award of Graduate Students Research Abroad Program sponsored by National Science Council, Taiwan to be a Visiting Researcher of Computer Science at Louisiana State University, USA from August 2003 to August 2005. Since September 2006, he has been a Postdoctoral Researcher of Dr. Peter Chen’s Research Group at Computer Science of Louisiana State University, USA. His research interests include knowledge representation, software engineering, and semiconductor manufacturing scheduling. He is also a member of IEEE and ACM. Alan Liu (劉立頌) received his M.S. and Ph.D. degree in Electrical Engineering and Computer Science from the University of Illinois at Chicago, USA in 1989 and 1994, respectively. He is a professor in the Department of Electrical Engineering and Center for Telecommunication Research, National Chung Cheng University, Chiayi, Taiwan. His research interests in artificial intelligence and software engineering include knowledge acquisition, requirements analysis, intelligent agents, and applications in embedded systems and robotic systems. He is also a member of IEEE, ACM, TAAI, and SEAT. Peter P. Chen (陳品山) is a M.J. Foster Distinguished Chair Professor of Computer Science at Louisiana State University, USA. Professor Chen has taught at MIT, UCLA, and Harvard. He is internationally known for his work on the Entity-Relationship (ER) model. He has received many awards including ACM/AAAI Allen Newell Award, IEEE Harry Goode Award, Pan Wen-Yuen Outstanding Research Award, DAMA International Achievement Award, and Stevens Software Method Innovation Award. Professor Chen is the Principal Investigator of a large NSF-funded multi-disciplined project on profiling of terrorists and malicious cyber transactions for counter terrorisms and crimes, and is the Principal Investigator or Co-Principal Investigator of several other projects funded by different government agencies. Professor Chen is also active in Digital library research and construction. He is assisting Dr. Raj Reddy of Carnegie-Mellon University (CMU) to create a large digital library of over one million books. He has been the principal investigator of various research projects in system architecture, information/knowledge management, software engineering, and performance analysis sponsored by many government agencies and commercial companies. He has also been listed in “Who’s Who in America” and “Who’s Who in the World” for more than 17 years.