IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 3, MAY 2012
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Logic Inverter Implemented with CVD-Assembled Graphene FET on Hexagonal Boron Nitride Edwin Kim, Nikhil Jain, Yang Xu, and Bin Yu, Fellow, IEEE
Abstract—We demonstrate one of the basic building elements of graphene electronics, logic inverter, based on graphene-on-boron nitride material system. The inverter is composed of two adjacent graphene-channel field-effect transistors (GFETs). The impacts of hexagonal boron nitride, a new supporting substrate material, on major device performance metrics of GFET such as smallsignal transconductance gm and effective carrier mobility μe ff are explored. The prototype of logic inverter is demonstrated on a single sheet of CVD-assembled monolayer graphene based on the unique ambipolar conduction behavior of the 2-D nanoscale carbon system. Index Terms—Carrier mobility, carbon circuit, field-effect transistor, graphene, hexagonal boron nitride.
I. INTRODUCTION RAPHENE field-effect transistor (GFET) could be the basic building element for future carbon-based electronics owing to the excellent material properties of 2-D carbon nanostructure, i.e., ultra-high carrier mobility and thin-film-like configuration that have good compatibility with the existing semiconductor chip fabrication techniques [1]. Since the discovery of graphene in 2004, a significant amount of experimental device research efforts have been made, largely using graphene flakes exfoliated mechanically from high-purity graphite. The ultimate demand for large-scale manufacturing-worthy fabrication of carbon electronics motivates on-chip chemical synthesis of graphene sheets [2]. Several approaches have been demonstrated to synthesize graphene, including epitaxial growth on the SiC substrate [3] and chemical vapor deposition (CVD) on selected catalytic metal (e.g., Ni [4] or Cu [5]). Supporting substrate material plays a key role in preserving the intrinsically superb carrier transport properties of graphene system. Several materials, e.g., hexagonal boron nitride (h-BN)
G
Manuscript received September 19, 2011; accepted February 9, 2012. Date of publication February 22, 2012; date of current version May 9, 2012. This research was partially supported by National Science Foundation (NSF) under Grant ECCS-1002228 and Grant ECCS-1028267, and the IBM Faculty Award. The review of this paper was arranged by Associate Editor F. Lombardi. E. Kim was with the College of Nanoscale Science and Engineering, State University of New York, Albany, NY 12203 U.S.A. He is now with Ramtron International Corporation, Colorado Springs, CO 80921 U.S.A (e-mail: edwin.
[email protected]). N. Jain and B. Yu are with the College of Nanoscale Science and Engineering, State University of New York, Albany, New York 12203 USA (e-mail:
[email protected]). Y. Xu is with Department of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TNANO.2012.2188413
and hexamethyldisilazane, have been proposed to improve the electrical transport behavior of graphene. The h-BN substrate has been recently demonstrated to help improving the graphene electronic performance by screening out undesirable carrierscattering effects commonly observed in graphene/SiO2 system [6], [7]. In this paper, we aim to investigate the impacts of the h-BN substrate and device scaling on key performance metrics of GFETs [8] based on the graphene-on-boron-nitride material system. h-BN is an insulating isomorph of graphite with B and N atoms occupying the equivalent A and B sublattices in the Bernal structure. It is relatively inert and expected to be free of dangling bonds or surface charge traps. The atomically planar surface should suppress the rippling in graphene sheet. With bandgap EG = 5.97 eV and dielectric constant ε ≈ 4 (close to that of SiO2 ), h-BN has negligibly small lattice mismatch (∼1.7%) with graphene and, thus, is an ideal substrate material for carbon-based electronics. Our previous research results showed that GFETs with graphene channel on the h-BN substrate have exhibited improved small-signal transconductance and effective carrier mobility, as compared with GFET on the SiO2 substrate [9]. Logic gates with single GFET [10] or complementary pair of GFETs [11] have been previously demonstrated utilizing exfoliated graphene on SiO2 . In this paper, we report functional logic inverter composed of two GFETs with CVD-assembled graphene monolayer on h-BN multilayer, a material system that has great potential in implementing future performance-driven carbon-based nanoelectronics. II. GRAPHENE ON HEXAGONAL BORON NITRIDE The material system for fabricating GFETs is schematically shown in Fig. 1(a). Thermal-oxide-coated silicon has been commonly used as the substrate for either exfoliated graphene or transferred CVD-grown graphene. Raman spectra were collected to identify the location of both monolayer graphene and h-BN sheets. As shown in Fig. 1(b), Raman spectrum yields two signature peaks in G and 2-D lines for monolayer graphene (measured at the specific location as marked by a red dot in the inset image). A thin multilayer h-BN flake with a thickness of a few nanometers (confirmed by atomic force microscope (AFM) scanning) was placed underneath the CVD-assembled graphene sheet. The G/2-D ratio is less than 0.5, which is typically reported for monolayer graphene. A weak peak in D-line at about 1366 cm−1 represents the existence of h-BN [12]. The device fabrication is schematically shown in Fig. 2. Thin multilayer h-BN flakes were mechanically exfoliated from the chemically synthesized high-quality h-BN nanocrystal onto 100-nm thermal SiO2 -coated silicon substrate (boron-doped). A monolayer graphene was then transferred onto the h-BN sheet
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Fig. 3. CVD-assembled graphene on the SiO2 substrate is heavily p-type doped as indicated by the peak location in the measured R-VB G curve, whereas the CVD-assembled graphene on the h-BN substrate shows only weak n-type doping. The different types of doping are compared with the apparently dopingless exfoliated graphene on the SiO2 substrate.
Fig. 1. (a) Multilayer h-BN is sandwiched between graphene and SiO2 -coated Si substrate. The undesirable carrier-scattering effect from oxide is screened out by thin h-BN multilayer. In consequence, improved electrical performance is expected in GFET. (b) Both graphene and h-BN sheets can be identified with signature peaks observed in Raman spectra.
Fig. 2. Schematic showing the fabrication process for implementing GFET with CVD-assembled graphene on exfoliated h-BN multilayer. The transfer of CVD graphene is followed by electron-beam pattering of the active channel area for GFET. Source and drain contacts are formed by metal lift-off process.
after metal (Cu)-catalytic CVD growth. Using CH4 (300 sccm) as the precursor, monolayer graphene was grown on Cu foil for 30 min after a Cu preannealing process conducted at high temperature (1000 ∞C). Once graphene was grown on Cu surface, polymethyl-methacrylate (PMMA) was spin-coated on one side of the graphene. Cu was then etched away using wet chemistry (FeCl3 ·6(H2 O) solution). After the PMMA (along with
graphene) was physically transferred onto the target substrate, it was removed with acetone, and graphene monolayer positions itself on the target substrate with h-BN flakes. Once the positions of h-BN and graphene were identified, a graphene-etching step was involved to pattern the active channel area of GFET. Positive photoresist (PMMA) was spin coated, followed by electron-beam lithography (EBL) process. After pattern development in 1:3 MIBK:IPA, the active area (covered by PMMA) was protected, while the uncovered area was removed during the plasma O2 etching. The source and drain contacts of the GFET were made by EBL patterning, evaporation of Ti (5 nm) and Pt (30 nm), and subsequent lift-off process. Fig. 3 shows the measured graphene channel resistance R as a function of back gate bias VBG obtained with VBG sweeping. Three material systems were examined: CVD-graphene on SiO2 , CVD-graphene on h-BN, and exfoliated graphene on SiO2 . The Dirac point VDirac of the exfoliated graphene on SiO2 is normally located around VBG = 0. However, CVD-assembled graphene on SiO2 is p-type heavily doped, since the hydroxide ion (OH− ) is so easily coupled to the dangling bond of the SiO2 surface that the measured R–VBG plot shows a large positive VDirac [13], [14]. On the other hand, CVD-assembled graphene on h-BN exhibits weak n-type doping largely due to the PMMA residue introduced during graphene transfer process [15]. We perform experimental investigation of the impacts of combined channel/substrate material system and device scaling on key device performance metrics of GFET. The small-signal transconductance is calculated by differentiating drain current (ID ) with respect to VBG , that is, gm = dID /dVBG . The GFETs on either h-BN or SiO2 substrate were examined. It was found that gm of GFET on h-BN is improved by 10 times over that of GFET on SiO2 with physical gate length (LG ) in the range of 500 nm in Fig. 4. The effective carrier mobility was extracted from the empirical expression of μeff = gd LG /WCox VBG with the drain conductance given by gd = dID /dVDS and the gate capacitance by Cox = εr ε0 /tox . Here VDS and tox are drain– source voltage bias and gate oxide thickness, respectively. The effective carrier mobility of GFET on the h-BN substrate is about 3–4 times higher as compared with that of GFET on the SiO2
KIM et al.: LOGIC INVERTER IMPLEMENTED WITH CVD-ASSEMBLED GRAPHENE FET ON HEXAGONAL BORON NITRIDE
Fig. 4. (a) Small-signal transconductances of the GFETs (gate length: 500 nm) with CVD-assembled graphene on two different substrates, SiO2 and h-BN, respectively. (b) Extracted carrier mobility of the GFET with CVD-assembled graphene on SiO2 and h-BN.
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Fig. 6. (a) Measured R-VB G characteristics of two GFETs, “2–3” (right) and “4–3” (left). Differential channel doping is observed. (b) Transfer characteristic for GFET “2–4” is depicted with the sweeping of gate voltage VB G .
III. EXPERIMENTAL RESULTS AND DISCUSSION A. Graphene FETs Implemented on the h-BN Substrate
Fig. 5. Four independent GFETs were fabricated with the common source (#3) shared by all devices made on h-BN (encircled by blue dashed line). The red dotted lines show the patterned graphene active areas. The cross-sectional view of the fabricated GFET is also schematically shown.
substrate. The superior electrical behavior suggests that h-BN could be an excellent substrate material for high-performance graphene-based logic circuits.
To demonstrate working graphene circuit on the h-BN substrate, we implement a complementary logic inverter prototype. Fig. 5 shows the image of the four neighboring GFETs and the schematic view of the cross-sectional structure. These GFETs were fabricated with CVD-assembled graphene monolayer on h-BN (encircled by blue dashed line). The red dotted lines show the patterned graphene active areas (1-μm-wide graphene stripes located underneath the metal contacts with 2-μm gap, i.e., gate length). The thickness of h-BN is confirmed to be less than 4 nm by AFM measurement. Among the GFET devices (“1–3”, “2–3”, “4–3”, and “5–3” as labeled by a pair of drain–source contact pads) with common source contact (#3), doping variation is observed in micron-scale area most likely due to local PMMA residues generated during the graphene transfer process. In Fig. 6(a), two GFETs (“2–3” and “4–3”) with differentially doped channels are compared. The doping of graphene is indicated by the position of the Dirac voltage, VDirac , measured from the R–VBG curves. In this experiment, two GFETs are denoted as RQN (“4–3” in the left) and RQP (“2–3” in the right), respectively. When the current between metal contacts 2 and 4 was measured, the transfer characteristic of GFET “2–4” is shown in Fig. 6(b). As VBG sweeps, three different junction configurations are observed with two GFETs connected in series [16]: PP, PN and NN for VBG < VDirac -N , VDirac -N < VBG < VDirac -P ,
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IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 11, NO. 3, MAY 2012
Fig. 7. (a) GFETs 2–3 and 4–3 are identified as p-type and n-type transistors depending on doping to make up of the complementary logic inverter. (b) Schematic of traditional complementary logic inverter is depicted.
and VDirac -P < VBG , respectively, where VDirac -N and VDirac -P represent the two Dirac voltages (VDirac -N < VDirac -P ). B. Graphene-Based Inverter on the h-BN Substrate Fig. 7 is the schematic view of a logic inverter composed of a pair of two GFETs connected in series. The p-type and ntype GFETs (denoted with QP and QN , respectively, as shown in the figure) are identified using the measured R–VBG curves as shown in Fig. 6. From the transfer characteristics of each individual GFET, the total electrical resistance R and conducting current I can be analyzed. The total R and I in the inverter (“2–4”) are calculated with two individual curves of QP and QN for VDD = 10, 20, and 40 mV, respectively, and with VDS = VDD /2: R(VDD ) = a × RQN (VDS ) + b × RQP (VDS ) and I(VDD ) = c × iDN (VDS ) + d × iDP (VDS ). Here, R(VDD ) and I(VDD ) are the total resistance and the drain current as functions of VDD . RQN (VDS ), RQP (VDS ), iDN (VDS ) and iDP (VDS ) are measured GFET resistances and drain currents for QN and QP , respectively, with a ≈ 0.8, b ≈ 1, c ≈ 0.6 and d ≈ 0.4. Given the analytical equation earlier, the output voltage
Fig. 8. (a) Measured VIN –VO U T transfer characteristics at VD D = 10, 20, and 40 mV. The output voltage swing (ΔVO U T ) can be increased as VD D increases. It should be noted that the full transfer is observed only in the PN region. (b) For VD D = 40 mV, the graphene inverter transfer characteristics in the PN region is shown (with the inset showing the typical transfer characteristics of a Si CMOS inverter).
(VOUT ) is obtained by VOUT (VDD ) =
VDD × RQN (VDS ) . (RQN (VDS ) + RQP (VDS ))
It is observed that in the PP and NN regions of the graphene logic inverter, VOUT shows nonlinear response (see Fig. 8). On the other hand, the full transfer response only occurs in the PN region. The demonstrated VOUT –VIN responsive behavior of the graphene inverter is attributed to the ambipolar conduction property of the GFETs. In Fig. 8(b), the full transfer behavior in the PN region is shown, similar to what is observed in a traditional Si CMOS inverter [17] (see inset of the figure). In each operating region of the transfer characteristic of a CMOS inverter, p-type and n-type MOSFETs are in linear, saturated, and cutoff modes, respectively, resulting in the shown transfer curve. Fig. 9 shows the power consumption in the graphene inverter along with the total resistance R, the total current I, and the output voltage VOUT . It is interestingly noted that the total power is in the same shape as the current. To reduce the power consumption, smaller current should be induced since the current is the dominant factor. However, at lower VDD , the output voltage swing, ΔVOUT , is proportionally reduced. With the demonstration result, we expected that the input voltage can be much reduced by scaling down the gate insulator thickness and the output swing could be increased by raising drain bias VDS . The input voltage range could be also adjusted
KIM et al.: LOGIC INVERTER IMPLEMENTED WITH CVD-ASSEMBLED GRAPHENE FET ON HEXAGONAL BORON NITRIDE
Fig. 9. For VD D = 40 mV, the total resistance R, current I, output voltage VO U T , and total power consumption are plotted. The power dissipation is determined primarily by the current.
by increasing the doping level of differential nature through demonstrated method such as electrical-stressing-induced doping in graphene [18]. IV. CONCLUSION In summary, GFETs were fabricated with CVD-assembled monolayer graphene channel on either the SiO2 or thin multilayer h-BN substrate. Key device performance metrics such as small-signal transconductance and effective carrier mobility can be largely improved with the multilayer h-BN substrate. Graphene inverter logic was demonstrated on the h-BN substrate. Although further improvement of operation (e.g., input voltage range and output voltage swing) can be achieved via device scaling and optimization, the result suggest that h-BN could be a viable supporting substrate material for high-performance carbon-based electronics.
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