Loop-based Interconnect Modeling and Optimization Approach for Multi-GHz Clock Network Design Xuejue Huang, Phillip Restle1, Thomas Bucelot1, Yu Cao, and Tsu-Jae King EECS Department, University of California, Berkeley, CA Tel: (510) 642-1010; FAX: (510) 643-2636; email:
[email protected] 1 IBM T.J. Watson Research Center, Yorktown Heights, NY
ABSTRACT An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip. I.
single line
…
VDD CLK GND
VDD
… W CLK WGND
multiple split-line
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S
…
INTRODUCTION
In modern multiple-layer interconnect design, global clock distribution usually uses thick top-level copper lines and is routed with large dimensions to reduce line resistance. With the fast increase of clock frequency and low line resistance, inductance has now become a first-order effect for global clock distribution design. The most accurate way of analyzing inductance effects in complex structures is to carry out Partial Element Equivalent Circuit (PEEC) analysis, which uses the concept of partial inductance [1]. However, because of the dense inductance matrix involved, this method is computationally expensive. More efficient methodologies are preferred to enable fast optimization and physical design exploration in the design and simulation of complex networks. One major complication of inductance analysis is the difficulty in determining current return paths in advance. But in the case of clock nets, wires are highly optimized and usually have VDD/GND shields to provide close return paths and to limit signal line coupling. Also, wide lines are usually split into multiple fingers interspersed with VDD/GND shields in order to suppress inductive ringing, and reduce delay [2]. In these special cases, the current return loops are relatively well defined or can be estimated. Therefore, it is feasible to use a loop-based method, in which the entire signal and return loops of single or multi-line structures are modeled with equivalent loop resistances (Rloop) and inductances (Lloop) (Fig. 1). The simulation complexity is greatly reduced using this method, as all mutual inductance terms are eliminated and the number of components in the circuit simulation is greatly reduced.
Rloop_N C/2
Lloop_N C
Figure 1. Proposed loop-based RLC modeling approach. Single and multiple split clock lines together with their ground returns are represented by a single chain of loop resistance, loop inductance and capacitance.
Inductance affects delay and ramp rate, and causes signal ringing. Also, the interaction between resistance and inductance at high frequencies will cause line and loop proximity effects that become important when chip frequencies reach the GHz regime (Fig. 2). At high frequency, the magnetic field generated by neighboring lines will change the current distribution in the conductor and result in higher current density at the edge of the lines. This is referred to as the line proximity effect or current crowding. Also at different frequencies, the current return loop distributes differently to minimize the overall reactance of the circuit. At low frequencies, inductive reactance is negligible and the currents spread out to minimize resistance. At high frequencies, inductive reactance dominates resistance, and the currents return through close neighbors to minimize inductance. This is called the loop proximity effect. These proximity effects lead to frequencydependent loop resistance and inductance. In this paper, we propose analytical models for the line and loop proximity effects. Based on these models, a complete loop-based interconnect modeling approach is developed for well-shielded wiring such as clock distribution networks, in which the Rloop and Lloop are calculated from analytical equations as a function of frequency and interconnect geometry.
low frequency: larger return loop
high frequency: smaller return loop
Physical Approximation
By
B0 =
µ0 2πP
I0
Ez y
(b)
z
Figure 2. Line and loop proximity effects. (a). Line proximity effect. Current crowds at the edges of the metal line at high frequency. Odd mode coupling is shown. (b). Loop proximity effect. Current return loop shrinks with increased frequency.
where RDC is the line DC resistance, and Rsheet is the sheet resistance. B. Loop proximity effect model
We first derive the analytical models for the line and loop proximity effects, and later combine them into a complete loop RLC model. A. Line proximity effect model The line proximity effect (Fig. 2(a)) is important at lower frequencies than the skin effect and is significant for many on-chip interconnects designed today. It causes the increase of line resistance above its DC value at high frequencies. We used a similar model as [3] developed for current crowding effects in RF inductors. The approximations for B and E fields inside the conductor are illustrated in Fig. 3. µ B0 = 0 I 0 2πP (1)
µ0 I 0 (at line edge) 4πP Here µ0 is the permeability of free space, P is the wire pitch (=W+S), I0 is the excitation current, and σ is the conductivity of the metal. The eddy current on each edge is approximated by a uniform current flowing within the outer 25% of the wire width: J eddy ( f ) = σE = σωW
l 1 / 4W µ l d 3 / 4W 3 3 µ l ≈ 0 [ln( )+ ] ) + ] ≈ 0 [ln( π W +t π 1 / 4W + t 2 2
Reddy = 2 × R sheet Leddy
(2)
where l is the wire length, and t is the thickness. These results can be combined to approximate the effective resistance Reff by setting I02Reff equal to the power dissipated: I eddy 2 2 Power = I 02 R0 + I eddy ( f ) R eddy = I 02 [ R DC + ( ) R eddy ] I0 (3) I eddy 2 ⇒ R eff ( f ) = R DC + ( ) Reddy I0 1 µ W2 ⇒ R eff ( f ) = R DC [1 + ( 0 f )2 ] 2 R sheet P
x W/2 E, Jeddy approximation
-W/2
Figure 3. Approximations of the B field, induced E field and eddy current profiles within the wire.
II. LOOP RESISTANCE AND INDUCTANCE MODEL
v ∂E z ∂B y = − jωB y , ⇒ E z = − jω ∫ B y dx ∇×E = =− ∂t ∂x
x
Loop proximity effect (Fig. 2(b)) leads to the increase of return resistance and the decrease of loop inductance at high frequencies. For example, in the case of four neighboring ground shields (two on each side) next to the center clock signal), assuming same widths and spacings for all wires, the current return in the nearest neighbor (I1) versus total current (I0) increases with frequency: R + jω ( L + M 1 − 2 M 2 − M 3 + M 4 ) I1 = I 0 4 R + 2 jω ( 2 L − 2 M 1 + M 2 − 2 M 3 + M 4 ) (4) ⇒
R 2 + ω 2 ( L + M 1 − 2M 2 − M 3 + M 4 ) 2 I1 = I0 16 R 2 + 4ω 2 (2 L − 2 M 1 + M 2 − 2 M 3 + M 4 ) 2
where M1, M2, M3, and M4 are the mutual inductances to the nth order neighbor. I1/I0 and I2/I0 versus frequency are plotted in Fig. 4. Note that in real circuits where the number of neighboring power lines are much more than four, the I1/I0 ratio will saturate at much lower frequency. We choose to approximate this loop frequency dependence with an exponential function: LoopFactor = (1 − p1 e − f / p2 ) / 2
The factor 1/2 comes from the fact that at extremely high frequency, most currents will only return through the nearest two neighboring wires. There are two fitting parameters p1 and p2 in this equation, which can be extracted from comparing with full-wave simulation results. 0.45
I2 I1 I0 I1 I2
0.40
I1 : I0
0.35 0.30
In : I0
(a)
0.25 0.20 0.15
I2 : I0
0.10 0.05
1E7
1E8
1E9 1E10 1E11 1E12
Frequency (Hz) Figure 4. With increased frequency, more current will return through the nearest neighbor (I1) and less through farther lines (I2). Here four neighboring wires (two on each side) are assumed.
Based on the above proximity effects models, we could derive the loop resistance and inductance models for a single clock line case (Table 1). The frequency f can be expressed as 0.1/tr, where tr (in ps) is the typical 30%-70% rise time at the far-end of the line. The loop inductance (Lloop_1) is calculated based on coupling capacitance, interconnect geometries, and frequency. Theoretically the loop inductance at infinite frequency L∞ is given by: L∞ = 1 /(v 2Clat ) where v is the speed of light in the dielectric, and Clat is the lateral capacitance. At finite frequencies, the inductance values are adjusted by factor kL, which consists of the same loop proximity effects term [(1 − p1 e − f / p ) / 2] as in the Rloop_1 model and a spacing adjustment term k1ln(S) + k2, with fitting parameters k1 and k2. The spacing adjustment term comes from the fact that inductance changes more slowly with spacing (S) than capacitance does (to the first-order, 1/C ∝ S and mutual inductance LM ∝ ln(S)). 2
D. Loop resistance and inductance model for multiple split clock lines
Table 1. Loop Resistance and Inductance Models for A Single Shielded Clock Line Rloop _ 1 = RCLK ( f ) + RGND ( f ) ⋅ (1 − p1e − f / p2 ) / 2 2
1 µW RGND ( f ) = RDC _ GND [1 + ( 0 GND f ) 2 ] 2 Rsheet P
Lloop _ 1 = k L ⋅ L∞ kL =
1 (1 − p 1 e − f / p 2 ) / 2 ⋅ [k 1 ln( S ) + k 2 ]
Table 2. Loop Resistance and Inductance Models for Multiple Shielded Clock Lines Rloop _ N =
Rloop _ 1
N aR WGND aR = kR + bR WCLK + S
parameters: kR = 0.17, bR = 0.72 Lloop _ N =
Lloop_N
80
aL = kR ,L
Lloop _ 1 aL
N WGND + bL WCLK + S
parameters: kL = 0.27, bL = 0.78
1.5
2.0
2.5 1.5
Wclk = Wgnd Lloop model
70 60
1.0
50 40
0.5 WCLK = WGND WCLK : WGND = 1.8 : 1 Rloop model
30 20
5
6
7
8
9
0.0
WCLK + WGND (µm)
Figure 5. Single line loop resistance and inductance model verification with full-wave simulation results. (All simulations with L = 5mm, input tr = 20ps, CL = 1pF)
70
2.5 structure1 2.0 structure2 1.5 RN and LN model 1.0
60
0.5
50
0.0
40
-0.5
30
-1.0
20
-1.5
10
-2.0
100 90
Simulation:
80
0
0
1
2
3
4
5
6
7
Number of parallel lines
8
9
Loop Inductance (nH)
parameters: k1 = 0.86; k2 = 2.78
Rloop_N
Spacing (µm) 1.0
2
parameters: p1 = 0.68; p2 = 5.88
Lloop_1
We used a full-wave PEEC interconnect transient analysis tool as a model development reference and verification target [4]. Loaded line structures are used with a large power mesh to represent a realistic on-chip environment. We found that eight ground lines (four on each side) next to the most outside clock wire was sufficient to represent the actual chip envi-
Loop Resistance Rloop (Ohm)
Rloop_1
1 µW RCLK ( f ) = RDC _ CLK [1 + ( 0 CLK f )2 ] 2 Rsheet P
III. MODEL VALIDATION THROUGH FULL-WAVE SIMULATION AND INTERCONNECT OPTIMIZATION
Loop Inductance Factor kL
The multi-line loop resistance (Rloop_N) and inductance (Lloop_N) are calculated based on the single line loop resistance (Rloop_1) and inductance (Lloop_1) (Table 2). We found that, both effective resistance and inductance are larger than what the simple parallel rule gives (Rloop_N = Rloop_1 / N, Lloop_N = Lloop_1 / N),
because the shield wires are now shared by more clock lines, and the inductive coupling between the split clock wires is additive. These are modeled through parameters aR and aL as exponents of N, both of which are less than 1. They are both functions of interconnect dimensions. For typical on-chip interconnect geometries, aR is usually in the range of [0.8, 0.85], and aL in the range of [0.9, 1]. Note that in the case of a multiple split line, the resistance increase over the parallel rule is usually more significant than that of the inductance. To construct the full RLC chain, the capacitance values can be calculated from a lookup table or closed form expressions, as they are relatively frequency-independent.
Loop Resistance Rloop (Ohm)
C. Loop resistance and inductance model for single shielded clock line
-2.5
Figure 6. Multi-line loop resistance and inductance model verification with full-wave simulation results. (Structure 1: WCLK = 2.9µm, WGND = 1.6µm, S = 0.9µm Structure 2: WCLK = WGND = 4.5µm, S = 1.8 µm)
105
60
Delay (ps)
95
50 40
90 85
30
80
20
75 10
70 65
5
6
7
8
9
30%-70% Rise Time (ps)
WCLK = WGND WCLK / WGND optimized
100
0
WCLK + WGND (µm) Figure 7. Improved performance achieved from WCLK and WGND ratio optimization.
Figure 8. Die photo of Power4 with the outline of the clock network.
ronment. For all simulations we assumed symmetrical shielding, which means same spacing on both sides of the clock wire, and same number and width for all ground wires. An HSPICE optimization function is used to extract the loop resistance and inductance values from matching delay, rise time and peak noise values from full-wave simulation results. Fig. 5 and Fig. 6 demonstrate excellent matching between the simulated Rloop and Lloop values for both single and multi-line cases and different interconnect geometries. Based on the above loop resistance and inductance models, we can analytically optimize the ratio of WCLK and WGND to minimize effective loop resistance and inductance at fixed routing area. It is found that optimal Signal-to-Return wire width ratio is ≈ 0.9-0.95 (WCLK : WGND ≈ 1.8-1.9). This ratio decreases (which means WGND needs to increase) with increasing frequency because of increased ground return resistance. Fig. 7 shows that with the same routing, optimized WCLK : WGND can reduce delay by ~ 9%, and rise time by ~21% comparing with WCLK = WGND case. It is worth mentioning that, in actual designs, other considerations like wire congestion, noise and IR drop on power lines are also important considerations in deciding interconnect geometries.
IV. MODEL VERIFICATION WITH MEASUREMENT DATA We simulated our RLC models and compared the results with measurement data from a Power4 chip in 0.18µm copper technology. The RLC models are implemented replacing each clock wire (or multiple split wires) together with their ground shields by a single chain of loop RLC calculated from our proposed analytical equations. Fig. 8 shows a die photo of a Power4 chip with outlines of the on-chip clock network. Fig. 9 shows the comparison of both near-end (inverter output) and far-end (circled) waveforms from measurement and simulation results based on the proposed loop RLC model. Assuming a good driver model, our proposed interconnect model is very accurate for both ramp rate and skew predictions.
simulation using the proposed model measurement data
Figure 9. Comparison of measured waveform from Power4 chip and the model prediction.
V. CONCLUSIONS In this paper we proposed a loop-based interconnect modeling approach for clock network design. It is highly efficient, as all the neighboring wire and ground shields are modeled as a single loop RLC chain, all mutual inductance terms are eliminated, and the loop RL values are calculated directly from analytical models. The model captures critical high frequency effects including inductance, line and loop proximity effects and is suitable for multi-GHz clock design and tuning. It accuracy is verified from comparison with fullwave simulation and measurement results. REFERENCES [1] [2] [3] [4]
A. E. Ruehli, “Inductance Calculation in a Complex Integrated Circuit Environment,” IBM Journal of Research and Development, Vol. 16, No. 5, pp. 470-481, September 1972. Y. Massoud, S. Majors, T. Bustami, and J. White, “Layout techniques for minimizing on-chip interconnect self-inductance,” Proceedings 1998 Design and Automation Conference (DAC), pp.566-71. W. B. Kuhn, and N. M. Ibrahim, “Analysis of Current Crowding Effects in Multiturn Spiral Inductors,” IEEE Transactions on Microwave Theory and Techniques, Vol. 49, No. 1, January 2001, pp. 31-38. Restle, P.J., Ruehli, A.E., Walker, S.G., and Papadopoulos, G. “Fullwave PEEC time-domain method for the modeling of on-chip interconnects,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.20, (no.7), July 2001, pp.877-86.
