May 16, 2007 ... Design of a frequency tripler is presented and its noise degradation, due to the
presence of additive noise of the multiplier, is measured and ...
Microwave/Millimeter-Wave Components
Low additive noise frequency tripler Design of a frequency tripler is presented and its noise degradation, due to the presence of additive noise of the multiplier, is measured and compared to theoretical limits. By Bogdan Sadowski
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any applications require a smaller frequency to be converted to a higher one by multiplication. But, frequency multiplication inherently results in phase noise degradation at least by an amount of theoretical limit as described by the equation:
∆LΦ[dB] = 20 log10 (N )
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(1)
— multiplication factor Hence, it is desirable to use multipliers with very low additive noise, and phase noise degradation that approaches theoretical limits. Often, odd-order multiplication is achieved by limiting the input signal symmetrically for both positive and negative half-waves—this in turn reduces the level of even–order products at the output of the multiplier. In order to minimize AM-PM conversion in such multipliers, the output signal should have its zero crossings perfectly aligned with zero crossings of the input signal[1]. In reference 2, Charles Wenzel had proposed using a current-limiting switch to fulfill such requirements and developed an original odd-order diode multiplier[2]. To explain the principle of operation, let’s consider first the basic configuration of an analog four-diode switch as shown in Figure 1. Symmetry of the circuit is marked by the dotted line, which also points to the virtual ground for the balanced Uctrl voltage. Input terminal (marked “IN” in Figure1) is driven by the input voltage source ug (t) of internal resistance Rg. Output terminal (“OUT” in Figure 1) is loaded with load resistance RL. Switch is in ON-state when dc control voltage Uctrl is applied with the polarity shown in Figure 1 across the control terminals. Diodes D1 and D4, as well as D2 and D3, are all forward biased in this case. At the instance of zero crossings of the input signal, i.e., ug (t) = 0 V, diode bridge is perfectly balanced (if all four diodes are identical) and there is no
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where: ∆LΦ[dB ] — phase noise degradation in dB
Odd-order multiplier
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Figure 1. Four-diode analog switch.
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Figure 2. Analog switch—equivalent circuit for control voltage.
current flowing in the load resistor RL. To estimate the current flowing in the diode D1 due to control voltage Uctrl, circuit is divided into two halves along another symmetry line (vertical) as shown in Figure 2. Due to the symmetry of the circuit, all current flowing in the diode D1 also flows in the diode D4. Thus, dc (bias) current flowing in diode D1 can be estimated as follows: U − (2 ⋅ U F ) I D1 = ctrl 2⋅ R (2) where: UF — diode forward voltage For simplicity, internal series resistance of
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each diode is considered small as compared to R, Rg and RL. For the case of u g (t ) ≠ 0V , the diode bridge becomes unbalanced and output current flows in the load resistor RL as a result. Signal source (of internal resistance Rg) driving the input (IN terminal in Figure 1) produces ac current iD1(t) flowing in the diode D1 in the opposite direction (during its positive half-wave of the cycle) as compared to the direction of the bias current ID1. To estimate the current flowing in the diode D1 due to signal source ug (t), circuit is divided into two halves along the symmetry
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2 ⋅ R ⋅ RL iD1 (t ) ⋅ + 2 ⋅ Rg R + (4 ⋅ RL )
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iD1 (t ) =
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u g (t ) 2 ⋅ R ⋅ RL + 2 ⋅ Rg R + (4 ⋅ RL )
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(7)
The total current flowing in the diode D1 in forward direction, iFD1(t), can be expressed by:
Figure 3. Analog switch—equivalent circuit for the input signal.
D1
) = u (t )
iFD1 (t ) = I D1 − iD1 (t )
D2
(8)
u g (t ) U ctrl − (2 ⋅ U F ) iFD1 (t ) = − 2⋅ R 2 ⋅ R ⋅ RL + 2 ⋅ R g R + (4 ⋅ RL )
(
IN
OUT
L
D4
D3
Figure 4. Basic configuration of an odd-order multiplier.
D1
D2
L1
IN
OUT
L2 D4
D3
Figure 5. Odd-order multiplier—circuit symmetry.
line as shown in Figure 3. Current flowing in the diode D1 is a sum of currents flowing in the resistor R/2 and in the branch consisting of diode D2 and resistor 2RL in series. For an ac current, the diode is modeled as a closed switch (internal resistance of the diode is again considered small as compared to R, Rg and RL). Current iD1(t) can be estimated as follows: u g (t ) − 2 ⋅ Rg ⋅ (iD1 (t ) ) iD1 (t ) = R ⋅ 2 ⋅ R L 2 R + (2 ⋅ RL ) 2
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where: ug (t) — voltage of the signal source Rg — internal resistance of the signal source u g (t ) − 2 ⋅ Rg ⋅ (iD1 (t ) ) iD1 (t ) = 2 ⋅ R ⋅ RL R + (4 ⋅ RL ) (4)
2 ⋅ R ⋅ RL iD1 (t ) ⋅ = u g (t ) − 2 ⋅ Rg ⋅ (iD1 (t ) ) R + (4 ⋅ RL )
(
(3)
)
(5)
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)
(9) Similarly, currents flowing in other diodes can be analyzed. The condition of being forward biased for diode D1 will cease (and the diode will turn off) when the instant value of current due to signal source becomes equal (and opposite in direction) to the value of dc “bias” current forced by the control voltage (Uctrl)—in other words, when the input signal reaches the threshold value. When the input voltage ug (t) is higher then the threshold value Ug threshold, output current flowing in the load RL reaches its limit and symmetrical clipping of the output current waveform occurs. Lower values of the control voltage (Uctrl) correspond to lower levels of the input threshold voltage Ug threshold. Thus, to cause limiting of the output current at very low input thresholds, condition Uctrl close to 2UF must be reinforced. For that condition, clipping of the output current occurs at instances close to the zero crossing instances of the input signal, which in turn, assures that AM-PM conversion is kept minimal. Going forward the same way, you may want to dc-short control voltage terminals. Dc-shorting of the control voltage terminals, with an inductor, aid operation of the analog switch as an odd-order multiplier with low additive noise due to the optimal alignment of the input and output zero crossings. Inductance value should be chosen to be sufficiently large in order to present a high impedance at the input signal frequency. Figure 4 shows basic configuration of such an odd-order multiplier. To better understand the principle of operation, the inductor is split into two halves, L1 = L2, as shown in Figure 5, along the symmetry line (dotted line in Figure 5) and the virtual ground point, between two halves of the inductor, is connected to the signal ground.
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During negative half-wave of the input signal UIN, diode D1 is polarized forward, thus allowing current iL1 to flow in the inductor L1. Energy stored in the magnetic field of inductor L1 (during negative half-wave of the input signal cycle) causes that the current of the inductor does not cease immediately after the polarity of the input signal has changed (when positive half-wave of the cycle starts) but continues to flow opposing the change (Lenz’s law) until the input voltage UIN has finally reached the level high enough to backward polarize the diode D1 and shut-off the current (Figure 6). As a result, dc level of the voltage UL1 is shifted with respect to zero voltage reference level. Value of the inductance L1 has to be relatively large to provide sufficient energy storage capacity. At microwave frequencies self-resonance will have to be taken into consideration, thus imposing an upper limit on the inductance value. Similarly, the circuit consisting of D4 and L2 could be analyzed. Figure 7 depicts waveforms produced by two rectifier/shifting circuits. Remaining diodes of the quad (diodes D2 and D3) perform the commutation of those two waveforms to the output (OUT terminal in Figure 7) to produce a square-wave (rich in odd-order harmonics).
D1 i L1 UIN
L1
UL1
Figure 6. Rectifier/shifting circuit—building block of odd-order multiplier.
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Inexpensive practical implementation
Inexpensive 3 GHz to 9 GHz frequency tripler was built to verify the noise performance. Two pairs of series-connected diodes from M/A-COM (MA4E2054B-287T and MA4E2054D-287T) were used. Phase noise plot of the tripler’s output signal at 9 GHz as compared to phase noise plot of the input signal at 3 GHz is shown in Figure 8. The noise degradation (due to the presence of additive noise of the multiplier) is significant only for offsets smaller then approximately 2 kHz. RFD
Figure 7. Odd-order multiplier—waveforms.
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Input Phase Noise Theoretical Limit Output Phase Noise
-40
(dBc / Hz)
-50
References
1. Richard A. Baugh, “Low Noise Frequency Multiplication,” Proc. 26th Annual Symposium, Frequency Control, Atlantic City, 1972. 2. Charles Wenzel, “New Topology Multiplier Generates Odd Harmonics,” RF Design Awards, RF Design magazine.
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ABOUT THE AUTHOR
-100 -110 -120 100
Offset (Hz)
10k
Figure 8.Input vs. output phase noise of 3 GHz to 9 GHz frequency tripler.
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100k
Bogdan Sadowski is a senior RF engineer with Harris Stratex Networks (formerly Microwave Communications Division of Harris Corp.) in Research Triangle Park, NC. His interests include frequency synthesis and non-linear circuits. He can be reached at
[email protected].
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