Low-IF Receiver Planning for The DECT System Vojkan Vidojkovic, Johan van der Tang and Arthur van Roermund Eindhoven University of Technology (TU/e) Department of Electrical Engineering, Mixed-signal Microelectronics (MsM) Group, EH 5.28 P.O. Box 513, 5600 MB Eindhoven, The Netherlands phone: +31 40 247 3393, fax: +31 40 245 5674 email:
[email protected] Abstract—In this paper, low-IF receiver planning for Digital European Cordless Telephone (DECT) systems operating around 1.9 GHz is described. A low-IF receiver architecture is chosen, since it allows a high degree of integration. Unlike zero-IF receivers, this architecture does not have a DCoffset or self-reception problem. The main features of the DECT system are presented, including the translation from the DECT system specification to RF circuit specification. Analytical expressions are presented for the noise figure (F) and the third order intercept point (IIP3) of a multi-stage two-path system, which are verified by simulation. These calculations are important for the low-IF receiver planning, since it has an in-phase and a quadrature branch. In order to incorporate the A/D-converter in the receiver planning calculations, a formula is derived which translates the Integral Nonlinearity (INL) of an A/D-converter to the IIP3 definition. In addition, the optimum IF frequency and selectivity distribution is considered, taking the A/D-converter requirements into account. A detailed description of receiver planning is given applied to the DECT system but the approach is suitable for other standards as well. Keywords— Receiver planing, DECT, Low-IF architecture, Noise figure (F), Third order intercept point (IIP3), A/D-converter.
I. I NTRODUCTION The wireless market is changing very rapidly. Pushed by the customer requirements, the system specifications are getting higher and higher. Driven by market requirements to reduce cost, CMOS technologies migrate towards deep sub-micron processes. It is important to see the influence of this technology trend for the receiver design. High level issues like choice of the architecture, choice of the intermediate frequency (IF), selectivity distribution, number of bits and sampling frequency of A/D converter directly influence the receiver performance and have great impact on receiver implementation. The receiver planning flow, proposed in this paper, is represented in the Fig. 1. Such top down design methodology is a structured approach to high performance receiver design, which can satisfy the future system requirements.
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Start System requirements (DECT) RF system specifications Architecture selection IF selection
Sub−system requirements and Receiver optimization
Optimized receiver planing
Fig. 1. Receiver planing flow
The structure of this paper is as follows. First four steps in the receiver planing flow are described in the sections II to V. In this case, sub-system specifications correspond to the specifications for the polyphase filter and A/D converter. They are calculated in section VI. In section VII, the analytical expressions for F and IIP3 of a multi-stage two path system are presented. The conclusion is given in section VIII. II. T HE DECT
SYSTEM
The DECT standard was originally developed in Europe but now has been adopted worldwide. Its main function is to provide wireless access to the fixed telephone network. DECT is based on FDMA (Frequency Division Multiple Access) and TDMA (Time Division Multiple Access) techniques. The frequency band 1880 1900 MHz, assigned to DECT, is divided into ten RF channels. The center frequency of each channel can be calculated using (1). Fc F0 c 1 728 MHz (1)
where F0 is the upper boundary of the DECT band ( F0 1897 344 MHz) and c is the channel number (c 0 1 9). A Gaussian Minimum Shift Keying (GMSK) modulation scheme is applied in DECT. It has constant envelope, continuous phase and high spectral efficiency. III. T RANSLATION
OF THE SYSTEM SPECIFICATIONS
The noise figure (F) of a receiver [1] can be calculated using (2). F
174 dBm Hz Psens
SNRout
10logB
(2)
The receiver sensitivity (Psens ) is defined as the lowest power level at the receiver input at which Bit Error Rate (BER) at the output of the demodulator is less than 10 3 . The DECT standard specifies (increased with production margin) [5]: Psens 95 dBm. SNRout is the minimal required signal to noise ratio at the input of the demodulator in order to obtain BER 10 3 . In DECT, SNRout 14 dB. B is the effective noise bandwidth. In DECT B 1 152 MHz. After the substitution, the value for calculated noise figure is F 4 38 dB. The noise floor of the receiver is defined as the total integrated noise power at the receiver input: Pnoise f loor Pnoise f loor
Psens
SNRout
109 dBm
(3) (4)
In order to calculate the signal level which corresponds to IIP3 , the inter-modulation (IM) performance from the DECT specifications [5] and (5) will be used. IIP3
Pi
Pi
Pw α 2
(5)
Pi is the power of the interferer, Pw is the power of the wanted signal and α is carrier to interferer level. IM performance is specified in the following way: if the wanted signal with power Pw 80 dBm is accompanied with two interferers, each of them having power Pi 42 dBm, then due to the nonlinearities, the third order IM products fall in the band of wanted signal. With these IM products present, BER at the output of the demodulator must be less than 10 3 . In [5] it was specified that receiver must cope with the interferer signal in the same channel with the wanted signal, which is 8 dB lower than the wanted signal. In order to make the influence of the third order IM products negligible, α is chosen to be 15 dB. This choice for α was checked by simulations and the result was satisfactory (BER 10 3 ). Substitution of all the values in (5) gives IIP3 15 5 dBm.
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IV. A RCHITECTURE
SELECTION
The architecture selection will be done using the following criteria: sensitivity and robustness to the technology scaling, flexibility in terms of ease of reuse for other technology, power consumption and level of integration. Besides the defined criteria for selection, the functions that a receiver must perform can also play important role in the architecture selection. The receiver must provide: selectivity, gain, image rejection and down-conversion. The followed approach is to consider what are the limitations for a certain function and how the limitations depend on the architecture. Among all the mentioned functions, the image rejection is the crucial for architecture selection. The most frequently used architectures will be considered: superheterodyne, zero-IF, and low-IF. It will be also assumed that the second order Butter-worth filter, with bandwidth of 150 MHz, is applied as RF filter (out-of-band rejection filter). The major problem in superheterodyne architecture is the integration of the high frequency image reject filter (HFIRF). The requirements for such filter are very high. The quality factor (Q) of such filter can be expressed as Q fc B where fc is the filter center frequency ( fc 1900 MHz) and B is the filter bandwidth. For 50 MHz B 200 MHz, Q is between 38 and 9 5. The required image rejection depends on the IF frequency ( fIF ). The image signal is situated at the frequency: fi
fw
2 fIF
(6)
where fw is the center frequency of the wanted signal. Concerning the interference performance and radio receiver blocking requirements [5], it follows that the level of the image signal will depend on fIF . It will be assumed that the image signal must be 20 dB below the wanted signal in order to avoid corruption. For this amount of image suppression, the required filter order (n) as a function of the IF ( fIF ) is depicted in the Fig. 2(a) and Fig. 2(b). It was assumed that the filter bandwidth is B 100 MHz. As it can be seen the requirements for HFIRF are very high and such filter can not be integrated. Discrete solutions are very expensive [7]. Even, if the fIF and B are so high that the integration of HFIRF becomes feasible, with the migration to the new technologies the capacitances of MOS transistor [9] will be increased, making the integration more costly. The major problem in the zero-IF architecture are DCoffsets. They are result of self-mixing and oscillator pulling, which depends on capacitive and substrate coupling. As it was mentioned, with the technology scaling the capacitances will increase. This effect will con-
12.0
137.8
10.8
Filter order (n)
Filter order (n)
170.0
105.6
73.4
P [dBm] mirror signal
wanted signal filter transfer function
9.6
x 8.4
f [KHz] 7.2
41.2
fx 9.0
30
40
50
60
6.0
60
70
IF [MHz] (a)
80
90
100
IF [MHz] (b)
Fig. 2. The filter order as a function of intermediate frequency
tribute to the DC-offset problem and in the future zero-IF architecture can not enable design of high performance receivers. The low-IF architecture is represented in the figure (3). There are two problems associated to the low-IF architecture: image rejection depends on matching and increased power consumption. For example due to the imperfection in the quadrature generator, the image rejection ratio (IRR) is limited to 20log 4 θ , where θ is the phase unbalance between I and Q signal [1]. With 1 phase unbalance, IRR of 47 dB can be achieved. It will be shown that this is enough for the DECT. Also, it was shown [9], that the matching will improve with newer CMOS technologies. The problem with power consumption can be solved with careful circuit design with special attention on power consumption. Advantages of the low-IF architecture are a high level of integration and no DC-offset problem. Based on this analysis, the low-IF architecture is chosen for DECT receiver as the most promising architecture.
VGA
A/D
Fig. 4. The spectrum after the down-conversion
adjacent channel represents the image signal which gives fIF 864 kHz (see (6)). The required image suppression is: IRR
Pw 20 37 dB
Pi
VI. R EQUIREMENTS
FOR THE POLYPHASE FILTER AND
A/D
LNA
DSP
(active or passive) VGA
I
x
n
log 10 10
Q
Tuning system
Fig. 3. Low - IF receiver with image rejection at IF
V. IF
SELECTION
The IF will be chosen in the way which relaxes the requirements for the polyphase filter and for the A/D converter. Taking into account the interference performance [5], interferer level is the lowest in the adjacent channel (Pi 56 dB). The power of the wanted signal is Pw 73 dB. So the IF will be selected in the way that
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1
2log Bfx lp
(8)
where x is required attenuation at frequency fx . Given the choice of IF ( fIF 864 kHz), and position of the image signal, it can be written:
fx x
A/D
CONVERTER
The center frequency of the polyphase filter ( fc ) is equal to the IF ( fc 864 kHz). The spectrum after downconversion is represented in the Fig. 4. The design question is to determine the bandwidth (B) and the order (n) of the polyphase filter. In order to do that, it will be assumed that the transfer function of the polyphase filter is obtained by frequency translation of a low-pass Butter-worth filter with the same order and bandwidth Bl p B 2. Expression (8) will be used for filter order calculation.
polyphase filter
RFF
(7)
2 fIF 37 dB
(9) (10)
From (8) it can be seen that the filter order is proportional to 1 Bl p . It means that it is beneficial to choose narrow bandwidth, but the limitation will be possible signal corruption of the wanted signal due to the filter transfer function. Considering the spectrum of the GMSK signal [6], almost all signal power is in the bandwidth from fcar to fcar 864 kHz, where fcar is the carrier frequency. Hence the bandwidth of the low-pass filter can be Bl p 864 kHz. From (8), it follows that in this case, the filter order is n 6 and the bandwidth of the polyphase filter is B 1 728 MHz. For the A/D converter, it is necessary to determine the (oversampling) frequency ( fsam ), number of bits (nb ),
14
Gain
13
−73 dBm
SNR out [dB]
12
Vmax − full scale of A/D converter
Pwanted signal Vsi
10
8
Gain
−95 dBm
6
4
−109 dBm 0
10
20
30
14 dB
Psensitivity
Gain
20 dB
Vqn − quantization noise
Pnoise floor
SNR ad [dB] (a)
Vqn
DR 6 02 nb
fsam fsig
1 25 10log
(11)
where DR is dynamic range and fsig is the signal bandwidth. In DECT, fsig 1 7 MHz. Dynamic range is the difference between the highest and lowest signal level that should be processed by A/D converter. Considering the selectivity introduced by the Butter-worth polyphase filter (n 6) and interferer levels given by the interference performance and radio receiver blocking requirements [5], all the interferers will be attenuated far below the level of wanted signal. So the highest signal level at the input of A/D converter can be expressed as: G 10 Pw
10
50 1 mW
(12)
where Pw 73 dBm is the power of the wanted signal at the receiver input and G is the receiver gain from antenna to the input of A/D converter (see Fig. 5(b)). The lowest signal level will be defined by the quantization noise. Due to quantization noise the signal to noise ratio at the output of A/D converter (SNRout ) will be lower than the signal to noise ratio at the input of A/D converter (SNRin). The following expression can be used to calculate SNRout : SNRout
G
10 Psens
50 1 mW
20 10
1 1 SNRad
(13)
1 SNRin
(14) (15)
bandwidth and filter order of the anti-alias filter (if necessary). The number of bits and sampling frequency [4] will be calculated using (11).
(b)
Fig. 5. (a) SNR corruption due the quantization noise (b) Mapping the signal levels into A/D converter range assuming the applied selectivity
Vmax
It can be seen that for SNRad 20 dB, SNRout is 13 dB, which will give BER 10 3 . This is the explanation why SNR 14 dB was used for calculation of the noise figure . Considering that the signal at the sensitivity level is the weakest signal that will be processed by the receiver 95 dBm), the level of the quantization noise (Psens must be 20 dB lower. So the level of the quantization noise will be:
Finally, dynamic range is: DR
20log
DR
42 dB
Vmax Vqn
(16) (17)
It is beneficial to choose a high sampling frequency because this relaxes the requirements for the anti-aliasing filter. In this case 6 times oversampled A/D converter will be used. The sampling frequency ( fsam ) is fsam 6 3 4 20 4 MHz. Using (11) it is possible to calculate the required number of bits, nb 6. Due to the sampling [3], the whole spectrum will appear again at the frequencies k fsam , k 1 2 . The signal around the frequency fsc fsam 864 kHz, fsc 19 536 MHz, and with the bandwidth of 1 7 MHz, will fall in the band of wanted signal and corrupt it. To avoid the corruption due to aliasing, this signal must be suppressed. Considering the frequency of the this signal, the level can be 23 dBm [5]. Taking into account the attenuation of the sixth order Butter-worth polyphase filter, the unwanted signal is suppressed below the noise floor and an anti-aliasing filter is not necessary. VII. N OISE
FIGURE AND
IIP3
CALCULATIONS
The total noise produced by a two port can be represented by equivalent input noise generators [2]. In the Fig. 6, Vn2 is equivalent voltage noise generator and In2 is equivalent current noise generator. In general equivalent input noise sources are correlated because they depend on the same noise sources in the circuit. In this case the noise factor (NF) can be calculated as: NF
1
Vn In Rs VR2
2
(18)
S
2 . V is the where SNRad is defined as: SNRad Vsi2 Vqn si voltage of the signal at the input of A/D converter. In Fig. 5(a), SNRout is represented as the function of SNRad for SNRin 14 dB.
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where VR2S 4kT Rs . The RF filter (RFF) is the first stage in the receiver after the antenna (Fig. 3). This is normally passive circuit and it is important to calculate the noise factor for such kind of
2
Vn
Rs
2
Vin
In
extension of the Friis formula [1], but for the two path architecture. In the calculations, it was assumed that the corresponding building blocks in both paths are identical.
Rout
V1
Rin
AV1
L NF2
A p2
Fig. 6. Equivalent input noise sources for a two port
NFeq 1 A p2 Rin2 1 2 2 Rout1 A L 2 Rin2 Rout1 Rout2
NF
(19) (20) (21)
Rs
RFF
MIXER
FILTER
VGA
A/D
MIXER
FILTER
VGA
A/D
LNA X
Vin
NFeq is the noise factor at point X in the Fig. 7 and can be calculated as:
NF3v
A23
NFeq
NF4
NF5
1
R A p3 Rout2 out3
14 dB
Fig. 7. Scheme for noise figure calculation with two A/D converters
A p3
circuit. In [1] it was shown that for passive circuit, NF L where L is the power loss. Generally, in the low-IF architecture (Fig. 3), there are two possibilities: two A/D converters can be used and digitize the signals from both paths (Fig. 7) or the signals from both paths can be added (Fig. 8) . The advantage of the second possibility is that only one A/D is needed, but further image suppression, if necessary, can not be done in digital domain. This can be disadvantage because in the case that the receiver should be redesigned for other standards which has the similar characteristics but requires higher image suppression, then the same architecture can not be used. Also, one of two possibilities will give lower noise figure which depends on the correlation between Vn2 and In2 . In order to keep the consideration general, the expressions for noise factor calculations will be given for both possibilities. If the block i in the low-IF architecture is described by its input impedance (Rini ), output impedance (Routi ), gain (Ai ), input noise voltage source (Vni2 ), input noise current source (Ini2 ) and noise factor (NFi ) which is calculated with respect to the output impedance of the previous stage (i 1), then for the scheme represented in the Fig. 7, the total noise factor can be calculated using the equations from (19) to (29), which represent the
A p4
Rs
RFF
MIXER
FILTER
VGA
MIXER
FILTER
VGA
A/D
LNA X
14 dB
Fig. 8. Scheme for noise figure calculation with one A/D converter
704
(22)
Rin3 2 2 Rout2 Rin3 2 Rin4 2 A p3 A24 Rout3 Rin4
(23) (24) (25)
NF3v is the noise factor for mixer which includes the influence of the noise from the mixer in the second path (Fig. 7).
1 M1 M2
NF3v M1
Vn3 In3 R out2 out2
Rin3 2 Rin3
VR2 out2
M2 VR2
(26)
R
Vn3 In3 Rin3
2
VR2 out2
Rout2 Rin3
1
Rout2 Rin3
2
2
(27)
(28)
4kT Rout2
out2
(29)
For the scheme depicted in the Fig. 8, the noise calculations are the same except for the equations: (22) and (26). These equations have the following forms:
NF3v
1
NFeq
NF3v
NF4
NF5
1
R 2A p3 Rout2 out3
1
R 2A p4 Rout2 out4
1 Vn3 In3 Rout2 2 VR2
(30)
2
(31)
out2
IIP3 calculation does not depend on the choice of the schemes (Fig. 7 and Fig. 8). The general formula for single path multi-stage architecture [1] can be used: 1 AIP32
Vin
1
R A p4 Rout2 out4
1 AIP32 1
∏nn i1 1 A2n ∑ AIP2 i 2 3 i
i 6
(32)
where An is the voltage gain of each stage and AIP3 i is the third order intercept point for each stage.
Vout 3
a1Vmax + a3Vmax INL
Vmax Vin Ideal input−output characteristic
Fig. 9. Nonlinearity of A/D converter
It is important to notice that AIP36 describes the nonlinearities of A/D converter. Assuming a differential A/D architecture and an input stage which determines the nonlinearity, the transfer characteristic of A/D converter can be written as [8]: Vout t
a1Vin t a3Vin3 t
(33)
Low-IF architecture, also, has very good flexibility for different standards and different systems, because high frequency image reject filter is avoided and the required changes can be done more successfully on the lower frequencies. For a chosen IF, the optimal solution for selectivity distribution is presented and A/D converter specifications are calculated. The possible problems associated to the low-IF architecture could be chip area and power consumption. Chip area is not so big issue considering the fact that the analog part of mixed-signal chip is small in comparison with the digital part and problem with power consumption can be solved with careful circuit design. With the derived formulas for noise and linearity, the specifications of the building blocks of the receiver can be calculated and optimized. ACKNOWLEDGMENTS
AIP36 is defined as a function of the integral nonlinearity in the following way:
The authors would like to thank A. Leeuwenburgh and P. Kamp from National Semiconductors and J.A. Hegt from Eindhoven University of Technology for many suggestions and technical discussions.
2 Vmax 3
R EFERENCES
INL 2a1Vmax
AIP3
INLnor
1 INLnor 3
(34) (35)
where INL represents maximal deviation from the ideal input-output characteristic (Fig. 9). VIII. C ONCLUSION Most important aspects of high level receiver planing are described in this article. Presented considerations are general and can be applied for other systems. The DECT system was used as an example . It was shown that lowIF architecture is the most promising one considering the selection criteria: sensitivity and robustness to the technology scaling, flexibility in terms of ease of reuse for other technology and level of integration.
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[1] B. Razavi, RF Microelectronics, Prentice Hall, 1998. [2] P.R. Gray, et al. , Analysis and design of analog integrated circuits, John Wiley & Sons, 2001. [3] K.S. Shanmugam, Digital and analog communication systems, John Wiley & Sons, 1985. [4] R. van de Plassche, Integrated analog to digital and digital to analog converters, Kluwer Academic Publishers, 1994. [5] ETSI DECT Standard, TBR6-Technical Basis for Regulation , 1999. [6] K. Murota, K. Hirade, GMSK Modulation for Digital Mobile Radio Telephony, IEEE Transactions on communications, vol. 29, no. 7, pp. 1044-1050, 1981. [7] J. Crols, M.S.J. Steyaert, Low-IF Topologies for High performance Analog Front Ends of Fully Integrated Receivers, IEEE Transactions on circuit and systems-II: analog and digital signal processing, vol. 45, no. 3, pp. 269-282, 1998. [8] B. Razavi, CMOS RF Receiver Design for Wireless LAN Applications, Radio and Wireless Conference (RAWCON), 1999, pp. 275 - 280, 1999 IEEE. [9] K. Bult, Scalability of wire-line analog front-ends, AACD, 2001.
