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University of Sharjah College of Engineering Department of Electrical and Computer Engineering
Senior Design Project Report Phase 2 – Senior Design Project 2
Low noise low power instrumentation amplifier for biomedical application Project group: Mohamed Balla El amien
U00031901
Abdulrahman Abdullah Zaatar
U00027317
Mohamed Ibrahim ElTinai
U00017995
Project Examination Committee: Supervisor
Dr. Soliman Mahmoud
Examiner
Dr. Anwar Hasan Jarndal
Chair
Dr. Amr Mohamed Elnadi Spring 2014/2015
1
ملخص الرسالة
إن اإلشارات الطبٌة الحٌوٌة ضرورٌة لألطباء لتشخٌص الحالة الطبٌة للمرضى .عادة ٌتم استخدام أقطاب كهربائٌة للحصول على هذه اإلشارات الطبٌة من جسم اإلنسان ومن ثم ٌتم استخدام مضخمات من أجل معالجتها رقمٌا .ومع ذلك ،فإن التحدي الرئٌسً فً هذه العملٌة هو أن المرٌض عادة ما ٌكون متصل باألجهزة الكهربائٌة التً تعمل بطاقة التٌار المستمر ،والتً ٌمكن أن تقلل من حرٌة التنقل للمرٌض ،مما ٌخلق نوع من عدم الراحة .وعالوة على ذلك ،هذا ٌحد من وقت مراقبة المرضى والذي ٌؤثر بالتالً على تشخٌص المرض .ولذلك ،هناك زٌادة مستمرة فً الطلب على األجهزة صغٌرة الحجم و التً تعمل بطاقة منخفضة (طاقة البطارٌة) و بالتالً تعطً للمرٌض حرٌة التنقل مع الحفاظ على عملٌة المراقبة الطبٌة المستمرة .إن هذه اإلشارات الطبٌة الحٌوٌة عادة ما تكون ضعٌفة جدا و مصحوبة بإشارات غٌر مرغوب فٌها و التً قد تؤثر على القراءة الصحٌحة لحالة المرٌض .ولذلك، فإن الحاجة إلى مضخمات ذات جودة عالٌة جدا هو أمر مهم في عملية التشخيص. إن اإلشارة الطبٌة الحٌوٌة المستهدفة في هذا المشروع هي الرسم الكهربائً للدماغ ) .(EEGو يهتم المشروع أساسا بتصمٌم مكبرعالٌة الجودة باستخدام تكنولوجٌا(.)CMOSوٌتضمن التقرٌر طبولوجٌا مختلفة لتنفٌذ هذه المضخمات وتقنٌات مفٌدة فً التصمٌم.
I
Abstract
Biomedical signals are essential to physicians for diagnosing medical conditions in patients. Usually, electrodes are used to acquire the biomedical signals from human body and then the amplifiers are used to amplify these signals in order to be suitable for analog-to-digital conversion. However, the main challenge in this process is the patient is usually connected to the mains-powered instrument, which can reduce the patient mobility and it creates a kind of discomfort. Furthermore, this limits the monitoring time of the patients and consequently affecting the diagnosis of the illness. Therefore, there is an increasing demand for low-power and small-size acquisition system. The biomedical signals are generally very weak and they suffer from the high common mode voltages. Thus, the need of very high quality instrumentation amplifier is important to insure better diagnosis. In this project, the targeted biomedical signal is the Electroencephalogram (EEG). The project mainly concerns about designing an instrumentation amplifier (IA) for EEG signal by using CMOS technology. The report contains different topologies for implementing the instrumentation amplifier and helpful techniques in designing.
II
Table of Contents List of figures ...................................................................................................................................................... V List of tables...................................................................................................................................................... VII Introduction .......................................................................................................................................................... 1 1.1 Biomedical signal background ................................................................................................................... 1 1.2 Electroencephalogram................................................................................................................................ 2 1.4 Design background .................................................................................................................................... 2 1.5 Objective .................................................................................................................................................... 3 1.6 Thesis organization .................................................................................................................................... 3 EEG basics ........................................................................................................................................................... 6 2.1 EEG Definition and Basics ........................................................................................................................ 6 2.2 EEG Characteristics ................................................................................................................................... 9 2.3 Interference Theory .................................................................................................................................. 10 CMOS Operational Amplifier (Op Amp) design procedure .............................................................................. 12 3.1 Introduction .............................................................................................................................................. 12 3.2 The basic two stage CMOS op-amp design procedures........................................................................... 15 3.2.1 Gain and bandwidth .......................................................................................................................... 17 3.2.2 Slew rate............................................................................................................................................ 19 3.2.3 Phase margin ..................................................................................................................................... 19 3.2.4 Output swing ..................................................................................................................................... 20 3.2.5 Common-mode range ........................................................................................................................ 20 3.2.6 Offset voltage minimization.............................................................................................................. 21 3.2.7 Power dissipation .............................................................................................................................. 21 3.2.8 Input referred thermal noise spectral density .................................................................................... 22 3.2.9 Design procedure .............................................................................................................................. 23 3.3 Calculation results of the two stage miller op-amp .................................................................................. 24 3.4 simulation results of the two stage op-amp .............................................................................................. 27 CMOS transconductance amplifiers (OTA): Basic circuits and Definitions ..................................................... 30 4.1 introduction .............................................................................................................................................. 30 4.2 CMOS Realizations of different types of transconductors ...................................................................... 30 4.2.1 Single Input Single Output Transconuctor Using CMOS Composite Transistor ................................. 32 4.2.2 Differential Input-Single Output Transconuctor ................................................................................... 36 4.2.4 Differential Input- Differential Output Transconuctor ......................................................................... 38 Fully differential programmable CMOS OTA................................................................................................... 40 5.1 introduction .............................................................................................................................................. 40 III
5.2 Digitally Programmable OTA Circuit Principle ...................................................................................... 41 5.3 The AB class buffer simulation results .................................................................................................... 45 5.4 Digital Programmable OTA ..................................................................................................................... 47 5.5 Common mode feedback circuit (CMFB) ............................................................................................... 48 5.6 Overall OTA simulation results ............................................................................................................... 51 Current Feedback Instrumentation Amplifier .................................................................................................... 56 6.1 Introduction .............................................................................................................................................. 56 6.2 The system elements ................................................................................................................................ 59 6.3 simulation results of the NMOS transistor as a resistor ........................................................................... 62 6.4 The instrumentation amplifier simulation results .................................................................................... 64 Instrumentation amplifier Layout ...................................................................................................................... 69 7.1 Introduction .............................................................................................................................................. 69 7.2 Layout Process ......................................................................................................................................... 70 7.3 MOS transistor, resistor and capacitor layout .......................................................................................... 71 7.4 Instrumentation amplifier layout .............................................................................................................. 72 Conclusion ......................................................................................................................................................... 76 Reference ........................................................................................................................................................... 77 Appendix A ........................................................................................................................................................ 78 Appendix B ........................................................................................................................................................ 79
IV
List of figures Figure 1.1 Frequency and amplitude ranges characteristics of the biomedical signals, EEG, ECG, and
4
EMG, and the correlating offset and noise signals. Figure 1.2 The typical EEG acquisition system block diagram.
5
Figure 2.1 Conventional 10–20 EEG electrode positions for the placement of 21 electrodes.
8
Figure 2.2 The typical normal brain rhythms with their amplitude levels.
11
Figure 3.1 The op-amp symbol.
13
Figure 3.2 The basic block diagram of the op-amp stages with the secondary circuits.
14
Figure 3.3 Two stage miller op-amp.
16
Figure 3.4 Small signal equivalent circuit of CMOS op-amp.
18
Figure 3.5 Two stage miller op-amp with robust biasing circuit.
26
Figure 3.6 The magnitude response of the proposed op-amp.
28
Figure 3.7 The frequency response of the proposed op-amp.
28
Figure 3.8 The input referred noise power spectral density of the proposed op-amp.
29
Figure 3.9 The input and the output of the proposed op-amp in buffer configuration.
29
Figure 4.1 CMOS Composite transistors.
33
Figure 4.2 SISO using CMOS composite transistor.
35
Figure 4.3 Differential input-Single output transconductor.
37
Figure 4.4 Differential input- differential output transconductor.
39
Figure 5.1 The concept of the digitally programmable OTA.
42
Figure 5.2 The class AB buffer circuit.
43
Figure 5.3 shows the input and the output of the buffer.
46
Figure 5.4 shows the frequency response of the buffer.
46
Figure 5.5 The digitally programmable OTA circuit based on the AB class buffer.
49
Figure 5.6 The overall digitally programmable OTA with CMFB circuit.
50
Figure 5.7 The derivative of the differential output current of the proposed OTA for different 4-bit code words.
53
V
Figure 5.8 The differential output current of the proposed OTA for different 4-bit code words.
53
Figure 5.9 The magnitude response of the output differential current of the proposed OTA for different 4 bit code words.
54
Figure 5.10 The IM3 test for the OTA for the bet word (0001).
54
Figure 6.1 Current feedback instrumentation amplifier (CFIA).
57
Figure 6.2 NMOS transistor used as a capacitor.
59
Figure 6.3 NMOS transistor used as a resistor
59
Figure 6.4 The instrumentation amplifier with active elements.
60
Figure 6.5 The resistance values of the NMOS vary from 100KΏ to 10MΏ based on aspect ratio in table 6.1.
62
Figure 6.6 The possible gain values for different resistance ratio (2,3,4,5,6,7,8,9,10 and 50).
64
Figure 6.7 The frequency response of the instrumentation amplifier.
64
Figure 6.8 The input referred noise of the instrumentation amplifier.
65
Figure 6.9 The third-order intermodulation test (IM3) with two tones at (60 and 80 Hz).
65
Figure 6.10 (a) shows the time representation of corrupted EEG signal with additive noise and (b) shows the output signal of the proposed instrumentation amplifier while the gain sitting of the amplifier is 54dB.
66
Figure 6.11 The common mode gain of the instrumentation amplifier.
66
Figure 6.12 The gain magnitude of the instrumentation amplifier for the different four bits word combination for the input OTA.
67
Figure 7.1 NMOS transistor layout in L-edit software.
71
Figure 7.2 PMOS transistor layout in L-edit software.
72
Figure 7.3 Resistor layout in L-edit software.
73
Figure 7.4 Capacitor layout in L-edit software.
73
Figure 7.5 The instrumentation amplifier layout.
74
VI
List of tables Table 3.1 Op-amp design steps.
23
Table 3.2 process parameters of 0.25µ CMOS technology.
24
Table 3.3 Op-amp specifications.
25
Table 3.4 Design parameters.
25
Table 3.5 Design parameters.
27
Table 3.6 Op-amp results.
27
Table 4.1 Different types of OTAs.
31
Table 5.1 The aspect ratio of the AB class buffer.
45
Table 5.2 The transistors aspect ratio, components and biasing voltages values of the OTA in
52
figure 5.6. Table 6.1 The aspect ratios of the NMOS transistor and there corresponding resistance values.
61
Table 6.2 Performance parameters of the proposed instrumentation amplifier.
63
VII
CHAPTER 1
Introduction
1.1 Biomedical signal background Biomedical signals are the electrical activity of the creature’s cells that produced due to the electrochemical interactions of certain type of cells that are elements of the nervous, glandular or muscular tissue. They are divided into two main classes, exogenous signals which are any signals applied from outside the human body and they are mainly used to measure internal structure and parameters and nowadays they are using some of them to solve some internal body disease, a good example of these signals is the x-ray signal. The second one is the endogenous signals which are the signals that arise from natural physiological processes inside the human body. These signals are very important to detect the human body state [1]. Biomedical signals are characterized by low bandwidth; low amplitude and they contain a lot of noise. Nowadays Biomedical signals have become very important for diagnosing medical conditions, human computer interaction and indifferent research areas.
1
1.2 Electroencephalogram There are different types of biomedical signals and each type has a specific range of amplitude and frequencies as shown in Figure 1.1. Electroencephalogram (EEG) is one of the important types in these signals. The EEG signals are characterized by low voltage amplitude from 0.5 to 100 µV, which is about 100 times lower than ECG signals. Also its frequency is low where the frequency range is from 0.5 to 100 Hz.
1.4 Design background In portable acquisition systems, maintaining the size and weight of the devices as small as possible without affecting the quality of reading is extremely important. In early portable acquisition systems a discrete components were used extensively due to their short design time and the components availability. However, they have large size and consume high power. In order to meet the low power criteria the current in the circuit must be reduced and the supply voltage should be low. Usually, in any acquisition system the picked signals are amplified and filtered firstly then converted to digital signals. Figure 1.2 illustrates the signal processing.
2
1.5 Objective The objective of this project is to design and implement an instrumentation amplifier for EEG signal based on the current feedback topology, which was chosen in senior design phase 1. That is sufficient to consider it the most convenient topology for implementing low-power and low-noise IAs.
1.6 Thesis organization The report illustrates the concept of current feedback instrumentation amplifier CFIA, which is used in biomedical systems. The report is divided into eight chapters. Chapter two studies the EEG basics. Chapter three describes the design procedures of the Op-amp, needed in CFIA topology, and its simulation results. Chapter four describes the design procedures the digitally programmable Differential OTA and its simulation results. Chapter five illustrates the concept of the fully differential programmable CMOS OTA. Chapter six shows CFIA implementation and simulation results. Chapter seven introduces the layouts of the proposed CFIA. Chapter eight is the conclusion of our work. All the simulation is done using SPICE software and 0.25µm technology model and the code is provided in the appendix. The layouts are designed by L-Edit software.
3
Signal Amplitude (uV)
50/ 60 Hz Coupling 104
103
ECG
102
EMG EEG
10 1 offset
0.1
1/ f Noise 1
10 102 Frequency (Hz)
103
Figure 1.1 Frequency and amplitude ranges characteristics of the biomedical signals, EEG, ECG, and EMG, and the correlating offset and noise signals.
4
Figure 1.2 The typical EEG acquisition system block diagram. 5
CHAPTER 2
EEG basics
2.1 EEG Definition and Basics Electroencephalogram (EEG) is a medical imaging technique that reads scalp electrical activity generated by brain structures. The electroencephalogram (EEG) is defined as electrical activity of an alternating type recorded from the scalp surface after being picked up by metal electrodes and conductive media [2]. There are two ways to measure EEG signal. The EEG signal measured directly from the cortical surface is called electrocortiogram while when using depth probes it is called electrogram. Mainly EEG measured from the cortical surface will be referred to in this report. The electrical activity of the brain is recorded with three types of electrodes: scalp, cortical and depth electrodes. Thus electroencephalographic reading is a completely non-invasive procedure that can be applied to patients, adults and children with no risk or limitation. Due to capability to reflect both the normal and abnormal electrical activity of the brain, EEG is found to be a very helpful tool in the field of neurology and clinical neurophysiology [2]. The EEG signals are low amplitude voltage ranged from 0.5 µV to 100 µV in amplitude, which is about 100 times lower than ECG signals. The EEG signal’s amplitude and frequency varies depending on the health, age and whether the person is awake or asleep.
6
The EEG has proven superior to clinical examination in newborns for the early detection and prognosis of brain dysfunction [3]. Two specific types of EEG recording are called monopolar and bipolar recordings. In order to under this point we take in consideration that EEG recordings reflect the difference in voltage between signals at two electrodes. In monopolar recordings the idea is to find a site that is not reflective of EEG activity per site to use as a reference site. Common sites used for this purpose are the ear (or ears), the mastoid, or even the nose. Other researchers have suggested that a useful reference to use is that of the average reference. This procedure basically takes a network of electrodes spaced across the scalp and mathematically averages those together. This mathematical average value is then used as the reference [4]. In bipolar recording, each electrode is located to record from an active site on the scalp. Thus, one could compare the difference in EEG activity between the right frontal areas with that of the left frontal area. This type of procedure has been used in clinical settings to identify unusual pathological waveforms [4]. The rhythmic variations of the EEG are continually present at the surface of the scalp from well before birth to death. In fact, the absence of the EEG for twenty-four hours has been used as an indicator of “brain death.” Additionally, EEG has been used to denote states of consciousness as found in sleep, epilepsy and brain pathology [4]. The International Federation of Societies for Electroencephalography and Clinical Neurophysiology has recommended the conventional electrode setting (also called 10–20) for 21 electrodes (excluding the earlobe electrodes), as shown in Figure 2.1 [5]. Detailed characteristics of the EEG signal are discussed in the next section.
7
10%
20%
FPZ FP1
FP2 FZ
20%
F7
T3
20%
T5
F3
C3
F4
CZ
C4
P4
P3
F2
T4
T6
PZ O1
O2 OZ
20% 10%
Figure 2.1 Conventional 10–20 EEG electrode positions for the placement of 21 electrodes.
8
2.2 EEG Characteristics In addition to the low amplitude of the EEG signals they are also low frequency signals where the frequency range is from 0.5 to 100 Hz. The intensities of the brain waves on the surface of the brain maybe as large as 10mV, whereas those recorded from the scalp have smaller amplitude of approximately 100µV. There are five major brain waves determined by their different frequency ranges. These frequency bands from low to high frequencies respectively are called alpha (α), theta (θ), beta (β), delta (δ), and gamma (γ). As illustrated in Figure 2.2 [5].
Delta waves lie within the range of 0.5 -4 Hz. These waves are basically affiliated with deep sleep and may be present in the waking state.
Theta waves lie within the range of 4–7.5 Hz. Theta waves appear as consciousness slips towards Drowsiness.
Alpha waves lie within the range of 8–13 Hz. Alpha waves have been thought to show both a relaxed awareness without any attention or concentration. The alpha wave is the most noticeable rhythm in the whole realm of brain activity and possibly covers a greater range than has been previously accepted.
Beta waves lie within the range of 14-26 Hz, A beta wave is the typical wake rhythm of the brain associated with active attention, active thinking and focus on the outside world and is found in normal adults. A high-level beta wave may be obtained when a human is in a panic state [5].
9
The frequencies above 30 Hz (mainly up to 45 Hz) correspond to the gamma range. (Sometimes called the fast beta wave).Observation of these rhythms can be used for confirmation of certain brain diseases, although the amplitudes of these rhythms are very low and their appearance is rare [5].
It is often difficult to understand and distinguish the brain rhythms from the scalp, even with trained eyes. Applications of advanced signal processing tool however, should enable analysis and separation of the desired waveforms from within the EEGs. Therefore, a definition of foreground and background EEG is very subjective and entirely depends on the abnormalities and applications [5].
2.3 Interference Theory Biomedical acquisition systems are often disturbed by the interference from the mains. Two main types of interference are called the electromagnetic interference and the electrostatic interference. In the case of the electromagnetic interference, the magnetic field created by the alternating mains current cuts the loop enclosed by the human body, the leads of the circuit, and the biomedical amplifier. This induces an electromotive force (EMF), which creates an AC potential at the input of the circuit. The electromagnetic interference can be reduced by decreasing the area of the loop by twisting the cables. Further reduction can be obtained be placing the acquisition system close to the electrodes, which in turn reduces the cable length [6].
10
Beta (β) 13–30 Hz
Alpha (α) 8–13 Hz
Theta (θ) 4–8 Hz
Delta (δ) 0.5–4 Hz
0
2
4 Time (s)
6
8
Figure 2.2 The typical normal brain rhythms with their amplitude levels.
11
CHAPTER 3
CMOS Operational Amplifier (Op Amp) design procedure
3.1 Introduction The operational amplifier (op amp) is considered one of the essential electronic components in designing of many analog circuits. Figure 3.1 shows the op-amp symbol where Rin is the input impedance which is ideally equal to infinite and Rout is the output impedance which is ideally equal to zero as well as the ideal op-amp is characterized with infinite gain. According to the previous ideal specifications the voltage V1 is equal to V2 and the currents i+ and i- are equal to zero. The design procedure of an Op amp needs to specify some parameters in order to achieve the required specification. Figure 3.2 shows the block diagram of the op-amp stages with the secondary circuits that might be used in designing an Op amp. The first stage of the Op amp is the differential stage which is based on two different inputs, which provide high input impedance. The intermediate stage is the gain stage. The third stage is the output stage, acts as a buffer which contains a single ended output with very small output impedance. The bias circuit forms suitable DC operating points for the transistors. The compensated circuit works as a feedback circuit to develop stability for the closed loop performance to the Op amp [7].
.
12
I+ V1
+
Vo IRin
V2
Ro -
Figure 3.1 The op-amp symbol.
13
Compensation Circuit: Using C or series C and R.
Differential stage: MOS Differential Amplifier with Active Load
High gain stage :CS (CE) Amplifier with active load
Output Buffer: Class A or class AB output stages
Bias Circuit
Figure 3.2 The basic block diagram of the op-amp stages with the secondary circuits.
14
3.2 The basic two stage CMOS op-amp design procedures
In designing an op-amp, there are some parameters that should be taken in consideration. They basically depend on the system where the op-amp is supposed to work in. Figure 3.3 shows the basic two stage miller op-amp. Equations of the op-amp characteristics can be found by assuming that the mobility reduction and the velocity saturation effect will be neglected for simplicity. for NMOS and
|
| for PMOS will be used. The following MOSFET, strong
inversion, square law equations will be used too:
( )
(3.1)
(3.2) √
( )
(3.3)
Strong inversion typically requires values of greater than approximately 200 to 250 mV for bulk MOSFET’s at room temperature [7].
15
VDD
M3
M4 M6
IB
-
M1
M2
+ Rc
Cc
Vo CL
M5
M8
M7
VSS
Figure 3.3 Two stage miller op-amp.
16
3.2.1 Gain and bandwidth
The bandwidth is a parameter related to the frequency characteristic of the op-amp and it is defined as the point -3dB from the DC gain. From the small signal equivalent circuit of CMOS op-amp shown in the figure 3.4 and under the low frequency conditions and
,
It can be shown that output voltage over the differential input voltage is given by:
(
)
(3.4)
Where Ao is the DC gain and it is given by:
(3.4.1) The op-amp dominant pole frequency and unity-gain bandwidth are given as: (3.5)
(3.6)
For ω ωp1, equation 3.4 can be approximated as: (3.7) (
)
Where Cgs6 is the capacitance of M6 , RA is the equivalent resistance at the output of the input stage, and RB is the resistance of the output stage.
17
Rc +
+
Vid -
Cc
gm1 Vid
RA
+
Cgs6 VA -
RB gm6 VA
CL Vo -
Figure 3.4 Small signal equivalent circuit of CMOS op-amp [7].
18
3.2.2 Slew rate
Slew rate it is the maximum rate of change in the output voltage due to step input voltage. It measures how fast the output voltage can follow the input voltage. There are two types of the slew rate internal and external. The value of the internal slew rate can be controlled by the value of the compensation capacitor Cc. The external slew rate can be determined from the load capacitor.
(3.8)
(3.9)
From equations 3.3, 3.6 and 3.8 with the assumption of
then:
(3.10)
3.2.3 Phase margin
The phase margin is defined as the difference between the signal phase at unity gain (0dB) and the 180ᵒ . It is usually used to measure the stability of the closed loop system.
19
3.2.4 Output swing
The output voltage of the op-amp is limited by the power supplies and the headroom voltage
of
the transistors of the gain stage. (3.11) (3.12) (3.13) (3.14) 3.2.5 Common-mode range
The common-mode range
is defined as the average of the power supply. In case of balance
power supply its value around zero. It can be calculated as follow:
(3.15) (3.16)
And from the figure 3.3 it can be easily conclude that: (3.17) (3.18)
20
3.2.6 Offset voltage minimization
When there is no input voltage an imbalanced current between Under this condition,
and
and
causes a systematic offset. . Since
( )
and
this will lead to
their current ratio will be
. Thus, ( ⁄ ) ( ⁄ )
( )
. By considering M5 and M7,
. Therefore, the imbalance of the current in the output stage
can be minimized to minimize the offset voltage using:
( ) ( )
( )
(3.19)
( )
3.2.7 Power dissipation
In designing the op-amp the considered power is the static power which can be calculated from the product of the currents and the voltage supplies as follow: (3.20) And from the equations 3.8, 3.9 ad 3.20 the power dissipation can be given in term of the slewrate and the compensation capacitor as: (3.21)
21
3.2.8 Input referred thermal noise spectral density
Input referred thermal noise spectral density of the two stage op-amp in the figure 3.3 can be shown to be:
[
][
(3.22)
]
From the equations 3.3, 3.8 and 3.15 can be obtained: (3.23)
From substituting 3.6,3.3 in equation 3.22
[
]
(3.24)
22
3.2.9 Design procedure
From the discussion in the previous subsections, the design procedure of two stage op-amp can be summarized in the following table: Table 3.1 Op-amp design steps [7]. steps
Equation [
1
]
2 √
3
4 5 ( )
6 ( ) 7
( )
8
( )
9
10
( )
( )
( ) ( )
( )
|
|
23
In figure 3.5 the robust bias circuit is added to the two stage op-amp in order to achieve more accurate biasing to the circuit. For ( )
( )
( )
( )
( )
and
( )
( )
It can be shown that: (3.25)
If ( )
is chosen to be 4( ) then,
( )
(3.26)
( )
3.3 Calculation results of the two stage miller op-amp For the process parameters shown in table 3.2 and op-amp specifications in table 3.3, design parameters of the op-amp in figure 3.5 is obtained from the steps in table 3.1 by using a Matlab code (see Appendix A) to calculate the parameters which are shown in table 3.4 Table 3.2 process parameters of 0.25µ CMOS technology. Process parameters
NMOS
PMOS
μ (cm2/V.s) Tox (m) Vt (V)
361.35 8*10-9 0.407
221.4 8*10-9 -0. 68317
24
Table 3.3 Op-amp specifications. Electrical parameters Supply voltage (V) Load capacitance (pF) DC gain (dB) Unity gain frequency (MHz) Phase margin (deg) Slewrate (V/µS) Input common range (V) Output swing (V)
Expected ±0.8 5 ≥75 1 65 +5/-5 +0.5/-0.5 +0. 6/-0. 6
Table 3.4 Design parameters. Procedure
Calculated
The proposed
Unit
Cc (W/L)1,2 (W/L)3,4 (W/L)5,8 (W/L)6 (W/L)7 (W/L)9 (W/L)10-14
0.5 0.6335 0.6545 0.4530 14.3979 4.9834 1.3089 1
0.5 1/1 1/1 1/1 30/2 6.25/1.25 2/1 1/1
pF µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm
25
VDD
M13
M11
M3
M4 M6
-
M12
M10
M1
M2
+ M9
Cc
Vo CL
M8
M14
M5 M7
RB
VSS
Figure 3.5 Two stage miller op-amp with robust biasing circuit [7].
26
3.4 simulation results of the two stage op-amp The op-amp circuit is simulated using PSPICE 0.25-μm technology under ±0.8 voltage supply. The aspect ratio of the transistor is showed in table 3.5. The op-amp is loaded with 5 pF. Figure 3.6 shows the magnitude response of the proposed op-amp which indicates a DC gain of 76.7 dB and unity gain frequency of 900 KHz. Figure 3.7 shows the frequency response of the op-amp which indicates a phase margin of 67o. The op-amp has input referred noise of 63.26 nV/√
which has
been measured at 1 KHz as showed in figure 3.8. In order to check the behavior of the output signal with respect to the input signal of the op-amp in buffer configuration, a transient response simulation is done with an input of pulse wave as shown in figure 3.9. It shows that the output is following the input. The overall power consumption of the op-amp is 4.52 µW. Table 3.5 Design parameters. Procedure Cc (W/L)1,2 (W/L)3,4 (W/L)5,8 (W/L)6 (W/L)7 (W/L)9 (W/L)10-14
The proposed 0.5 1/1 1/1 1/1 30/2 6.25/1.25 2/1 1/1
Unit pF µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm
Table 3.6 Op-amp results. Electrical parameters Supply voltage (V) Load capacitance (pF) DC gain (dB) Unity gain frequency (MHz) Phase margin (deg) Output swing (V) Power dissipation (µW)
Expected ±0.8 5 ≥75 1 65 +0. 6/-0. 6
Obtained ±0.8 5 76.741 0.9 67 +0. 6/-0. 7 4.5 27
100 100
(1.4823m, 76.741)
505 0
Gain (DB)
(900K, 0.000) 00
50- 5 0
-100 -100 11mHz .0mHz 10mHz 100mHz 1 1Hz .0Hz 10mHz 100mHz DB(V(7)/V(1,2))
10Hz 10Hz
100Hz 1.0KHz 10KHz 100KHz 1 . 0 M H z z 10MHz 10MHz 100MHz 1 .1GHz 0GHz 100KHz 100Hz 10KHz 1MH 100MHz 1KHz Frequency Frequency
00mHz o DB(V(7)/ V(2,1)) 0mHz
Figure 3.6 The magnitude response of the proposed op-amp. mHz Hz z
&Gain phase (degree)
Gain magnitude (DB)
200 200
00
(PM=67o) -200 -200
-400 -400 1.0mHz 10mHz 100mHz 1.0Hz 10mHz 1Hz 1mHz 100mHz DB(V(7)/V(2,1)) p( V(7)/V(2,1))
10Hz 10Hz
100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHz 100KHz 1GHz 100Hz 10KHz 1MH z 10MHz 100MHz 1KHz Frequency
o DB(V(7)/ V(2,1)) o P(V(7)/ V(2,1))
Frequency
Figure 3.7 The frequency response of the proposed op-amp.
28
Input referred noise spectral density (uV/√
)
1.0uV 1.00
0.75
0.5uV 0.5
0.25---
)1.000K, 63.265n)
00 V 1.0mHz 10mHz 100mHz 1.0Hz 10mHz 1Hz 1mHz 100mHz V(INOISE)
10Hz 10Hz
100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHz 100KHz 1GHz 100Hz 10KHz 1MH z 10MHz 100MHz 1KHz Frequency Frequency
o V(INOISE)
Figure 3.8 The input referred noise power spectral density of the proposed op-amp.
1.0V 1.0V
00V SEL>> -1.0V
(V)
Input & output voltage
1
-1 1.0V 1
V(2)
00V -1
-1.0V -1.0V 0s 0s
0 V(7) V(7)
10ms 10ms
10
o V(2) o V(7)
20ms 20ms
20
30ms 30ms
30
40ms 40ms
40
50ms 50ms
60ms 60ms 50 60 Time Time Time (ms)
70ms 70ms
70
80ms 80ms
80
90
90ms 90ms
100ms 100ms
100
Figure 3.9 The input and the output of the proposed op-amp in buffer configuration.
29
CHAPTER 4
CMOS transconductance amplifiers (OTA): Basic circuits and Definitions 4.1 introduction The operational transconductance amplifier (OTA) is a voltage controlled current source (VCCS). The first transconductance amplifier was implemented by bipolar transistors in 1969. Then in middle of 80’s CMOS transconductance amplifier was introduced and became important component in many electronic circuits. Table 4.1 shows the different types of OTAs and their general equations where Gm is the transconductance gain. Generally OTA should meet some specifications. For instance, high input impedance which achieves by connecting the inputs to the gate of MOS transistors, high output impedance and linearity which means the output current should be linearly proportional to the input voltage.
4.2 CMOS Realizations of different types of transconductors There are different realizations and designs to obtain the specifications that mentioned before. This section will discuss some of CMOS realizations of different types of transconductors. In general for high performance OTAs the designs are usually complex.
30
Table 4.1 Different types of OTAs.
Type
Symbol representation
General equation
Single Input-Single Output
Iout
Transconuctor
Gm Vi
Differential InputSingle
V1
Output
+
Iout
Gm
Transconuctor
V2
-
V1
+
Iout1
Gm
Iout2
Differential InputDifferential Output Transconuctor
V2
-
V1
+
Iout1
Gm
Iout2
Differential InputBalanced Output Transconuctor
V2
-
31
4.2.1 Single Input Single Output Transconuctor Using CMOS Composite Transistor For CMOS composite transistor in Figure 4.1 the transistors M1 and M2 in are assumed working in the saturation region and they have the same drain current (ID) due to series connection. This current can be given in term of NMOS parameters as: (4.1)
Also it can be given in term of PMOS parameters as: |
(4.2)
|
Therefore the equivalent VGSeq is given by:
√
√
(4.3)
Where VTeq and Keq are given by:
|
|
(4.4)
(4.5) √
√
32
ID
+
M1
+ VGS1
-
VSG2
+
VGSeq
-
-
M2
Figure 4.1 CMOS Composite transistors.
33
If two CMOS Composite transistor are connected in series as shown in Figure 4.2 the output current is given by: (4.6)
Where I1 and I2 are given by:
(4.7)
(4.8)
If the
then the total output current Iout is given by: (4.9)
In equation 4.9 the output current is linearly proportional to the input voltage with a proportional constant equal to transconductance value which can be controlled by the voltage (VC) as shown in equation 4.10. (4.10)
There are some problems associated with the SISO using CMOS composite transistor. Firstly, the threshold voltage VTeq in equation 4.10 is a temperature dependent. Hence, the transconductance is also a temperature dependent. Secondly, the equation 4.10 is assumed the two composite transistor are totally matched which is difficult to implement. 34
VDD
Vc
M1
I1
M2 Iout
Vin M3
I2 M4
-Vc
VSS Figure 4.2 SISO using CMOS composite transistor.
35
4.2.2 Differential Input-Single Output Transconuctor Another realization of OTA is Differential Input-Single Output transconuctor (DISO). In Figure 4.4 all transistors are assumed in saturation region also the differential transistors (M1, M2) are assumed matched and the current mirror transistors (M4, M4) are matched with unity gain. The output current is given by: (4.11) √
√
In equation 4.11 there is a nonlinear term (
)
that will affect the performance of the
transconductor. There are different techniques to reduce the effect of that term and example of which is the use degeneration resistor with the differential pair.
36
VDD
M3
M4 I4 = I3 = I1
I3 = I1
Iout
I1 V1
I2
M1
M2
+ Vid = V1-V2 V2 IRef
VSS Figure 4.3 Differential input-Single output transconuctor.
37
4.2.4 Differential Input- Differential Output Transconuctor A very common transconductance is the differential input- differential output transconuctor which shown in Figure 4.4. If the transistors (M1 to M4) are working in saturation region and they are matched. Then the differential output current (Iout1 – Iout2) can be derived as following:
(4.12.1)
(4.12.2)
(4.12.3)
(4.12.4)
(4.13)
(4.14)
The transconductance Gm will equal to
.
38
VDD
M5
M7
M6
Iout1
Ia
Ib
Iout2
V1
Vbias M1
M2
M3
M4
M8
V2
Va
Vb
VSS
Figure 4.4 Differential input- differential output transconuctor.
39
CHAPTER 5
Fully differential programmable CMOS OTA 5.1 introduction Designing an OTA with wide range of response and satisfy the performance conditions in terms of power consumption, noise, linearity and frequency response is the optimum goal for any designer. Therefore, a new designing concept is introduced and discussed. In this chapter, low power consumption, fully differential programmable OTA design is implemented. As well as the concept of programmability in analog circuits is introduced.
40
5.2 Digitally Programmable OTA Circuit Principle The concept behind the digital programmable OTA circuit is to connect a resistor between two ideal voltage buffers as shown in the figure 5.1 [8]. Then the current passing the resistor is given by the following equation:
(5.1)
Therefore the transconductance is given by:
(5.2)
From equation 5.2 it is clear that the value of the transconductance can be controlled by the value of the resistor. Using class AB buffer, shown in figure 5.2, will help in achieving low power OTA. The buffer should provide low output impedance, in order to reduce the attenuation at the output, and also provide high current capability. The first condition, low output impedance, can be achieved by taking the output of the buffer from the low impedance node which is the source of the transistor M1. As well as connecting the feedback transistors M3, M4, M7 and M11 is such configuration will help in increasing the transconductance of the transistor M1 and consequentially decrease the output resistance knowing that the output impedance from the source of M1 is given by ( 1/gm ).
41
R V-
V+
Figure 5.1 The concept of the digitally programmable OTA.
42
VDD
Ib M3
M11
M17
M1 Vi Vo Mc Vc M7
M18 M4
Isb
VSS
Figure 5.2 The class AB buffer circuit.
43
If the transistor M1 in saturation mode then the output voltage is given by:
(5.3) √
The class AB configuration is required to control the output current in the both direction with low power consumption. This can be explained as follow, if the output terminal is providing current the voltage at gates of M3 and M11 will increase then the gate voltage of M7 will increase because it is connected to the source of M3 thus the current in M7 will increase. Similarly if the output terminal draws current the voltage at gates of M3 and M11 is decreased hence the current through them is increased and as a result the gate voltage of M7 is decreased also and this will decrease the current in M7 and increase it in M11. Then there is a bi-direction output current. In order to calculate the standby power consumption, assume that all transistors are in saturation region and that M3 and M4 are matched. Then it follows that: (5.4)
(5.5)
In the standby mode no current will draw from the output terminal of the buffer, so the current in M11 is equal to the current in M7 [9]. (5.6)
44
5.3 The AB class buffer simulation results The buffer circuit is simulated using PSPICE 0.25-μm technology under ±0.8 voltage supply. The aspect ratio of the transistor is showed in table 5.1. The input voltage is scanned from -200 mV to 200 mV. Figure 5.3 shows the input and the output of the buffer while it is loaded by 1KΏ resistor. Figure 5.4 shows the frequency response of the buffer when a load of 5 pf and 1KΏ is connected to the output. The buffer has bandwidth of 75 KHz. Table 5.1 The aspect ratio of the AB class buffer. MOS transistor M1 Mc M3 , M4 M7 M11 , M17 M18
The aspect ratio 10/1 0.5/0.25 0.5/0.5 3/0.5 1/0.5 1.5/0.5
Unit µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm
45
200mV
00 V 403mV
-200
-200mV
-400mV
-400
-600 -200
-600mV -200mV V(1)
-150
-150mV V(8)
-100mV
-100
-50
-50mV
o V(1) o V(8)
-0mV
0
50mV
50
100mV
100
150mV
150
200mV
200
vid*2
Input voltage (mV)
Figure 5.3 shows the input and the output of the buffer.
100mV
100
Output voltage magnitude (mV)
Output voltage (mV)
200
75 50mV
25
00 V 100mHz 1.0Hz 100mHz 1.0Hz V(8) o I(Ro1)-I(Ro2)
10Hz
10Hz
100Hz 1.0KHz 100Hz 1.0KHz Frequency Frequency
10KHz 10KHz
100KHz 100KHz
1.0MHz
1.0MHz
Figure 5.4 shows the frequency response of the buffer.
46
5.4 Digital Programmable OTA
To apply the programmability concept in the circuit the resistor in between the two buffers terminals in figure 5.1 is replaced with a linearized transistor array. The resistance of the transistor will be: (5.7)
Where IDS depends on K constant:
(5.8) . (5.9)
Where μn is the electron mobility, Cox is the gate oxide capacitance per unit area, and W/L is the transistor aspect ratio. As a result, the value of the resistor is controlled by the aspect ratio of the NMOS transistors array, and then the overall transconductance will depend directly on the NMOS transistor aspect ratio. By connecting the gate of the NMOS transistor to the maximum power supply it will operate the transistor in linear mode keeping in mind the bulk is always connected to the minimum power supply. Similarly, connecting the gate to the minimum power supply will turn the transistor off. Through this method the circuit can be easily digitally controlled.
47
Figure 4.5 shows the overall OTA which consists of two AB class buffers and a transistor array in between. The function of the transistors M19, M20, M21 and M22 is to copy the currents from the output terminals of the buffers to the output terminals of the overall OTA. The current mirroring will provide more flexibility over the transconductance value and that by control the aspect ratio of the transistor.
5.5 Common mode feedback circuit (CMFB)
To ensure the output voltage of the OTA is balanced and a common mode feedback circuit (CMFB) is added to the OTA as shown in the figure 5.6. The function of the CMFB is to determine the common mode voltage and control it to a pre-specified value (VCM) usually equal to midrail, so in case of dual power supply the VCM is equal to zero. The CMFB circuit consists of transistors Mce1, Mce2, Mc1, Mcc2, Mc3, M29, and M30 in addition to two resistors (R) and two capacitors (C) [8]. In the ideal case where fully balanced output voltage signals appear at the output terminals, then Vcm0 = 0V. Since the input voltages of CMFB (Vcm0, Vcm) are equal, the tail current Ibcm will be equally divided between Mcm4 and Mcm3. Therefore, a current
will be passed through Mc3,
Mc29 and Mc30 to the output nodes. Similarly, consider the case when the magnitude of Vo2 is less than Vo1 which results in a positive CM signal at Vcm0. This voltage will cause the current in Mc29 and Mc30 to decrease and consequentially reduce the voltages Vo1 and Vo2 until the common mode voltage Vcm0 is to zero again as specified before. Now consider the case where the common mode voltage is negative, by the same method Vcm0 will be adjusted to be equal to Vcm.
48
VDD
16M 15M
18M
3M
21M
11M
12M
5M
0Md
19M
1Md +V
-V
1Vo
2Vo Mdn
Io1
Io2
Vc
Vc
22M
7M
4M
Vbais
20M
9M
6M
Vsb
VSS
Figure 5.5 The digitally programmable OTA circuit based on the AB class buffer [9].
49
Figure 5.6 The overall digitally programmable OTA with CMFB circuit [8].
50
Io1
Vo1
M21
Mhcm1
Mc29
Vbais
M22
M16
Vc
V+
Vsb
Mcc1
M1
M3
M15
M4
M7
M11
Mdn
Md1
Md0
M9
M12
VSS
VDD
M2
M6
Mcc2
M5
M18
M20
Vc
V-
M19
Mhcm2
Io2
Vo2
Mc30
Mcs2
Vcm
Mcs1
Mcm
Mc1
Mc3
Mc2
Vo1
Mcme
C
Mc1 R
C
Mc2 R
Vo2
5.6 Overall OTA simulation results The OTA shown in figure 5.6 is simulated in PSPICE under ±0.8V supplies and using four NMOS transistors in the digital array to provide fifteen output combinations. Table 5.2 shows the OTA transistors aspect ratio. Figures 5.7 and 5.8 show the differential output current and the derivative of the differential output current, respectively, of the proposed OTA for different four bit code word assuming that the output terminals of the transconductance are loaded by Ro1 = Ro2 =1 KΏ. The Gm value varies from 1 nA/V up to 15 nA/V, while the input voltage is scanned from -20 mV to 20 mV. Moreover, the magnitude frequency response of the OTA is shown in figure 5.9. The total power consumption of the OTA is 1.66 μW. These results satisfy the recommended conditions of the OTA to be used in EEG detection systems.
51
Table 5.2 The transistors aspect ratio, components and biasing voltages values of the OTA in figure 5.6.
MOS transistor M1 , M2 Mc1 , Mc2 M3 , M4,M5,M6 M7,M9,M11,M12 M15, M16,M18 M17 M19,M20,M21,M22 Md0 Md1 Md2 Md3 Mce1,Mce2 Mcc1,Mcc2 Mcs1 Mcs2 Mcme Mcm Mhcm1,Mhcm2
The aspect ratio 2/0.5 0.75/10.25 0.5/50.5 35/0.5 1/1 0.75/1.25 0.75/25 0.5/80 0.5/40 0.5/20 0.5/10 0.5/0.5 1/0.5 0.5/45 0.5/2.25 1/4.5 1/0.5 0.5/2.25
Unit µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm
COMPONENT Rce1,Rce2 Ce1,Ce2
100 1
Ώ pF
VOLTAGES Vbias Vsb Vd Vc Vcm
-0.25 0 0.71 -0.3 0
V V V V V
52
17n
1111
15n
10
10n
(nA/V)
Output trans-conductance
17 15
5
5n
0
0 -20mV -16mV -12mV D(I(Ro109)- I(Ro209)) D(I(Ro110)- I(Ro210)) D(I(Ro101)- I(Ro201)) D(I(Ro102)- I(Ro202)) D(I(Ro108)-I(Ro208))
-16
-20 o D(I(Ro1)-I(Ro2))
-12
-8mV D(I(Ro111)- I(Ro211)) D(I(Ro103)- I(Ro203))
-8
0001 4 -4 0 Input voltage (mV)
-4mV 0V D(I(Ro112)- I(Ro212)) D(I(Ro104)- I(Ro204))
4mV D(I(Ro113)- I(Ro213)) D(I(Ro105)- I(Ro205))
8mV D(I(Ro114)- I(Ro214)) D(I(Ro106)-I(Ro206))
8
12mV 16mV D(I(Ro115)- I(Ro215)) D(I(Ro107)- I(Ro207))
12
20mV
16
20
2*vid
Figure 5.7 The derivative of the differential output current of the proposed OTA for different 4-bit code words.
400pA
400 200
Output current (pA)
200pA
1111 0
0A
0001 -200pA
-200 -400
-400pA -20mV I(Ro109)- I(Ro209) I(Ro102)- I(Ro202)
-16mV I(Ro110)- I(Ro210) I(Ro103)- I(Ro203)
-16 -20 o I(Ro1)-I(Ro2)
-12mV -8mV -4mV I(Ro111)- I(Ro211) I(Ro112)- I(Ro212) I(Ro104)- I(Ro204) I(Ro105)- I(Ro205)
-12
-8
0V I(Ro113)- I(Ro213) I(Ro106)-I(Ro206) 2*vid
4mV I(Ro114)- I(Ro214) I(Ro107)- I(Ro207)
4 -4 0 Input voltage (mV)
8mV I(Ro115)- I(Ro215) I(Ro108)-I(Ro208)
8
12mV 16mV I(Ro101)- I(Ro201)
12
16
20mV
20
Figure 5.8 The differential output current of the proposed OTA for different 4-bit code words.
53
1111
Magnitude (nA)
3
2
1 0 100mHz
0001 1.0Hz
10Hz
100Hz
o I(Ro1)-T(Ro2)
1.0KHz
10KHz
100KHz
1.0MHz
Frequency
Figure 5.9 The magnitude response of the output differential current of the proposed OTA for different 4 bit code words.
Output current
100pA 1.0pA
38db ∆F=20 Hz ∆F=20 Hz ∆F=20 Hz
10fA
100e-18A 10e-18A 0
10 20 30 40 o I(Ro101)- I(Ro201)
50
60
70
80
90
100 110 120 130 140 150 160
Frequency
Figure 5.10 The IM3 test for the OTA for the bet word (0001).
54
2.452uW 2.450uW
Power
2.448uW 2.446uW
Power dissipation = 2.4422uW
2.444uW 2.442uW -200mV -160mV -120mV -80mV -40mV 0mV o (I(X1.Vss)-I(X1.Vdd))* V(X1.4)
40mV 80mV 120mV 160mV 200mV
Figure 5.11 The OTA power dissipation.
55
CHAPTER 6
Current Feedback Instrumentation Amplifier
6.1 Introduction Current feedback instrumentation amplifier (CFIA) is considered one of the best topologies because it has better CMRR and higher input impedance in comparison to other topologies such as switched capacitor and three op-amp instrumentation amplifier. Figure 6.1 shows the system functional blocks of CFIA. The input transconductor (Gm,in) converts the differential input voltage (Vin) into a differential input current (Iin) and the feedback transconductor (Gm,fb) converts the feedback voltage (Vfb) into feedback current (Ifb). The Vfb is attenuated form of the output voltage (Vout) through voltage divider R1 and R2. The amplifier Aout function is to maintain the Vout in such way to keep the summation of Iin and Ifb zero under the steady state conditions. The gain and the dominant frequency of the CFIA shown in figure 6.1 is given by:
(6.1) (
(
)
(6.1.1)
)
(
(
)
)
(6.2)
56
(6.3) (
)
This topology has very high CMRR due to the input transconductor that isolates the common mode voltage by converting the differential input voltage into differential current, so the CMRR of CFIA is determined by the CMRR of Gm,in. One of the great advantages of CFIA is that the signal is manipulated in current domain where the summation and subtraction are much easier than in voltage domain. Furthermore, current domain can help in calibrating some sources of error for example the offset, gain error and mainly the mismatch between the input and feedback transconductors.
57
CM
+ Vin
+Gm,in -+
X1
Aout +
X2
-
CM +Gm,fb -+
Vo R1
R2
+ Vfb -
Vref
Figure 6.1 Current feedback instrumentation amplifier (CFIA).
58
6.2 The system elements From equations (6.1) and (6.2) it is clear that there is a tradeoff between the gain and the bandwidth of the instrumentation amplifier. In order to have high gain with reasonable bandwidth that can pass the signal and reject the noise (≈100 Hz) the capacitors in figure 6.1 should have value in fF. This small value of the capacitance can be achieved by using the parasitic capacitance of the NMOS transistor when its terminals are connected as showed in figure 6.2.
It is clear from equation (6.1) the gain depends on the ratio of the two OTAs on the resistance ratio
and also depends
. From the figure 5.7 the maximum ratio for the OTAs is 15 (when Gm,in
has bit word 1111, and the Gm,fb has bit word 0001), so the gain will be 15*(
.
In order to have high gain the resistance ratio should be high as well as each individual resistor should have high resistance, so no need for buffer stage in the op-amp and this consider as an advantage in the design. The maximum resistance can be implemented in the IC is 10KΏ. One way to implement high resistance is by using NMOS transistor in linear region, so it works as a resistor and it resistance will depend on the aspect ratio of the transistor. To ensure that the NMOS transistor is working in the linear region the body should be connected to the minimum supply voltage and the gate should be connected to the maximum supply voltage. Figure 6.3 shows how to connect NMOS transistor to works as a resistor. Figure 6.4 shows the instrumentation amplifier after replace the passive elements (CM, R1 and R2) by the active elements.
59
G S
D B
Figure 6.2 NMOS transistor used as a capacitor.
D B
G
Vin Vss
VDD S
Figure 6.3 NMOS transistor used as a resistor.
60
CM S
G
B D
X1 -
Aout
+
Gm,in
Vin
Vo
-
X2
R1
+
+
D B
-
G CM
Vss
VDD S
B D
S
R2
G +
D
-
Gm,fb
Vfb
B
G
-
+
Vss
VDD S
-
+
Vref
Figure 6.4 The instrumentation amplifier with active elements.
61
6.3 simulation results of the NMOS transistor as a resistor The circuit in figure 6.2 is simulated using PSPICE 0.25-μm technology. Table 6.1 shows the aspect ratios of the transistor and there corresponding resistance values. Figure 6.4 shows the resistance values while the applied voltage is scanned from -20 mV to 20 mV.
Table 6.1 The aspect ratios of the NMOS transistor and there corresponding resistance values. Procedure (W/L) (W/L) (W/L) (W/L) (W/L) (W/L) (W/L) (W/L) (W/L) (W/L) (W/L) (W/L)
The proposed 0.5/2 0.5/4.25 0.5/6.5 0.5/8.5 0.5/10.75 0.5/12.75 0.5/15 0.5/17 0.5/19.25 0.5/21.5 0.5/107 0.5/215
µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm µm/ µm
Resistance 100 200 300 400 500 600 700 800 900 1000 5000 10000
KΏ KΏ KΏ KΏ KΏ KΏ KΏ KΏ KΏ KΏ KΏ KΏ
62
Resistance (MΩ)
1.5M 1.5
11.0M
0.5M 0.5
0
0 -20mV 1/D(ID(M10)) 1/D(ID(M20))
-20
-16
-16mV 1/D(ID(M11)) 1/D(ID(M21))
-12
-12mV 1/D(ID(M12))
-8
-8mV 1/D(ID(M13))
-4
-4mV 1/D(ID(M14))
0
0V 1/D(ID(M15))
4
8
4mV 1/D(ID(M16))
8mV 1/D(ID(M17))
12
12mV 1/D(ID(M18))
16
20
16mV 1/D(ID(M19))
20mV
Input voltage Vd*2 (mV)
(a)
12M 12
Resistance (MΩ)
101 0 M
88 M
66 M 4 -20
4M -20mV 1/D(ID(M100))
-16- 11 /5 Dm (V I D ( M 1 0 1 )-12 ) o Vds(M)/Id(M)
-10mV
8
-5mV
00 mV Vd*2 4Input voltage (mV)
4
5mV
8
10mV
12
15mV
16
20
20mV
(b) Figure 6.5 The resistance values of the NMOS vary from 100KΏ to 10MΏ based on aspect ratio in table 6.1.
63
6.4 The instrumentation amplifier simulation results The instrumentation amplifier shown in figure 6.4 is simulated in PSPICE. Figure 6.6 shows the possible gain values for different resistance ratio (2,3,4,5,6,7,8,9,10 and 50). The gain results approximately follow the calculated values from equation (6.1.1) with constant error around 3 dB less than the expected ones. Figure 6.7 shows the frequency response with gain (54dB) and its phase margin (63ᵒ). The instrumentation amplifier has input referred noise of 5.9 µV/√
which has been
measured at 1 KHz as showed in figure 6.8. Figure 6.9 presents the third-order intermodulation test (IM3) with two tones at (60 and 80 Hz).The IM3 test reveal a value of −22.4 dB for the instrumentation amplifier. Figure 6.10 (a) shows the time representation of corrupted EEG signal with additive noise and (b) shows the output signal of the proposed instrumentation amplifier while the gain sitting of the amplifier is 54dB. Figure 6.11 shows the common mode gain is -84 dB, differential gain 54 and the CMRR is 138 dB. Figure 6.12 shows the gain magnitude of the instrumentation amplifier obtained from different four bits word combination of the input OTA while keeping the feedback OTA constant (0001) and the resistance ratio (
. The gain in figure
6.12 varies between 33dB to 54dB as expected. The total power consumption of the instrumentation amplifier is 9.4 µW. Table 6.2 Performance parameters of the proposed instrumentation amplifier. Electrical parameters CMOS technology (µm) Supply voltage (V) Number of transistors DC gain (dB) Unity gain frequency (KHz) Phase margin (degree) Bandwidth (Hz) Input referred noise (µV/√ ) CMRR (dB) Inband IM3 (dB) Power dissipation (µW)
obtained 0.25 ±0.8 84 54 165 63 330 5.9 138 -35 9.4
64
Figure 6.6 The possible gain values for different resistance ratio (2,3,4,5,6,7,8,9,10 and 50).
Figure 6.7 The frequency response of the instrumentation amplifier.
65
Input referred noise spectral density (uV/√
)
1.00
0.75
0.5
)1.000K, 63.265n) 1mHz 10mHz 100mHz 1Hz
10Hz
100Hz 1KHz 10KHz 100KHz 1MHz 10MHz 100MHz 1GHz
Frequency
o V(INOISE)
Figure 6.8 The input referred noise of the instrumentation amplifier.
100mV
Magnitude
10mV
35 dB
100uV
∆f = 20Hz ∆f = 20Hz ∆f = 20Hz
1.0uV 100nV 0
10 20 o V(115)
30
40
50
60
70 80 90 Frequency (Hz)
100
110
120
130
140 150
Figure 6.9 The third-order intermodulation test (IM3) with two tones at (40 and 60 Hz).
66
(b)
(a)
Figure 6.10 (a) shows the time representation of corrupted EEG signal with additive noise and (b) shows the output signal of the proposed instrumentation amplifier while the gain sitting of the amplifier is 54 dB.
CMRR=138 dB 150
Magnitude
100
Avid =54 dB
50 -0 -50
ACM =83.8 dB
-100 -150 10mHz 100mHz 1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz o DB(V(7)/V(1,2)) o DB(V(70)/V(1000)) o DB((V(7)/V(1,2))/(V(70)/V(1000))) Frequency
Figure 6.11 The frequency response of the instrumentation amplifier in differential mode and common mode.
67
Gain magnitude (dB)
80 1111
60 40
0001 20 0 -20 10m
30m
0.1
0.3
o DB(V(115)/V(1,2))
1.0
3.0
10 30 100 Frequency (Hz)
300 1.0K 3.0K 10K 30K 100K
Figure 6.12 The gain magnitude of the instrumentation amplifier for the different four bits word combination for the input OTA.
68
CHAPTER 7
Instrumentation amplifier Layout 7.1 Introduction In order to complete the process of designing the instrumentation amplifier and to make it ready for use, a layout should be designed. An integrated circuit can be designed by a layout which is represented by a set of photo mask layers in a two dimensional configuration that builds a three dimensional of component of the integrated circuit and defines the different regions of the circuit components. The importance of this process is that it gives the actual outline of circuit before fabricating the circuit into a chip because that it creates an accurate model of the circuit, so that the simulated results after the layout imitates the actual response of the circuit and it demonstrates if the circuit is still working well. In other words, the layout process gives the factual calculation of the parasitic effect in the circuit due to the components and the connection between them. The parasitic effect is unavoidable and unwanted capacitance between parts of an electronic component or circuit simply because of their adjacency to each other. For this reason it is ought to do the layout for the Instrumentation amplifier circuit and also be able to simulate the layout extraction results (post layout results) to ensure the functionality of the circuit.
69
7.2 Layout Process Silicon is the basic material used in fabrication which is used as a wafer for CMOS circuits. This wafer is doped with donor atoms, such as phosphorus for an n-type wafer, or acceptor atoms (A dopant atom that when added to a semiconductor it can form a p-type region), such as boron for a ptype wafer. Our dialogue centers on a p-type wafer (the most common substrate used in CMOS IC processing) because there is available a software to optimize the layout; however it might not be the most favorable method. When designing CMOS integrated circuits with a p-type wafer, NMOS are fabricated directly in the p-type wafer, while p-channel transistors PMOS are fabricated in an n-well. The substrate or well are sometimes referred to as the bulk or body of a MOSFET. That is why this process is referred to as n-well process. Different types of masks can be used to configure the components such as poly-silicon, metal, diffusion, contacts and wells. While designing the layout, the type of the transistors should be taken into account. NMOS transistors can be fabricated directly if the wafer is p-type but the PMOS transistors need an n-well layer to be fabricated in it. Throughout this chapter, the layout of a transistor, resistor and capacitor will be discussed then the layout of the Instrumentation amplifier will be introduced.
70
7.3 MOS transistor, resistor and capacitor layout
Any CMOS circuit consists of group of transistors and several resisters and capacitors. The layout of a NMOS transistor with an aspect ratio of (32 μm / 3 μm) is shown in Figure 7.1 with the different layers. Similarly shown in Figure 7.2 the layout of a PMOS transistor with an aspect ratio of (34 μm / 3 μm). The height of the active (green) is the width of transistor and the width of the poly-silicon (red) is the length of the transistor. Metal above an active region represents the layout of the resistance value as shown in Fig 7.3. The value of the resistor determines the active size as given (7.1)
Where ρ is defined as resistivity of the material, W and L are the width and the length of resistor and t is known as thickness of the resistor. On the other hand, the capacitor is represented by an active region under two parallel metal layers as shown in Fig 4.3. The value of the capacitance value determines the active size as given
(7.2)
Where 𝜀ox is the permittivity of oxide layer and the
ox
represents the thickness of the oxide layer, W
& L are the width and length of the capacitor.
71
7.4 Instrumentation amplifier layout The layout of proposed Instrumentation amplifier circuit is done using L-edit software using 0.25μm technology model which is shown in Figure 7.5.
Figure 7.1 NMOS transistor layout in L-edit software.
72
Figure 7.2 PMOS transistor layout in L-edit software.
73
Figure 7.3 Resistor layout in L-edit software.
Figure 7.4 Capacitor layout in L-edit software.
74
Figure 7.5 The instrumentation amplifier layout.
75
CHAPTER 8
Conclusion In conclusion of this work a design of an instrumentation amplifier for biomedical purposes was discussed and designed. This design done based on the important characteristics of the biomedical signals with appropriate size for being a portable device. The main and basic needed information and design characteristics equations to be considered in the design were shown and discussed through the chapters. The design of each part in the instrumentation amplifier is presented with their simulation results. The proposed design of the instrumentation amplifier meets the important aspects for a portable biomedical application. The DC gain is 54 dB and the bandwidth is 330 Hz. The input referred noise is 5.9 µV/√
. Moreover, the layout is done to the instrumentation amplifier. Table
8.1 shows a comparison between the proposed IA and other works.
76
Reference
[1] Jr. John W. Clark, Michael R. Neuman, Walter H. Olson, Robert A. Peura, and Jr. Frank P. Primiano, "The Origin of Biopotentials," in Medical instrumentation application and design, 4th ed., John G. Webster, Ed. United States of America: John Wily & Sons, 2010, p. 163. [2] M. Teplan, "FUNDAMENTALS OF EEG MEASUREMENT," MEASUREMENT SCIENCE REVIEW, Volume 2, Section 2, vol. II, 2002. [3] Patrick Celka, Boualem Boashash, and Paul Colditz, "Preprocessing and Time-Frequency Analysis of Newborn EEG Seizures," IEEE ENGINEERING IN MEDICINE AND BIOLOGY, 2001. [4] William J. Ray and Semyon Slobounov, "Fundamentals of EEG methodology in concussion resaerch ," in Foundations of Sport-Related Brain Injuries, Semyon M. Slobounov and Wayne J. Sebastianelli, Eds. New York, United States of America: Springer, 2006, pp. 223-224. [5] Saeid Sanei and J.A. Chambers, "Introduction to EEG," in EEG Signal Processing. Chichester, England: John Wiley & Sons, Ltd, 2007, pp. 10-16. [6] Refet Fırat, Chris Van Hoof, and Robert Puers, Biopotential Readout Circuits for Portable Acquisition Systems, Mohammed Ismail, Ed.: Springer, 2009. [7] J. Mahattanakul and J. Chutichatuporn, ""Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme," ," Circuits and Systems I: Regular Papers, pp. pp.1508,1514, Aug. 2005. [8] Ahmed Bamakhramah and Saeed A. Al-Tunaiji, S. A. Mahmoud, "“Low noise Low Pass Filter for ECG Portable Detection Systems with Digitally Programmable Range” ," in Circuits, Systems, and Signal Processing (CSSP9478), vol. Vol.32, pp. pp. 2029-2045, Aug. 31, 2013. [9] M. Ismail H. Elwan, "A CMOS digitally programmable class AB OTA circuit," IEEE Trans. Circuits., vol. 47, no. II, pp. 1551–1556, 2000.
77
Appendix A
Matlab code for the Op-amp parameters calculations
% design parameters clear all clc UnCox = 1.558e-4; UpCox = 9.55e-5; Up = 221.4e-4; Cc =0.5e-12; CL =5e-12; Vop = 0.2; Von = 0.2; Vip = 0.3; Vin = 0.3; SR = 5e6; Vtn = 0.407; Vtp = 0.6832; wn = 2*pi*(5e6); %q = 65; Vdd = 0.8; %%%% ID7 = SR*(Cc+CL) L6 = sqrt((3*Up*Vop*Cc)/(2*wn*(Cc+CL)*2.1445)) W6 = (2*SR*(Cc+CL)*L6)/((UpCox)*((Vop)^2)) A6 = W6/L6 ID5 = Cc*SR A12 = ((wn^2)*Cc)/(UnCox*SR) A58 = (2*SR*Cc)/(UnCox*((Vin-Vtn-(SR/wn))^2)) A7 = ((Cc+CL)/Cc)*A58 A34 = (A6/(2*A7))*A58 A9 = (2*Cc*SR)/(UpCox*Vop*(Vdd-Vop-(2*Vtp))) A9 = A6/(1+(CL/Cc))
78
Appendix B
Spice code
** circuit descripion ** *inputs are 1 & 2 X1 1 2 4 5 23 24 25 26 OTA X2 0 3 4 5 233 244 255 266 OTA X3 5 4 115 OPAMP
**** differntial mode signal **** *vid 1 100 dc 0v ac 100u *e 2 100 1 100 -1
*commen mode signal Vcm0 1000 0 DC 0v
**** Pulse **** *vid 1 100 Pulse (-50u +50u 10m 1n 1n 10m 20.000002m) *e 2 100 1 100 -1
**** EEG ***** vid 1 1001 SIN (0 15u 13Hz) e 2 101 1 1001 -1
79
Vid2 1001 1002 SIN (0 10u 30Hz) e2 101 102 1001 1002 -1 Vid3 1002 1000 SIN (0 3u 2000Hz) e3 102 1000 1002 1000 -1 **** load ****
*VDDD 400 0 0.8 *VSSS 500 0 -0.8
*MR 115 400 3 500 modn L=80u W=0.5u *R 3 0 50K
*R1 115 3 5Meg *R2 3 0 100k
VDD 400 0 2.5 VSS 500 0 -2.5
Md1 115 400 3 500 modn L=107u W=0.5u Md2 3 400 0 500 modn L=2u W=0.5u
* CM *CM1 5 115 5f *CM2 4 0 5f
80
MC1 5 115 5 5 modn L=2u W=2u MC2 4 0 4 4 modn L=2u W=2u
* DIGITAL FOR IN Gm Vd0 23 0 0.71V Vd1 24 0 0.71V Vd2 25 0 0.71V Vd3 26 0 0.71V
* DIGITAL FOR FB Gm Vd00 233 0 0.71V Vd11 244 0 -0.71V Vd22 255 0 -0.71V Vd33 266 0 -0.71V
***************************************************************************
* OTA [node1 (+in) ,node2 (-in), node7 (+o), node15 (-o)]
*
V+ V- I+ I-
.SUBCKT OTA 1 2 7 15 23 24 25 26
* power supply
81
Vdd 4 0 0.8V Vss 5 0 -0.8V
*FIRST BUFFER TRANSISTORS
M1 3 1 8 8 modn L=0.5u W=2u Mcc1 8 9 5 5 modn L=10.25u W=0.75u M15 3 50 4 4 modp L=1u W=1u M3 4 3 6 6 modn L=50.5u W=0.5u M4 6 11 5 5 modn L=50.5u W=0.5u M7 8 6 5 5 modn L=0.5u W=35u M11 8 3 4 4 modp L=0.5u W=35u M16 50 50 4 4 modp L=1u W=1u M17 50 51 5 5 modn L=1.25u W=0.75u M21 7 3 4 4 modp L=25u W=0.75u M22 7 6 5 5 modn L=25u W=0.75u
*************************************************
*SECOND BUFFER TRANSISTORS
M2 12 2 13 13 modn L=0.5u W=2u Mcc2 13 9 5 5 modn L=10.25u W=0.75u M18 12 50 4 4 modp L=1u W=1u
82
M5 4 12 14 14 modn L=50.5u W=0.5u M6 14 11 5 5 modn L=50.5u W=0.5u M9 13 14 5 5 modn L=0.5u W=35u M12 13 12 4 4 modp L=0.5u W=35u M19 15 12 4 4 modp L=25u W=0.75u M20 15 14 5 5 modn L=25u W=0.75u
**************************************************
*TRANSISTOR ARRAY (R) (MD1 IS THE LEAST SiGNIFICANT BIT)
*R1 8 13 0.14285Meg
Md1 8 23 13 5 modn L=80u W=0.5u Md2 8 24 13 5 modn L=40u W=0.5u Md3 8 25 13 5 modn L=20u W=0.5u Md4 8 26 13 5 modn L=10u W=0.5u
**************************************************
* COMMON FEEDBACK TRANSISTORS
Mce1 4 7 21 21 modn L=0.5u W=0.5u Mce2 4 15 22 22 modn L=0.5u W=0.5u
83
Mc1 10 16 17 17 modn L=0.5u W=1u Mc2 4 18 17 17 modn L=0.5u W=1u Mc3 10 10 4 4 modp L=1u W=1u Mcs1 52 50 4 4 modp L=45u W=0.5u Mcs2 52 52 5 5 modn L=2.25u W=0.5u Mc29 7 10 4 4 modp L=1u W=1u Mc30 15 10 4 4 modp L=1u W=1u Mcme 18 52 5 5 modn L=4.5u W=1u Mcm 17 52 5 5 modn L=0.5u W=1u Mhcm1 7 52 5 5 modn L=2.25u W=0.5u Mhcm2 15 52 5 5 modn L=2.25u W=0.5u
*COMMON FEEDBACK COMPONENTS
Ce1 21 18 1p Ce2 22 18 1p
Rce1 21 18 100 Rce2 18 22 100
**************************************************
*BAIS VOLTAGES
84
Vbias 51 0 -0.25V Vsb 11 0 0V Vcm 16 0 0V Vc 9 0 -0.3V
.ENDS
***************************************************************************************** ***************************************************
*
V- V+ Vo
.SUBCKT OPAMP 1 2 7 * power supply Vdd 4 0 0.8V Vss 5 0 -0.8V
*DIFFERENTIAL INPUT TRANSISRORS WITH ACTIVE LOADS
M1 3 1 8 8 modn L=1u W=1u M2 6 2 8 8 modn L=1u W=1u M3 3 3 4 4 modp L=1u W=1u M4 6 3 4 4 modp L=1u W=1u M5 8 9 5 5 modn L=3u W=2u 85
* GAIN STAGE TRANSISTORS
M6 7 6 4 4 modp L=2u W=30u M7 7 9 5 5 modn L=1.25u W=6.25u
*BIAS CIRCUIT
M8 9 9 5 5 modn L=3u W=2u M10 9 11 12 12 modp L=1u W=1u M11 12 13 4 4 modp L=1u W=1u M12 11 11 13 13 modp L=1u W=1u M13 13 13 4 4 modp L=1u W=1u M14 11 9 14 14 modn L=2u W=2.5u
RB 14 5 62K
* OUTPUT STAGE **buffer stage**
*M100 200 7 300 300 modn L=0.5u W=2u *M3100 700 700 300 300 modn L=1u W=10u *Mc00 300 600 5 5 modn L=10.25u W=0.75u *M300 4 200 800 800 modn L=50.5u W=0.5u *M400 800 900 5 5 modn L=50.5u W=0.5u
86
*M700 700 800 5 5 modn L=0.5u W=35u *M1100 700 200 4 4 modp L=0.5u W=35u
*M17 10 10 4 4 modp L=0.5u W=1u *M18 10 10 9 9 modn L=0.5u W=1.5u
**biasing circuit
*M1700 1200 1300 5 5 modn L=10u W=0.75u *M1600 1200 1200 4 4 modp L=1u W=12.5u *M1500 200 1200 4 4 modp L=1u W=1u *M1400 700 1200 4 4 modp L=1u W=1u
** biasing voltages *Vc00 600 0 -0.3 *Vsb00 900 0 0.1 *Vbias00 1300 0 -0.25
*MN 4 7 15 15 modn L=1u W=50u *MP 5 7 15 15 modp L=0.25u W=25u
*compensation network
M9 10 11 6 6 modp L=2u W=1u Cc 7 10 0.5p
87
.ENDS ***************************************************************************************** **************************************************
*-----------------------------*MOSFET model .MODEL modn NMOS +TOX
= 8E-9
+XJ
= 1E-7
+K1
= 0.4728294
+K3B
LEVEL = 7
= -10
NCH
= 2.2E17
K2 W0
+DVT0W = 0
= 3.621074E-3 K3
DVT2 = -0.3
+U0
= 361.3464355 UA
+UC
= 4.669186E-11 VSAT = 1.898742E5
+AGS
= 0.2592162
B0
= -9.67751E-10 UB
+DWG
=1
=0
A0
A2
= 1.3381235 = 5E-6
= 0.3487525
PRWG = 0.0713836
PRWB = -7.21866E-3
WINT = 1.389179E-7 LINT = 1.24319E-9
= -1.034792E-8 DWB
+NFACTOR = 0.7366118 +CDSCD = 0
= 2.889157E-18
= 2.220067E-6 B1
+KETA = -9.077245E-3 A1
+WR
= 2.193565E-7
DVT2W = 0
DVT1 = 0.4276766
+RDSW = 780.376869
= 70.0489524
= 1.830495E-5 NLX
DVT1W = 0
+DVT0 = 0.802594
VTH0 = 0.4074928
CIT
= 9.824117E-9 VOFF = -0.0869274 =0
CDSCB = 0
CDSC = 2.4E-4 ETA0 = 0.0346215
+ETAB = -7.988336E-3 DSUB = 0.3317286
PCLM = 1.9546403
+PDIBLC1 = 4.161735E-3 PDIBLC2 = 1.19743E-5
PDIBLCB = 0.1
+DROUT = 2.748338E-3 PSCBE1 = 7.42428E8
PSCBE2 = 1E-3
+PVAG = 0
DELTA = 0.01
RSH
= 3.9 88
+MOBMOD = 1
PRT
+KT1
= -0.11
+UA1
= 4.31E-9
+AT +WW +LL +LWN
UB1 WL
=0
LLN
=1
KT2
=0
LW
=0
CJ
= 0.3510986
=0
=0
CAPMOD = 2
CGDO = 2.58E-10
+CGBO = 1E-12
= -5.6E-11
=1
WWL
=1
LWL
UC1
WLN
=1
= -1.5
= 0.022
= -7.61E-18
WWN
+XPART = 0.5
+MJ
UTE
KT1L = 0
= 3.3E4
=0
=0
CGSO = 2.58E-10
= 1.012513E-3 PB
= 0.8
CJSW = 2.862666E-10 PBSW = 0.8
+MJSW = 0.1518459
CJSWG = 1.82E-10
+MJSWG = 0.1518459
CF
=0
+PRDSW = -73.5674578 PK2
PBSWG = 0.8
PVTH0 = -0.0100437
= 3.087074E-3 WKETA = 3.003636E-3
+LKETA = 2.647195E-3
.MODEL modp PMOS +TOX
LEVEL = 7
= 8E-9
+XJ
= 1E-7
NCH
+K1
= 0.3939412
K2
+K3B
= 15.35112
W0
+DVT0W = 0 +DVT0 = 1.4617205
= 8.52E16
VTH0 = -0.6831778
= 0.0308482 = 1E-5
DVT1W = 0
K3 NLX
= 221.3795636 UA
+UC
= 8.567678E-11 VSAT = 2E5
+AGS
= 0.389467
B0
= 1E-9
DVT2W = 0
DVT1 = 0.3569339
+U0
=0
DVT2 = -0.0368562
= 1.573901E-9 UB A0
= 2.419633E-6 B1
= 5E-18
= 1.999067 = 5E-6
89
+KETA = -6.020293E-3 A1 +RDSW = 4E3 +WR +DWG
= 4.394989E-5 A2
PRWG = -0.2146377
=1
PRWB = 0.1688991
WINT = 1.569174E-7 LINT = 0
= -2.578547E-8 DWB
+NFACTOR = 1.8063821 +CDSCD = 0
CIT
= 9.89001E-9 =0
VOFF = -0.1219424
CDSC = 2.4E-4
CDSCB = 0
ETA0 = 0.0518465
+ETAB = 4.735705E-3 DSUB = 0.4254421 +PDIBLC1 = 0
PCLM = 2.7235598
PDIBLC2 = 4.344554E-3 PDIBLCB = 4.528856E-3
+DROUT = 5.604876E-3 PSCBE1 = 8E10 +PVAG = 4.6592572
PRT
+KT1
= -0.11
+UA1
= 4.31E-9
+WW +LL +LWN
=0 =0
UB1 WL
UTE
=1
+XPART = 0.5
KT2
= -7.61E-18 =0
WWN LLN
= -1.5
UC1
=0
= -5.6E-11
=1
WWL LW
= 2.8
= 0.022
WLN
=1
=1
LWL
RSH
=0
KT1L = 0
= 3.3E4
PSCBE2 = 5.04016E-10
DELTA = 0.01
+MOBMOD = 1
+AT
= 0.6320223
=0
=0
CAPMOD = 2
CGDO = 3.12E-10
CGSO = 3.12E-10
+CGBO = 1E-12
CJ
+MJ
CJSW = 2.91776E-10 PBSW = 0.99
= 0.392439
+MJSW = 0.1676363 +MJSWG = 0.1676363
= 9.916255E-4 PB
CJSWG = 4.42E-11 CF
+PRDSW = -233.4720278 PK2
=0
= 0.8896731
PBSWG = 0.99
PVTH0 = 0.0107102
= 1.861393E-3 WKETA = -6.345721E-3
+LKETA = -0.0207051
90
** analysis requests **
.OP *.DC vid -100mV 100mV 10uV
.AC dec 10 0.01 1G *.Noise V(115) vid .TRAN 1ns 1000ms 0ms 2ms
**output request ** *.PRINT AC Vdb (7) Vp(7) *.PLOT AC Vdb (7) Vp(7)
*.PRINT TRAN V(7) *.PLOT TRAN V(2,1) V(115) *.FOUR 100Hz V(7)
.PLOT NOISE ONOISE INOISE .PROBE .end
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