performance phase locked systems such as frequency synthesizers used in .... [12] 'Analysis and design of analog integra
Low Phase Noise Fully Integrated VCO Balasaheb Darade* and Tarun Parmar, Student Member, IEEE *
[email protected],
[email protected] J.N.E.College, Aurangabad
Abstract—A successful attempt is being done to design a very low phase noise fully integrated VCO in 0.5um BiCMOS process with 10-20% tuning range. The VCO uses MOS capacitors for tuning and on-chip inductor as LCtank circuit. On-chip CMOS bandgap Bias Network is implemented using large MOSFET’s operating in sub threshold region along with fast BJTs. Our aim is to maximize Q of the LC tank circuit so as to reduce phase noise. Index Terms— VCO, Bi-CMOS, On-chip Inductor, MEM tunable capacitors, Bandgap Bias Network
I. INTRODUCTION
L
ow phase noise VCO’s are an integral part of highperformance phase locked systems such as frequency synthesizers used in wireless transceivers [1] and also needed for good quality of transmission signal [2] .It is very important block of communication devices like Transceivers. While most present implementations of RF VCO employ external inductors to achieve a low phase noise, the current trend is towards VLSI and low cost monolithic solution A critical building block of almost any wireless or wireline transceiver is the local oscillator (LO). When used with a mixer, the LO allows frequency translation and channel selection of radio frequency (RF) signals. The LO is typically implemented as a phase-locked loop (PLL), wherein a voltage-controlled oscillator (VCO) is phase-locked to a high-stability crystal oscillator. A VCO is basically comprised of a gain element and a resonator. The resonator determines the oscillation frequency, and when it is composed of energy storing inductors and capacitors, it is often referred to as an LC tank. A voltagecontrolled varactor diode allows the oscillation frequency of the VCO to be varied. The most critical performance specification for an oscillator is phase noise. In a receiver, the phase noise of the local oscillator limits the ability to detect a weak signal in the presence of a strong signal in an adjacent channel. In a transmitter, phase noise results in energy being transmitted outside of the desired band. To help
minimize phase noise, we need high-Q (low-loss) inductors and capacitors. II. LITERATURE REVIEW A. Introduction Integrated LC voltage-controlled oscillators (VCOs) are common functional blocks in modern radio frequency communication systems and are used as local oscillators to up- and down convert signals. Due to the everincreasing demand for bandwidth, very stringent requirements are placed on the spectral purity of local oscillators. Efforts to improve the phase-noise performance of integrated LC VCOs have resulted in a large number of realizations [3]-[5]. Due to their relatively good phase noise, ease of implementation, and differential operation, cross-coupled inductance–capacitance (LC) oscillators play an important role in high-frequency circuit design [6].
Fig. 1 Steady state parallel LC oscillator Model
B. Design Topology Fig.1 shows the model for a parallel LC oscillator in steady state, where the conductance gtank represents the tank loss and –gactive is the effective negative conductance of the active devices that compensates the losses in the tank. As there are different traditional oscillator topologies like ring oscillators, relaxation oscillators and harmonics oscillators. We are using harmonic oscillator design in our project. Cross-coupled oscillator design is quite popular in current CMOS implementations as it is having a simple topology. Due to relatively good phase noise, ease of implementation and differential operation, crosscoupled inductance capacitance oscillator plays an important role in high-frequency designs.
III. PROTOTYPE DESIGN A. Target Design Specifications 1) Design Frequency: 2) Supply Voltage: 3) Power Dissipation: 4) Tuning Range: 5) Temperature Range 6) Yield
1.95GHz 2.8V to 3.5V =10% -40C to 80 C 95%
B. Inductor For low phase noise, design of inductor with small L and high Q was the major challenge for us. We have designed octagonal shaped inductor of L=7.75nH, with N=3, W=15um,S=20um and Ri=200um. Fig.2 shows the current density simulation using Method of Moments.
D. VCO Core We have chosen reflexive oscillator topology to cancel the loss of resonator using negative resistance cross coupled MOSFETs. Fig.4 shows VCO evolution steps. Fig.4(a) shows lossy tank circuit used as resonator. Gloss is compensated by n and p channel negative channel negative resistance which resulted in better phase noise at given power dissipation with reduced flicker noise[9][10]. We have used differential design to suppress substrate noise and simple low noise current source to minimize noise up-conversion. Both p and n type MOSFET’s are used to achieve high signal swing and good rise/fall time symmetry.Fig.5 shows the implemented VCO Core.
Fig. 4 VCO Evolution
Fig. 2 On-Chip Inductor with EM simulated currents
From EM simulated S and Y parameters obtained optimized inductor model is shown in Fig.3
Fig. 3 Optimized Model of the Inductor
C. MOS Capacitor Designed MOS capacitors (with drain and source tied together) to provide analog frequency tuning with reduced design size. This proved correct approach as inductor takes more space on chip [8]. We have found out the best region of operation for optimum Q (so linearity and high Q both obtained), capacitance can be varied by changing the voltage across it. (i.e. control voltage) and centre frequency of oscillation can be changed.
Fig. 5 Implemented VCO Core
E. Bandgap Bias Network To allow stable biasing independent of supply voltage, temperature and process, we have designed on-chip BiCMOS bandgap bias network optimized with respect to noise behavior. Used CTAT (Complementary to Absolute Temperature) and PTAT (Proportional to Absolute Temperature) combination to realize bandgap [11]-[13].
We have thoroughly designed and analyzed different possible designs and finally come up with Bandgap Bias Circuit (Fig.6) with satisfied response as shown in Fig.7
Fig. 7 Response of the Bandgap Voltage Reference
REFERENCES Fig. 6 Bandgap Voltage Reference
[1]
IV. RESULTS AND CONCLUSION
[2]
. We have obtained clean frequency response from 1.87 GHz to 2.15 GHz. Frequency response at 1.95 GHz is shown fig 8. Within 80 MHz range from centre frequency 1.95 GHz phase noise obtained is also low. So it is suitable for W-CDMA. Our plans are to implement digital tuning for battery operated devices.
[3]
[4]
[5] [6]
[7] [8] [9] [10]
[11] [12] [13]
Fig. 8 Frequency Responses at 1.95 GHz
B.Razavi,” Analysis Modeling and Simulation of Phase Noise in Monolithic Voltage Controlled Oscillators’ Proc CICC MAY 1995. Erich Hafner,” ‘The Effect of Noise in Oscillators’ Proc IEEE February 1966. N. M. Nguyen and R. G. Meyer,” A 1.8GHz monolithic LC voltage controlled oscillator, “IEEE J. Solid State Circuits, vol 27,pp.444-450,Mar-1992 J. Craninckx and M. Steyaert,” A 1.8GHz CO\MOS low phase noise voltage controlled oscillator with prescalar,” IEEE J.Solid State Circuits, vol. 30.pp.1474-1482,Dec 1995 B.Razavi,”A 1.8GHz CMOS voltage controlled oscillator,” in ISSCC Dig. Tech. Papers,1997,pp.388-389 Ali Hajimiri, ” Concepts and Methods in Optimization of Integrated LC VCOs,” IEEE Journal of Solid-State Ccircuits, vol. 36, No. 6, June 2001 IEEE Transactions on Microwave Theory and Technology Digital Achieve 1953-2000 MOSFET Theory and Design R.N.Warner,Jr and B.L.Grung Oxford University Press,1999 Hajimiri et. al, “Design Issues in CMOS Differential LC Oscillators”, JSSC, May 1999 and Feb, 2000 (pp 286-287) ‘RF CMOS Transceivers for Cellular Telephony’, Behzad Razavi, University of California, Topics In Circuits For Communications, IEEE Communications Magazine, August 2003 Voltage References and Biasing, 1993 Thomas H. Lee; rev. November 19, 2001 (Handout #20: EE214 Fall 2001) ‘Analysis and design of analog integrated circuits’ by Gray and Mayer, John Wiley Press,1996 MOSFET Theory and Design R.N.Warner,Jr and B.L.Grung Oxford University Press,1999
