A circuit design for a low-power full adder array-based multiplier in domino logic is proposed. It is based on the low-swing voltage technique. The output voltage ...
Low-Power Domino Logic Multiplier Using Low-Swing Technique A. Rjoub and 0. Koufopavlou VLSI Design Laboratory, Department of Electrical & Computer Engineering, University of Patras, 26500 Patras, Greece
tends to be a very attractive method performance, low-power designs.
ABSTRACT
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A circuit design for a low-power full adder array-based The potential of domino logic in designing low power circuits is investigated in this paper. As an example, the popular Braun multiplier is employed [8], which is based on a state transition diagram technique. In this paper, we introduce a new low power Braun multiplier implementation using domino logic, which is based on a low voltage swing technique.
multiplier in domino logic is proposed. It is based on the low-swing voltage technique. The output voltage swing of the domino gate is reduced, resulting in lower power dissipation and improvements in power-delay product. The proposed technique is general and can be used in all domino logic circuit designs. SPICE simulation results have shown that up to 40% power dissipation reduction could be achieved by using the proposed circuit design method.
The organization of this paper is as follows. In section 2 the basic structure of the domino logic is presented. The proposed low-power design technique for domino logic circuits is explained in section 3. The application of the a Braun multiplier proposed technique on implementation is described in section 4. The paper is concluded in section 5.
1. INTRODUCTION Multiplier play a significant role in high speed digital signal processing. It’s the most important part of the Arithmetic Logic Unit (ALU), FPU and ASIC’s where high processing speed is required. Currently, the importance of low power design increases rapidly due to the increasing demand for portable and mobile systems. Many different types of low power multipliers are proposed, and fabricated as benchmarks for demonstrating various high-speed technologies in many applications[ 1-31.
2. STRUCTURE OF THE DOMINO LOGIC GATES The basic structure of domino logic is shown in Fig. 1. It is a non-inverting structure, and consists of a nMOS transistor network, which implements the required logic function, two transistors (an nMOS and a PMOS) where the clock signal is applied and synchronizes the operation of the circuit, and a static CMOS inverter which provides the circuit’s output.
Low power design techniques require special attention to avoid significant increment of the circuit’s area or sacrifice in the speed performance of the systems. In CMOS technology power consumption can be reduced by decreasing the nodal capacitance, decreasing the power supply voltage or through architecture refinements, where the total power may be reduced by eliminating unnecessary transistors [4]. Dynamic logic and especially domino logic could play an important role in -the future integrated circuits. Domino logic circuits have many advantages such as high speed of operation, minimum used area, low noise margins, and the most important of all, they offer potential power consumption savings since the overall gate capacitance is smaller than their static counterparts [4-71. For this reason circuit design using domino logic
Structure
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Fig. 1: Conventional domino logic structure
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The period where CLK is low is called the precharge phase. In this phase the internal node, F ,is charged to power supply voltage while the output node, F, is discharged to ground. The period where CLK is high is called the evaluation phase. In this phase the values of the inputs determine the discharge (F = 0) or not (F = 1) of the internal node
3. LOW SWINGILOW POWER DOMINO LOGIC Dynamic power dissipation occurs during charging of the internal and the output nodes. Since the capacitance of the internal nodes is small, most of the dynamic power is consumed during the output node charging, especially when high fan-out is assumed. The energy drawn by a power supply voltage, Vdd, for charging a node capacitance, c , which swings from 0 to v,', is
The inverter in the output of a domino logic circuit is included for several reasons. First, it is required for proper operation of a chain of domino gates. Second, the internal node F is a weak node, when the clock is high, the high value on that node is not driven [5].
given by E= C, x V ,
xV,
The dynamic power Pd resulting from charging and discharging the capacitance in domino logic without considering the internal capacitance is given as
Arbitrary Boolean functions can be constructed from the pass-transistor network. As an example a domino logic full adder is shown in Fig.2. The domino logic full adder is compared with a conventional CMOS full adder [2]. The input capacitance is about half of the conventional CMOS design, thus achieving higher speed and lower powers dissipation.
where CL is the output capacitance driven by the output is the output inverter, Vdd is the supply voltage, VOUT voltage swing and f is the switching frequency. The proposed low power architecture for domino gates is based on a low-swing technique. The output inverter shown in Fig. 3 replaces the output inverter in the structure of the conventional domino gate.
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Fig. 2: Full Adder in Domino Logic
F n
Moreover, the powerful logic functionality of domino logic due to the multilevel pass-transistor network, realizes complex boolean functions efficiently with a small number of nMOS transistors, thus further reducing area and delay time. In fact the transistor count in the domino full adder is 21, whereas in conventional CMOS it is 28 [2]. The area required for domino logic full adder, is almost 213 of the corresponding conventional CMOS adder.
Fig. 3: A Low-PowerLow-Swing Domino Inverter An nMOS Transistor (MI) is inserted between the drain of the PMOS transistor and the output [9]. Applying a reference voltage, V,,, on the gate of M I , the voltage at its source, and therefore on the output node of the inverter, can not exceed the voltage value V,, -VTN, where VTNis the threshold voltage of the nMOS transistor. So, the voltage on the output node swings between the values 0 (for high input) and V,, - VTN(for low-input).
To compare the full-adder performance between domino and conventional CMOS, circuit simulations are performed using SPICE at a supply voltage of 3.3V. The simulated worst-case delay time was measured by using a SPICE submicron technology file, for the domino logic adder 0,30 ns while for conventional CMOS full adders 0,44 ns which proves the superiority of the domino logic speed comparing to the conventional CMOS logic.
A structure of nMOS transistors, connected as shown in Fig. 3, is used for the derivation of V,, Assuming a structure with n transistors, a reference voltage equal to
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v d d - nVTN is derived. In this way, a controlled voltage swing can be achieved. This leads to increase circuit design flexibility as a trade off between power consumption and propagation delay. In order to V , , to remain in the proper value, a capacitor with a value at least five times the value of the source and drain parasitic capacitance, is inserted to the circuit. This capacitance can be very easily produced in CMOS technology (gate capacitance of a transistor with proper size).
the last stage without the proposed low swing architecture, as the last carry of the last Full Adder. To show the characteristics improvement achieved by the proposed technique, a 4 x 4 bit multiplier has been implemented, by using both the conventional and the proposed domino logic. As an example, a 0.5pm CMOS technology with power supply voltage Vdd= 5 V , and threshold voltage VTN= 0.65V was used.
The proposed domino gate defines a valid family of logic as it can be used for the design of all logic circuits (Fig. 4). Putting in series such gates, the overall structure will operate properly if the condition Vdll- nVTN > VTN is valid. As the number n is increased the bias of the following gate will be reduced resulting in an increase in the propagation delay. However, an increase of n means increase in power savings.
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Fig. 5: Proposed Domino Logic Multiplier Simulation results have shown that for n = 2 the gate output voltages swing in the range of 0 - 2.92V, while for n = 3 in the range of 0 -2.25V. By these values, a direct and precise power consumption estimation can be derived. For the measurement of the power consumption, the power meter circuit proposed in [lo] has been used. Fig. 4: Proposed Low-Swing Domino Logic
In Fig. 6 the total power consumption of the proposed design normalized to the power consumption of the conventional domino for different number of the transistors in the nMOS structure, n, is presented. The significant advantages of the proposed low-swing domino gate in the context of the power dissipation are obvious. From Fig. 6, it can be observed that increasing n results in significant power consumption reduction. For example, the simulation results show that for n = 3, power saving is about 40%.
The energy dissipated by the proposed domino gate architecture for charging the output node from 0 to (Vdd- (Vre, - V T N ) ) becomes E = CL.XVdd x (Vdd - (VrpfVTN))Compared to the full swing case, a reduction in power dissipation of ((VrlT- V T N ) / Vdd) x 100 % is achieved.
4. MULTIPLIER ARCHITECTURE
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The Braun multiplier [SI is used for the comparison between the proposed low power domino logic with the conventional CMOS logic. In Fig. 5 the block diagram of the multiplier architecture is shown. Let 1 be the word length of multiplicand, and k be the word length of the multiplier. A full adder array based multiplier contains l x k AND gates and 1 x (k - I ) 1-bit full adders. To create full swing output voltage levels, we let the inverters of the sum of the Ripple Carry Adders in
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Fig.6: Normalized Power Consumption.
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5. CONCUSIONS
Using low-swing technique is much better than the reduction of the supply voltage in a circuit. In the first case the increase of the delay is due to the inverter where low-swing voltage is applied, while in the second case the additional delay time is due the delay of all the subcircuits.
In this paper a new low power domino logic has been proposed. This is based in a low voltage swing and leads to significant power savings for architectures which present high fan out requirements. The proposed lowswing technique can be applied in all domino structures and thus it is a valid approach for circuit design. Significant power savings can be achieved while a trade off between power and delay can be adjusted for meeting the circuit design specifications. This is achieved by the efficient way of the realization of the low-swing technique.
The total average propagation delay through the proposed multiplier normalized to the conventional domino logic one, for various values of n, is shown in Fig. 7. It is noted that an increase of n causes an increase in the propagation delay time, as it is expected.
REFERENCES G. E. Sobelman and D. L. Raatz, “Low-Power Multiplier Design Using Delayed Evaluation”, in Proc. of IEEE International Symposium on Circuits and Systems, pp. 1564-1567, 1995. N. Weste, and K. Eshraghian, “Principles of CMOS VLSI Design”, Addison-Weslet Publishing Company, 1992. J. H. Satyanarayana and K. K. Parhi, A Theoretical Approach to Estimation of Bounds on Power Consumption in Digital Multipliers”, IEEE Trans. on Circuits and Systems II, vol. 44, no. 6, pp. 473-481, June 1997. C. Farnsworth, D. A. Edwards and S.S. Sikand, Utilising Dynamic Logic for Low Power Consumption in Asynchronous Circuits”, in Proc. of lEEE ISARACS, Salt Lake City, Utah, USA, Nov. 1994. D. V. Campenhout, T. Mudge and K. Sakallah, “Timing Verification of Sequential Domino Circuits,” in Proc. of IEEE/ACM International Conference on Computer-Aided Design, pp. 127132, 1996 A. P. Chandrakasan, and R. W. Brodersen, “Low Power Digital CMOS Design,” Kluwer Academic Publishers, 1995. J. M. Rabaey, M. Pedram, “Low Power Design Methodologies”, Kluwer Academic Publishers, 1996. Kai Hwang, “Computer Architecture: Principles, Architectures and Design”, John Wiley & Sons, 1979. A. Rjoub, S. Nikolaidis, 0. Koufopavlou, T. Stouraitis, ‘‘ A new efficient low power Bus architecture”, in Proc. of lEEE International Symposium on Circuits and Systems, vol. III, pp. 1864-1867, 1997 [ 101Sung, MO Kang, “Accurate Simulation of Power Dissipation in VLSI Circuits”, IEEE J. Solid State Circuits, vol. SC-21, no. 5, pp.889-891, Oct. 1986. “
Fig.7: Normalized Delay Time.
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As a final measure of low power domino logic, the power-delay product can be used. In Fig. 8, the normalized power-delay product with respect to the power-delay product of the conventional domino architecture is shown. For all values of n (i.e., 1, 2, 3) and for various load capacitance there is an improvement (lower values) in the power-delay product which proves the broad validity of the proposed technique.
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Fig.8: Normalized Power-Delay Product Consumption.
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