ICSE2008 Proc. 2008, Johor Bahru Malaysia

Low-Power High-Tuning Range CMOS Ring Oscillator VCOs Mahdi Parvizi Student Member, IEEE, Amir Khodabakhsh Student Member, IEEE, A. Nabavi Member IEEE Department of Electrical Engineering Tarbiat Modares University Tehran, Iran Email: [email protected]

Abstract—This paper presents the design of two new ring oscillators based on differential and single-ended topologies using a 0.13µm 1P8M CMOS technology. The differential oscillator utilizes feed-forward technique and a new composite load with inductive impedance, reducing the delay per stage and widening the tuning range. The output frequency ranges from 0.5 to 9.5 GHz and the circuit consumes only 9mW. The simulation result of phase noise is -85.3dBc/Hz @ 1MHz offset from centre frequency. The singleended ring oscillator with inductive composite load oscillates from 6.3 to 13.9 GHz and consumes only 5.1 mW with phase noise of -81.5dBc/Hz @ 1MHz offset from centre frequency. Index Terms—CMOS ring oscillator VCO, composite load, High tuning range, Phase noise, Voltage controlled oscillator (VCO)

I.

INTRODUCTION

V

COs are one of the important blocks of data communication systems and have wide applications, from data modulating in transmitters to demodulation and clock recovery in receivers. A CMOS VCO can be built using ring structures, relaxation circuits, or an LC resonant circuit. Ring inverter-based oscillators have some advantages among the other oscillators that have made them a good choice for designers. Compared to other alternatives, especially the LC resonator-based oscillators, the ring oscillator is compact, as it doesn’t need on chip inductors [2]. Further, its tuning range can span orders of magnitude as the ring oscillator is tuned by current. Meanwhile, it is desirable to scale down the current consumption of the VCO proportional to frequency variations which can be reached using ring oscillators. However, ring

40

1-4244-2561-7/08/$20.00 ©2008 IEEE

oscillators suffer from low Q factor and consequently larger phase noise. Ring oscillators with differential delay stages exhibit greater immunity to supply disturbance and substrate induced noise than single delay stage ones. However, single-ended ring oscillators can reach higher frequency than differential ring oscillators. In recent years, several novel cells have been proposed to reduce the delay of each cell as [5] to reach higher frequencies. Nevertheless, achieving low-power consumption, high frequency, wide tuning ranges and good phase noise is a challenging task. In this paper, a new differential and single-ended ring oscillator with new composite load are proposed, resulting in relatively higher frequencies and wider tuning ranges. The reminder of the paper is organized as follows. In section II, the structure of proposed ring oscillators are introduced. In section III, phase noise analysis is reported. Simulation results and comparison with other ring oscillators are shown in section IV. Finally, conclusion is given in section V.

II.

PROPOSED RING OSCILLATORS

A. Differential 10GHz Ring Oscillator Design Fig. 1 shows the schematic of delay stage, in which the nMOS transistors M1 and M2 create the input pair for primary loop, while the pMOS transistors M3 and M6 form the input pair for secondary loop. The proposed differential ring oscillator uses composite load (M3&M7M6&M8) and feed-forward technique [5] to reduce the delay of each cell. M4 and M5 are utilized to control the frequency of operation by varying their gate voltage. Applying control voltage to pMOS transistors helps avoiding tail current control mode and increasing output

ICSE2008 Proc. 2008, Johor Bahru Malaysia

voltage swing and reducing 1/f noise. Furthermore, single control voltage relaxes the implementation of charge pumps and loop filters in the PLLs. The size of M4 and M5 determines the tuning range [5].

provided by basic inverter delay cell. Hence various techniques had been explored to reduce the smallest achievable delay per stage, one of which is the feed-forward or dual-delay paths technique [5]. Fig. 3 illustrates the block diagram of a three-stage ring oscillator using feedforward technique.

Fig. 3 Block diagram of the proposed differential ring oscillator with feed-forward technique Fig.1 Differential Delay cell used in proposed ring oscillator

The nMOS transistors M7 and M8 are used as a load besides M3 and M6 to create a composite load [9], showing inductive impedance at the drain of M3 and M6. This new load helps the cell to oscillate at higher frequency and reaches wider tuning ranges as will be shown in section IV. As shown in Fig. 2, considering the gate source capacitance of M3 we have:

The basic concept of feed-forward oscillator is to add a secondary feed-forward path to the loop to reduce the delay per stage compared to that of the single-loop oscillators. The bold lines seen in Fig. 3 represent the primary loop and the solid lines represent the secondary loop. The primary inputs of each stage are connected to the differential outputs of previous stage, and the secondary inputs of each stage are connected to the differential outputs of two preceding stages. Therefore the load transistors (M3 & M6) are turned on before the primary nMOS transistors (M1 & M2). This architecture allows using the minimum number of stages and reaching higher frequencies. B. Single-Ended 14 GHz ring oscillator Design

Fig. 2 Novel load used in proposed ring oscillator showing inductive impedance 1 VY = VX

SCGS 3 1 SCGS 3

+

1

=

gm 7 (λ = γ = 0) gm 7 + SCGS 3

(1)

gm 7

IX gm 7 gm 3 = VX gm 7 + SCGS 3

(2)

VX CGS 3 1 S = + IX gm 3 gm 3gm 7

(3)

and

Therefore, the impedance at the drain of M3 is always inductive. Its magnitude can be changed by varying the widths of M7 and M8. Feed-forward technique The frequency of a conventional single-loop ring oscillator is limited by the smallest delay

Fig. 4 shows the single-ended delay cell, in which M1 and M2 form the input pair and M3 works as a load to control the frequency of operation. In addition to M2, M4 acts as a composite load and the impedance seen from the drain of M2 is inductive as described in previous section. It helps reaching higher Q for oscillator and therefore better phase noise. Because of its simplicity and lower total capacitance, this architecture can reach higher frequencies. However, it suffers from common mode noises, supply disturbance and substrate induced noises. The size of M4 determines the tuning range of frequency. By avoiding tail current control in this architecture, higher frequencies and higher voltage swing is achieved. The block diagram of the single-ended ring oscillator is shown in Fig. 5. Given the technology, using minimum number 41

ICSE2008 Proc. 2008, Johor Bahru Malaysia

of transistors and minimum stages allows reaching highest possible frequency. The proposed ring oscillator can oscillate up to 13.9GHz.

where Weff = Wn + Wp

(6)

and µeff =

µnWn + µpWp

(7)

Wn + Wp

Where ∆V is the gate overdrive in the middle of transition, i.e., ∆V = (VDD/2) – VT [3]. During one cycle, each node of the oscillator is charged to qmax and then discharged to zero. Therefore, the total power dissipation is approximately given by (8) P = 2ηNVDD q max f0 Fig. 4 Single-ended delay cell used in proposed ring oscillator

where η is a proportional constant due to crowbar current, N is the number of stages, VDD is the power supply voltage, qmax is the maximum charge of the node, and f0 (= ω0/2π) is the nominal frequency of oscillation [3]. It is shown in [3] that the expressions for phase noise in single-ended CMOS ring oscillators is:

{ }

L ∆f ≈

Fig. 5 The block diagram of proposed single-ended VCO

III.

PHASE NOISE CALCULATION

As shown in [3], the phase noise of the oscillators is dominated by white noise. For CMOS transistor, the drain current noise spectral density is given by in2 ∆f

= 4kT γ gd 0 = 4kT γ µC ox

W ∆V L

(4)

where gd0 is the zero-bias drain source conductance, µ is the mobility, Cox is the gateoxide capacitance per unit area, K is Boltzmann constant, W and L are the channel width and length of the device, respectively, and ∆V is the gate overdrive. The coefficient γ is 2/3 for long channel devices in the saturation region and typically two or three times greater for short channel devices [4]. A. Single-Ended CMOS Ring Oscillators Assume a single-ended CMOS ring oscillator with equal length NMOS and PMOS transistors, and VTN = |VTP|. The maximum total channel noise from NMOS and PMOS devices, when both the input and output are at VDD/2, is given by Weff in2 = 4kT γ gd 0 = 4kT γ µeff Cox ∆V L ∆f

42

(5)

2 8 kT VDD f0 ⋅ ⋅ ⋅ 2 3η P Vchar ∆f

(9)

where Vchar is the characteristic voltage of the device. For the long channel devices it is defined as Vchar = ∆V/γ. For short channel devices Vchar = EC L/ γ, where EC is the critical electric field and is defined as the value of electric field resulting in half the carrier velocity expected from low field mobility. Any extra disturbance, such as substrate and supply noise, or noise contributed by extra circuitry or asymmetry in the waveform will result in a larger value than (9). Also the minimum available phase noise for a singleended ring oscillator, assuming that all symmetry criteria are met, occurs for zero threshold voltage [3] and it is

{ }

L ∆f >

16 kT f0 ⋅ ⋅ 3η P ∆f 2

(10)

Considering our single-ended ring oscillator structure, which has two PMOS and two NMOS transistors as shown in Fig. 4, channel noises of all devices are added together. Therefore, the maximum total channel phase noise from all devices is still the same as (5), but in Eq. (6) and Eq. (7) Wp and Wn multiplies by a factor of two. Other equations from Eq. (8) to Eq. (10) will be the same as simple structure, so Eq. (9) can be used for estimating the phase noise in our structure presented in Fig. 4 which is approximately -83dBc/Hz. B. Differential CMOS Ring Oscillators

ICSE2008 Proc. 2008, Johor Bahru Malaysia

in2 ∆f

= 4kTI tail

1 1 + V R I L tail char

(12)

Fig. 6 illustrates the tuning characteristics of proposed VCOs. Changing the control voltage between 0-0.8V, the frequency varies between 0.5-9.5 GHz (i.e., 180% tuning range) in differential VCO and between 6.3-13.9 GHz (i.e., 77% tuning range) in single-ended one. It shows linear characteristics and wide tuning range of oscillators. 14.00G Differential_freq_range

12.00G

Freqenc(Hz)

Consider a simple differential CMOS ring oscillator with resistive load. The total power dissipation is (11) P = NI tailVDD where N is the number of stages, Itail is the tail bias current of the differential pair, and VDD is the supply voltage. In these structures, tail noise in the vicinity of even harmonics can be significantly reduced by variety of means, such as with a series inductor or a parallel capacitor. Only mentioning noise of the differential transistors and the load, total current noise on each single-ended node can be written as [3]

V 8 kT VDD ⋅N ⋅ ⋅ + DD P Vchar RLI tail 3η

f2 ⋅ 0 2 ∆f

(13)

Note that, despite the single-ended ring oscillators, a differential ring oscillator exhibits a phase noise and jitter dependency on the number of stages. Given the frequency and power dissipation, the phase noise degrades as the number of stages increases. Considering our differential ring oscillator, shown in Fig. 1 and Fig. 3, three parallel transistors (two PMOS devices and one NMOS device) are used instead of a resistor in the simple resistive load differential ring oscillator. Therefore, Eq. (10) will remain true for our structure, but total current noise on each single-ended node and phase noise of this structure is given by in2 ∆f

=

16kTI tail

(14)

Vchar

f02 2

32 kT VDD (15) ⋅N ⋅ ⋅ ⋅ 3η P Vchar ∆f respectively, considering equal length NMOS and PMOS, and VTN = |VTP|. Using Eq. (15), phase noise is approximately -87.5dBc/Hz for our structure.

{ }

Lmin ∆f =

IV.

SIMULATION RESULTS AND PERFORMANCE COMPARISON

The proposed ring oscillators are simulated using ADS in a 0.13µm 1P8M CMOS technology. The width of M7 and M8 in Differential oscillator is set to minimum feature size to have the most inductive effect and the other widths are changed to reach the optimum results.

8.000G 6.000G 4.000G

0.0000 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Control Voltage (V)

Fig. 6 Frequency sweep with control voltage in differential oscillator

The differential circuit draws 11mA and 4mA from 1.2V supply when running at highest and lowest frequency, respectively. The phase noise is calculated using harmonic balance simulation. It shows a phase noise of -85.3dBc/Hz @1MHz offset from centre frequency, which is very close to -87dBc that was calculated in our phase noise analysis. Single-ended VCO draws 7mA and 1.5mA from 1.2V supply when running at the highest and the lowest frequency, respectively. The phase noise is -81.5dBc @ 1MHz offset from 10 GHz centre frequency, which is close to -83dBc that was calculated in our phase noise analysis. Fig. 7 shows the simulation results. Phase Noise (dBc/Hz)

{ }

10.00G

2.000G

where RL is the load resistor. The phase noise for differential CMOS ring oscillator is [3]: Lmin ∆f =

Single_ended_Freq_range

-50 Differential_Pahse_noise

-60

Single_ended_phase_noise

-70 -80 -90 -100 -110 100.0k

1.000M 5M Frequency (Hz) Fig. 7 Phase noise simulation of differential ring oscillator

As single-end VCO oscillates at higher frequencies it shows poorer phase noise characteristics. Simulations show good frequency stability against temperature and power supply variations. The circuit is tested under 10% power 43

ICSE2008 Proc. 2008, Johor Bahru Malaysia

supply variations and 0-80˚C changes. Fig. 8 shows the results.

temperature

15.50G 15.00G Vdd=1.300

14.00G

Frequency (Hz)

Vdd=1.200

13.00G Vdd=1.100

12.00G

tuning range from center frequency f0 (%), and Pdc is the measured power in mW. Clearly, the proposed ring oscillators have higher frequencies and wider tuning ranges, while consuming lower power. These better characteristics stem from using new composite load along with feed-forward technique and the finer feature size of 0.13-µm CMOS technology.

11.00G

V.

10.00G

CONCLUSION

Vdd=1.300

9.000G

Vdd=1.200 Vdd=1.100

8.000G 0

10

20

30

40

50

60

70

80

(C) Fig. 8 Power supply andTempreture temperature variation effects

Some other reported ring oscillators data are listed in Table 1 for performance comparison. The VCO performance may also be evaluated using the following figure of merit (FOM) equation:

FOM = − L{∆f } + 20 log( f 0 / ∆f )

(13)

+ 10 log(T .R.) − 10 log( Pdc / 1mw) Where L{∆f } is the phase noise at ∆f offset frequency from centre frequency f0, T.R. is the

In this paper, two new ring oscillators are proposed based on differential and single-ended topology. The differential ring oscillator illustrates 180% tuning range @ 5GHz. It utilizes feed-forward technique and a novel composite load, generating inductive impedance to reduce the delay of each stage. The phase noise of the circuit is -85.3dBc/Hz@1MHz offset from centre frequency, and consumes only 9mW. The singleended ring oscillator, with the same inductive composite load, oscillates up to 14GHz with merely 5.1mW power consumption. The phase noise of the circuit is -81.5dBc/Hz @1MHz offset from centre frequency of 10GHz.

Table I. Performance comparison with prior state-of-art published works Parameter Center Freq.(GHz) Tuning range Phase noise @1MHz(-dBc/Hz) Technology Power Dissipation(mW) FOM(dBc/Hz)

VI.

Proposed differential 5

Proposed single-ended 10.1

[5]

[6]

[7]

[8]

9.2

3.6

5

5.5

180% 85.3

77% 81.5

18% 99.9

74% 90.1

130% 82

14% 99.2

CMOS 0.13µm 9

CMOS 0.13µm

CMOS 0.18µm

CMOS 0.18µm

CMOS 0.18µm

CMOS 0.25µm

5.1

50

17

135

80

172.3

173.4

174.7

167.6

155.2

166

REFERENCES

[1] Asad A. Abidi, "Phase Noise and Jitter in CMOS Ring Oscillators", IEEE J. Solid-State Circuits, Vol. 41, No. 8, pp. 1083-1816, Aug. 2006 [2] Liang Dai, and Ramesh Harjani, "Design of LowPhase-Noise CMOS Ring Oscillators", IEEE Trans. on Circuits and Syst. II, Vol. 49, No. 5, pp. 328-338, May 2002 [3] Ali Hajimiri, Sotirios Limotyrakis, and Thomas H. Lee, "Jitter and Phase Noise in Ring Oscillators", IEEE J. Solid-State Circuits, Vol. 34, No. 6, pp. 790804, Jun. 1999 [4] A. A. Abidi, "High-frequency Noise Measurement of FET's with Small Dimentions", IEEE Trans. Electron Device, Vol. ED-33, pp. 1801-1805, Nov. 1986 [5] Hai Qi Liu, Wang Ling Goh and Liter Siek," A 0.18-µm 10-GHz CMOS Ring Oscillator for Optical 44

Transceivers," in IEEE Int. Symposium on Circuits and Systems, Vol. 2, pp. 1525 - 1528, May 2005 [6] Wei-Hsuan Tu, Jyh-Yih Yeh, Hung-Chieh and Tsai Chorng-Kuang Wang “A 1.8V 2.5-5.2 GHz CMOS Dual-input Two-stage Ring VCO,” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp. 134-137 Aug. ,2004 [7] Afshin Rezayee and Ken Martin, “A Coupled Two-Stage Ring Oscillator,” IEEE Symposium on systems and circuits, Vol. 2, pp. 878 – 881, Aug. 2001 [8] Y. A. Eken and J. P. Uyemura, “A 5.9-GHz voltage-controlled ring oscillator in 0.18-µm CMOS,” IEEE J. Solid-State Circuits, Vol.39, No. 1, pp. 230233, Jan. 2004. [9] B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw-Hill, 2001

Low-Power High-Tuning Range CMOS Ring Oscillator VCOs Mahdi Parvizi Student Member, IEEE, Amir Khodabakhsh Student Member, IEEE, A. Nabavi Member IEEE Department of Electrical Engineering Tarbiat Modares University Tehran, Iran Email: [email protected]

Abstract—This paper presents the design of two new ring oscillators based on differential and single-ended topologies using a 0.13µm 1P8M CMOS technology. The differential oscillator utilizes feed-forward technique and a new composite load with inductive impedance, reducing the delay per stage and widening the tuning range. The output frequency ranges from 0.5 to 9.5 GHz and the circuit consumes only 9mW. The simulation result of phase noise is -85.3dBc/Hz @ 1MHz offset from centre frequency. The singleended ring oscillator with inductive composite load oscillates from 6.3 to 13.9 GHz and consumes only 5.1 mW with phase noise of -81.5dBc/Hz @ 1MHz offset from centre frequency. Index Terms—CMOS ring oscillator VCO, composite load, High tuning range, Phase noise, Voltage controlled oscillator (VCO)

I.

INTRODUCTION

V

COs are one of the important blocks of data communication systems and have wide applications, from data modulating in transmitters to demodulation and clock recovery in receivers. A CMOS VCO can be built using ring structures, relaxation circuits, or an LC resonant circuit. Ring inverter-based oscillators have some advantages among the other oscillators that have made them a good choice for designers. Compared to other alternatives, especially the LC resonator-based oscillators, the ring oscillator is compact, as it doesn’t need on chip inductors [2]. Further, its tuning range can span orders of magnitude as the ring oscillator is tuned by current. Meanwhile, it is desirable to scale down the current consumption of the VCO proportional to frequency variations which can be reached using ring oscillators. However, ring

40

1-4244-2561-7/08/$20.00 ©2008 IEEE

oscillators suffer from low Q factor and consequently larger phase noise. Ring oscillators with differential delay stages exhibit greater immunity to supply disturbance and substrate induced noise than single delay stage ones. However, single-ended ring oscillators can reach higher frequency than differential ring oscillators. In recent years, several novel cells have been proposed to reduce the delay of each cell as [5] to reach higher frequencies. Nevertheless, achieving low-power consumption, high frequency, wide tuning ranges and good phase noise is a challenging task. In this paper, a new differential and single-ended ring oscillator with new composite load are proposed, resulting in relatively higher frequencies and wider tuning ranges. The reminder of the paper is organized as follows. In section II, the structure of proposed ring oscillators are introduced. In section III, phase noise analysis is reported. Simulation results and comparison with other ring oscillators are shown in section IV. Finally, conclusion is given in section V.

II.

PROPOSED RING OSCILLATORS

A. Differential 10GHz Ring Oscillator Design Fig. 1 shows the schematic of delay stage, in which the nMOS transistors M1 and M2 create the input pair for primary loop, while the pMOS transistors M3 and M6 form the input pair for secondary loop. The proposed differential ring oscillator uses composite load (M3&M7M6&M8) and feed-forward technique [5] to reduce the delay of each cell. M4 and M5 are utilized to control the frequency of operation by varying their gate voltage. Applying control voltage to pMOS transistors helps avoiding tail current control mode and increasing output

ICSE2008 Proc. 2008, Johor Bahru Malaysia

voltage swing and reducing 1/f noise. Furthermore, single control voltage relaxes the implementation of charge pumps and loop filters in the PLLs. The size of M4 and M5 determines the tuning range [5].

provided by basic inverter delay cell. Hence various techniques had been explored to reduce the smallest achievable delay per stage, one of which is the feed-forward or dual-delay paths technique [5]. Fig. 3 illustrates the block diagram of a three-stage ring oscillator using feedforward technique.

Fig. 3 Block diagram of the proposed differential ring oscillator with feed-forward technique Fig.1 Differential Delay cell used in proposed ring oscillator

The nMOS transistors M7 and M8 are used as a load besides M3 and M6 to create a composite load [9], showing inductive impedance at the drain of M3 and M6. This new load helps the cell to oscillate at higher frequency and reaches wider tuning ranges as will be shown in section IV. As shown in Fig. 2, considering the gate source capacitance of M3 we have:

The basic concept of feed-forward oscillator is to add a secondary feed-forward path to the loop to reduce the delay per stage compared to that of the single-loop oscillators. The bold lines seen in Fig. 3 represent the primary loop and the solid lines represent the secondary loop. The primary inputs of each stage are connected to the differential outputs of previous stage, and the secondary inputs of each stage are connected to the differential outputs of two preceding stages. Therefore the load transistors (M3 & M6) are turned on before the primary nMOS transistors (M1 & M2). This architecture allows using the minimum number of stages and reaching higher frequencies. B. Single-Ended 14 GHz ring oscillator Design

Fig. 2 Novel load used in proposed ring oscillator showing inductive impedance 1 VY = VX

SCGS 3 1 SCGS 3

+

1

=

gm 7 (λ = γ = 0) gm 7 + SCGS 3

(1)

gm 7

IX gm 7 gm 3 = VX gm 7 + SCGS 3

(2)

VX CGS 3 1 S = + IX gm 3 gm 3gm 7

(3)

and

Therefore, the impedance at the drain of M3 is always inductive. Its magnitude can be changed by varying the widths of M7 and M8. Feed-forward technique The frequency of a conventional single-loop ring oscillator is limited by the smallest delay

Fig. 4 shows the single-ended delay cell, in which M1 and M2 form the input pair and M3 works as a load to control the frequency of operation. In addition to M2, M4 acts as a composite load and the impedance seen from the drain of M2 is inductive as described in previous section. It helps reaching higher Q for oscillator and therefore better phase noise. Because of its simplicity and lower total capacitance, this architecture can reach higher frequencies. However, it suffers from common mode noises, supply disturbance and substrate induced noises. The size of M4 determines the tuning range of frequency. By avoiding tail current control in this architecture, higher frequencies and higher voltage swing is achieved. The block diagram of the single-ended ring oscillator is shown in Fig. 5. Given the technology, using minimum number 41

ICSE2008 Proc. 2008, Johor Bahru Malaysia

of transistors and minimum stages allows reaching highest possible frequency. The proposed ring oscillator can oscillate up to 13.9GHz.

where Weff = Wn + Wp

(6)

and µeff =

µnWn + µpWp

(7)

Wn + Wp

Where ∆V is the gate overdrive in the middle of transition, i.e., ∆V = (VDD/2) – VT [3]. During one cycle, each node of the oscillator is charged to qmax and then discharged to zero. Therefore, the total power dissipation is approximately given by (8) P = 2ηNVDD q max f0 Fig. 4 Single-ended delay cell used in proposed ring oscillator

where η is a proportional constant due to crowbar current, N is the number of stages, VDD is the power supply voltage, qmax is the maximum charge of the node, and f0 (= ω0/2π) is the nominal frequency of oscillation [3]. It is shown in [3] that the expressions for phase noise in single-ended CMOS ring oscillators is:

{ }

L ∆f ≈

Fig. 5 The block diagram of proposed single-ended VCO

III.

PHASE NOISE CALCULATION

As shown in [3], the phase noise of the oscillators is dominated by white noise. For CMOS transistor, the drain current noise spectral density is given by in2 ∆f

= 4kT γ gd 0 = 4kT γ µC ox

W ∆V L

(4)

where gd0 is the zero-bias drain source conductance, µ is the mobility, Cox is the gateoxide capacitance per unit area, K is Boltzmann constant, W and L are the channel width and length of the device, respectively, and ∆V is the gate overdrive. The coefficient γ is 2/3 for long channel devices in the saturation region and typically two or three times greater for short channel devices [4]. A. Single-Ended CMOS Ring Oscillators Assume a single-ended CMOS ring oscillator with equal length NMOS and PMOS transistors, and VTN = |VTP|. The maximum total channel noise from NMOS and PMOS devices, when both the input and output are at VDD/2, is given by Weff in2 = 4kT γ gd 0 = 4kT γ µeff Cox ∆V L ∆f

42

(5)

2 8 kT VDD f0 ⋅ ⋅ ⋅ 2 3η P Vchar ∆f

(9)

where Vchar is the characteristic voltage of the device. For the long channel devices it is defined as Vchar = ∆V/γ. For short channel devices Vchar = EC L/ γ, where EC is the critical electric field and is defined as the value of electric field resulting in half the carrier velocity expected from low field mobility. Any extra disturbance, such as substrate and supply noise, or noise contributed by extra circuitry or asymmetry in the waveform will result in a larger value than (9). Also the minimum available phase noise for a singleended ring oscillator, assuming that all symmetry criteria are met, occurs for zero threshold voltage [3] and it is

{ }

L ∆f >

16 kT f0 ⋅ ⋅ 3η P ∆f 2

(10)

Considering our single-ended ring oscillator structure, which has two PMOS and two NMOS transistors as shown in Fig. 4, channel noises of all devices are added together. Therefore, the maximum total channel phase noise from all devices is still the same as (5), but in Eq. (6) and Eq. (7) Wp and Wn multiplies by a factor of two. Other equations from Eq. (8) to Eq. (10) will be the same as simple structure, so Eq. (9) can be used for estimating the phase noise in our structure presented in Fig. 4 which is approximately -83dBc/Hz. B. Differential CMOS Ring Oscillators

ICSE2008 Proc. 2008, Johor Bahru Malaysia

in2 ∆f

= 4kTI tail

1 1 + V R I L tail char

(12)

Fig. 6 illustrates the tuning characteristics of proposed VCOs. Changing the control voltage between 0-0.8V, the frequency varies between 0.5-9.5 GHz (i.e., 180% tuning range) in differential VCO and between 6.3-13.9 GHz (i.e., 77% tuning range) in single-ended one. It shows linear characteristics and wide tuning range of oscillators. 14.00G Differential_freq_range

12.00G

Freqenc(Hz)

Consider a simple differential CMOS ring oscillator with resistive load. The total power dissipation is (11) P = NI tailVDD where N is the number of stages, Itail is the tail bias current of the differential pair, and VDD is the supply voltage. In these structures, tail noise in the vicinity of even harmonics can be significantly reduced by variety of means, such as with a series inductor or a parallel capacitor. Only mentioning noise of the differential transistors and the load, total current noise on each single-ended node can be written as [3]

V 8 kT VDD ⋅N ⋅ ⋅ + DD P Vchar RLI tail 3η

f2 ⋅ 0 2 ∆f

(13)

Note that, despite the single-ended ring oscillators, a differential ring oscillator exhibits a phase noise and jitter dependency on the number of stages. Given the frequency and power dissipation, the phase noise degrades as the number of stages increases. Considering our differential ring oscillator, shown in Fig. 1 and Fig. 3, three parallel transistors (two PMOS devices and one NMOS device) are used instead of a resistor in the simple resistive load differential ring oscillator. Therefore, Eq. (10) will remain true for our structure, but total current noise on each single-ended node and phase noise of this structure is given by in2 ∆f

=

16kTI tail

(14)

Vchar

f02 2

32 kT VDD (15) ⋅N ⋅ ⋅ ⋅ 3η P Vchar ∆f respectively, considering equal length NMOS and PMOS, and VTN = |VTP|. Using Eq. (15), phase noise is approximately -87.5dBc/Hz for our structure.

{ }

Lmin ∆f =

IV.

SIMULATION RESULTS AND PERFORMANCE COMPARISON

The proposed ring oscillators are simulated using ADS in a 0.13µm 1P8M CMOS technology. The width of M7 and M8 in Differential oscillator is set to minimum feature size to have the most inductive effect and the other widths are changed to reach the optimum results.

8.000G 6.000G 4.000G

0.0000 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Control Voltage (V)

Fig. 6 Frequency sweep with control voltage in differential oscillator

The differential circuit draws 11mA and 4mA from 1.2V supply when running at highest and lowest frequency, respectively. The phase noise is calculated using harmonic balance simulation. It shows a phase noise of -85.3dBc/Hz @1MHz offset from centre frequency, which is very close to -87dBc that was calculated in our phase noise analysis. Single-ended VCO draws 7mA and 1.5mA from 1.2V supply when running at the highest and the lowest frequency, respectively. The phase noise is -81.5dBc @ 1MHz offset from 10 GHz centre frequency, which is close to -83dBc that was calculated in our phase noise analysis. Fig. 7 shows the simulation results. Phase Noise (dBc/Hz)

{ }

10.00G

2.000G

where RL is the load resistor. The phase noise for differential CMOS ring oscillator is [3]: Lmin ∆f =

Single_ended_Freq_range

-50 Differential_Pahse_noise

-60

Single_ended_phase_noise

-70 -80 -90 -100 -110 100.0k

1.000M 5M Frequency (Hz) Fig. 7 Phase noise simulation of differential ring oscillator

As single-end VCO oscillates at higher frequencies it shows poorer phase noise characteristics. Simulations show good frequency stability against temperature and power supply variations. The circuit is tested under 10% power 43

ICSE2008 Proc. 2008, Johor Bahru Malaysia

supply variations and 0-80˚C changes. Fig. 8 shows the results.

temperature

15.50G 15.00G Vdd=1.300

14.00G

Frequency (Hz)

Vdd=1.200

13.00G Vdd=1.100

12.00G

tuning range from center frequency f0 (%), and Pdc is the measured power in mW. Clearly, the proposed ring oscillators have higher frequencies and wider tuning ranges, while consuming lower power. These better characteristics stem from using new composite load along with feed-forward technique and the finer feature size of 0.13-µm CMOS technology.

11.00G

V.

10.00G

CONCLUSION

Vdd=1.300

9.000G

Vdd=1.200 Vdd=1.100

8.000G 0

10

20

30

40

50

60

70

80

(C) Fig. 8 Power supply andTempreture temperature variation effects

Some other reported ring oscillators data are listed in Table 1 for performance comparison. The VCO performance may also be evaluated using the following figure of merit (FOM) equation:

FOM = − L{∆f } + 20 log( f 0 / ∆f )

(13)

+ 10 log(T .R.) − 10 log( Pdc / 1mw) Where L{∆f } is the phase noise at ∆f offset frequency from centre frequency f0, T.R. is the

In this paper, two new ring oscillators are proposed based on differential and single-ended topology. The differential ring oscillator illustrates 180% tuning range @ 5GHz. It utilizes feed-forward technique and a novel composite load, generating inductive impedance to reduce the delay of each stage. The phase noise of the circuit is -85.3dBc/Hz@1MHz offset from centre frequency, and consumes only 9mW. The singleended ring oscillator, with the same inductive composite load, oscillates up to 14GHz with merely 5.1mW power consumption. The phase noise of the circuit is -81.5dBc/Hz @1MHz offset from centre frequency of 10GHz.

Table I. Performance comparison with prior state-of-art published works Parameter Center Freq.(GHz) Tuning range Phase noise @1MHz(-dBc/Hz) Technology Power Dissipation(mW) FOM(dBc/Hz)

VI.

Proposed differential 5

Proposed single-ended 10.1

[5]

[6]

[7]

[8]

9.2

3.6

5

5.5

180% 85.3

77% 81.5

18% 99.9

74% 90.1

130% 82

14% 99.2

CMOS 0.13µm 9

CMOS 0.13µm

CMOS 0.18µm

CMOS 0.18µm

CMOS 0.18µm

CMOS 0.25µm

5.1

50

17

135

80

172.3

173.4

174.7

167.6

155.2

166

REFERENCES

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Transceivers," in IEEE Int. Symposium on Circuits and Systems, Vol. 2, pp. 1525 - 1528, May 2005 [6] Wei-Hsuan Tu, Jyh-Yih Yeh, Hung-Chieh and Tsai Chorng-Kuang Wang “A 1.8V 2.5-5.2 GHz CMOS Dual-input Two-stage Ring VCO,” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp. 134-137 Aug. ,2004 [7] Afshin Rezayee and Ken Martin, “A Coupled Two-Stage Ring Oscillator,” IEEE Symposium on systems and circuits, Vol. 2, pp. 878 – 881, Aug. 2001 [8] Y. A. Eken and J. P. Uyemura, “A 5.9-GHz voltage-controlled ring oscillator in 0.18-µm CMOS,” IEEE J. Solid-State Circuits, Vol.39, No. 1, pp. 230233, Jan. 2004. [9] B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw-Hill, 2001