Low Power Modified Feed-Through Logic Circuit for Ultra ... - IJETAE

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013)

Low Power Modified Feed-Through Logic Circuit for Ultra-low Voltage Arithmetic Circuits Laxmiprava Samal1, Prof. Tejaswini R Choudri2 1

2

RKDF Institute of Science &Technology, Bhopal Deptt. of Electronics & Communication, RKDF Institute of Science & Technology, Bhopal

Abstract— A modified approach for Feed-Through logic (FTL) is developed in this paper to provide optimized power delay product (PDP). The need for faster circuits with low power dissipation has made it common practice to use feed through logic. Problems associated with domino logic like limitation of non-inverting only logic, charge sharing and the need of output inverter are eliminated. FTL performs a partial evaluation in a computational block before its input signals reach a valid level, and performs a quick final evaluation as soon as the inputs arrive, leading to a reduction in the delay. The FTL is well suited to arithmetic circuits where the critical path consists of a large number of gates. It is examined against proposed modified approach, by analysis through computer simulation. It is shown that the modified LPHS-FTL has low power consumption and high speed over existing FTL. The proposed circuit is simulated using 0.18μm, 1.8V CMOS process technology. Based on the performance the given approach is found very efficient for ultra-low voltage arithmetic circuits. Investigation suggests that the given approach has improved power delay product over the existing FTL.

Circuits having long logic depth need to have better speed and low power dissipation for which a new logic family called feedthrough logic (FTL) is proposed in [5]. This logic works on domino concept along with the important feature that output is evaluated before all the inputs are valid. This feature results in very fast evaluation in computational block. The problems associated with domino logic [6] circuits like charge sharing, charge leakage and non-inverting logic are completely eliminated. FTL has numerous applications like direct cascading of dynamic CMOS, to produce differential output, to design iterative networks. This paper presents a modified approach in high-speed FTL in [1] which results in reduced power consumption as compared to the conventional design. The total power dissipated in a generic digital CMOS gate is given by

Keywords— Dynamic Logic Circuit, Feed-Through Logic (FTL), Modified Feed-Through Logic, Low Power, Power Delay Product (PDP).

Where Fclk denotes the system clock frequency, Viswing is the voltage swing at node i, Ciload is the load capacitance at node i, αi the activity factor at node i, Iisc is the short circuit current and is the leakage current. This paper is organized as follows: Section II briefly describe the principle of operation for FTL. In Section III proposed modified FTL is presented, Section IV gives conclusion and Section V describes future prospect.

Ptotal = Pstatic + Pdynamic + Pshort-circuit........…. (1.1) Ptotal = VddIl+ VddFckl ∑i Viswing Ciload αi+ Vdd ∑i Iisc……. (1.2)

I. INTRODUCTION In the past major concern in VLSI design was area, performance, cost and reliability; power consideration was mostly of secondary importance. In recent years, this has begun to change increasingly; power is being given comparable weight to area and speed consideration. Though the static CMOS logic offers less speed, it is best known for its lowest power dissipation. As the number of inputs increase, the number of transistors required will be doubled. Dynamic logic is well suited for high speed circuit design and requires less number of transistors to implement a given logic, but the major drawback with this logic is, its excessive power dissipation due to the switching activity and clock. Excessive power dissipation of dynamic logic circuit is reduced with a mix of dynamic and static circuit styles [2], use of dual supply voltages [3] and dual threshold voltage (VT) [4] that have been proposed.

II. CONVENTIONAL FEED THROUGH LOGIC (FTL) Feedthrough logic is shown in fig.1.1. This logic circuit consists of a PMOS load transistor Mp and an NMOS reset transistor Mr and an NMOS block in which inputs are applied. The gates of Mp & Mr are connected to CLK. When CLK =1(reset phase), Mp is OFF and Mr is ON and the output is reset to logic low. Now when CLK =0(evaluation phase), Mp is ON and is OFF and the output either goes to logic level high or remains at low logic according to the inputs applied to the NMOS block. So in this output can either go from 0 to 1 or remain at 0 level according to the applied inputs. 440

International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013)

Fig.2.1 Modified low power FTL [1]structure (LP-FTL) Fig.1.1 Feedthrough Logic[1]

B. Modified HS-FTL [1] In order to improve the speed of proposed LP-FTL [1] structure the reset transistor Mr is connected to VDD/2 as shown in Fig. 2.2. The operation of this circuit is as follows, when CLK =1, the output node (OUT) will charges to the threshold voltage VTH. During evaluation phase according to input value the output node only makes partial transition from VTH to VOH or VOL. Since during evaluation phase the output node (OUT) only makes partial transitions, this improves propagation delay.

A long chain of inverter designed by using FTL is shown in Fig. 1.2.

Fig.1.2 Transistor level circuit diagram for long chain of inverter using FTL [1](5-stages)

A. Modified LP-FTL [1] The proposed modified circuit is shown in Fig. 2.1. Here one additional PMOS transistor MP2 in series with MP1. The operation of this circuit is similar to that of FTL in [1]. During reset phase i.e. when CLK=1, output node is pulled to GND through Mr. During evaluation phase i.e. CLK=0, output node charges through Mp1 and Mp2. Mr is turned off and the output node conditionally evaluates to V OH or VOL depending upon input to NMOS block. If the NMOS block evaluates to high then output node pulled toward V DD i.e. VOH =VDD, otherwise it remain at logic low i.e. VOL. Since Mp1 and Mp2 are in series, it further reduces leakage through M1 transistor and hence it helps in reducing VOL which is less than the VOL of existing FTL. This reduces dynamic power consumption but due to the insertion of PMOS transistor Mp2 propagation delay of the proposed LP-FTL in Fig. 2.1 increases.

Fig.2.2 Modified high speed FTL[1] structure (HS-FTL)

Fig.2.3 Inverter using Modified HS-FTL [1] structure

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013) III. PROPOSED APPROACH A. Proposed Low-power-High-Speed Structure The proposed modified circuit is shown in Fig. 3.1. It consists of the same pull-up network as that of HS-FTL in [1]. In order to minimize power delay product, an additional NMOS transistor Mr2 and a PMOS transistor Mp3 is added to the PDN of HS-FTL in [1].The gate of Mr2 is driven by CLK as Vgs and Mp3 is at GND. In this approach, it mitigates the short circuit current in the precharge phase. Because in precharge condition there is rippling which causes static current leakage through the input (NMOS). The role of additional transistor Mr2 is to increase the dynamic resistance of PDN. Due to which the output node discharges up to VOL value greater than the VOL of FTL [1]. The trade of in VOL results for less HIGH to LOW propagation delay from VTH to VOL. Also the PMOS (Mp3) is always ON providing low resistance path for easy discharge of output node voltage during evaluation phase. In addition to the reduced delay in modified FTL, power consumption also reduces because of increased value of VOL. The dynamic power consumption of a digital circuit is given by

Fig.3.2 Schematic of proposed modified LPHS- FTL inverter.

Pdynamic = Vdd Fclk ∑i Viswing Ciload αi…….…. (3.1) Where Fclk denotes the system clock frequency, Viswing is the voltage swing at node i, Ciload is the load capacitance at node i, αi the activity factor at node i. Increased value of VOL reduces Viswing in modified FTL. Therefore, modified FTL has lower power consumption than in FTL.

Fig.3.3 Waveform for proposed modified LPHS-FTL inverter.

B. Design of long chain of inverter A long chain of inverter (5-stages) designed by using the proposed structure in Fig.3.1. Fig 3.2 shows the schematic of single stage inverter.Fig.3.3 shows the simulated waveform of single stage inverter. The circuit is simulated using 180nm CMOS process technology. Power supply is 1.8V for all simulation. Circuits are drawn using Tanner Sedit. Net list obtained from T-spice for the schematic circuit are used with 180nm technology model files to simulate on TSPICE simulator. C. Simulation Results In performance analysis of modified FTL against FTL, we have used 180 nm CMOS process technology, using the parameters for typical process corner at 250C. Power supply VDD is taken 1.8 V throughout the simulations. Circuits are simulated using Tanner EDA tool. In this section the performance of inverters based on both approaches is compared.

Fig.3.1 Modified proposed LPHS-FTL for PDP Optimization

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International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 12, December 2013) The FTL and modified FTL inverters are shown in Figure 2.3 and Figure 3.2 respectively. 20fF capacitive load is taken in the analysis. The values obtained for various performance metrics like propagation delay, power dissipation and power delay product (PDP) are summarized in Table I.

IV. CONCLUSION In the era of high speed digital circuits FTL gives advantage of smaller power consumption compared to any other logic families in literature. In this paper we proposed a 5-stage inverter using Modified LPHS-FTL structure based on partial evaluation concept. It dissipates less power. According to the result in Tables I & II, Modified FTL is suitable for low power arithmetic, pipelining and filter circuit design over FTL. Modified LPHS-FTL also has lesser delay, reduced power consumption and improved PDP. Though it improves the performance of a circuit, it is achieved at the cost of increased number of transistors in reset block.

Table I Performance Comparison of Simulation Results for single stage FTL and Modified LPHS-FTL Inverter

2.9

Power (µw) 313.19

PDP (ns*µw) 908.25

2.5

238.94

597.35

2.3

67.22

154.60

Logic

Delay (ns)

FTL HS-FTL [1] Modified LPHS-FTL

Fig.3.5 Power dissipation Vs logic styles for 5-Stage Inverter Chain Fig.3.4 Power delay product Vs logic styles for single stage inverter

V. FUTURE PROSPECT

Table II Comparison of simulation results for 5-Stage inverter of FTL and Proposed Modified LPHS-FTL

Logic

Power (µw)

FTL

2608

HS-FTL

3631.96

Modified LPHS-FTL

1250.27

The advent of a mobile computing era has become a major motivation for low power design because the operation time of a mobile device is heavily restricted by its battery life. The growing complexity of mobile devices, such as a cell phone with a digital camera or a personal digital assistant (PDA) with global positioning system (GPS) makes the power problem more challenging. REFERENCES [1]

Table I and Table II shows the average dynamic power dissipation and propagation delay comparison among the high speed logic styles with the proposed modified structure of FTL for a chain of 5-inverter stages at 20fF capacitive load.

[2]

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