Josephson junctions and dc SQUIDs based on these junctions. The first junctions and SQUIDs showed non- hysteretic behavior at 4.2 K caused by the A1 ...
J. Phys. ZVFrance 12 (2002) 0EDP Sciences, Les Ulis
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DOI: 10.105 l/jp420020052
Low-T, ramp-type Josephson junctions for SQUIDS M. Podt, B.G.A. Rolink, J. Flokstra and H. Rogalla Low Temperature Division, Department of Applied Physics, University of Twente, P.O.Box 21 7, 7500 Enschede, The Netherlands
Abstract: The Josephson tunnel junction is the basic element of a superconducting quantum interference device (SQUID). Amongst other parameters, the junction capacitance determines the characteristics of a (digital) SQUID. In a conventional dc SQUID, reducing the junction capacitance decreases the flux noise of the sensor, whereas in digital SQUIDs, the operating frequency can be increased when reducing the junction capacitance. For digital SQUIDs, this means that not only the flux noise decreases, but also the flux slew rate increases. Slew rates up to lo8 @ds can be achieved by reducing the junction size to the sub-pm2 level. Using a ramp-type structure allows sub-pm2 Josephson junctions sizes using standard lithography. In this paper we present the first results on low-T, ramp-type Josephson junctions and dc SQUIDs based on these junctions. The first junctions and SQUIDs showed nonhysteretic behavior at 4.2 K caused by the A1 bottom layer in the design.
1. INTRODUCTION Low-T, superconducting quantum interference devices (SQUIDs) are well-known very sensitive superconducting sensors for magnetic flux and are used for a wide range of applications. The energy resolution and the flux slew rate are two important parameters, which are dependent on the properties of the Josephson junctions that are used in the design. Both the conventional resistively shunted dc SQUID and the digital SQUID benefit from a reduction in the junction size, i.e. the flux noise and in case of the digital SQUID also the flux slew rate can be improved by reducing the junction size. The ramp-type junction, which is discussed in this paper, is one of the possibilities to decrease the size of low-T, Josephson junction [ 1,2]. The main advantage of this technique is that standard lithography and fabrication processes can be used. In this paper, we discuss the need for small junction areas to further improve the performance of (digital) SQUIDs and we present the first results on ramp-type junctions based on Nb/Al technology. In the design of superconducting circuits, e.g. SQUIDs, the parameters of the Josephson tunnel junction, like critical current IO, the capacitance Cj, the related plasma frequency f p and the normal state resistance RN, play an important role. The dc SQUID consists of a superconducting loop interrupted by two Josephson tunnel junctions, which are shunted by resistors to remove hysteresis. The McCumber parameter,
determines whether the junction is hysteretic or non-hysteretic, i.e. for pc 1 the junction is hysteretic and for pc < 1 the junction is non-hysteretic. In this equation, R, is the effective resistance of the shunt resistance and the quasiparticle resistance. The white noise in a dc SQUID is caused by thermal noise in the shunt resistors and is given by
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Junction capacitance (pF) Figure 1. Contour plot of the energy resolution of a dc SQUID. The parameters that are fixed in this calculation are: the temperature T = 4.2 K, the screening parameter pL = 2Z,&$DO = 1 and the McCumber parameter pc = 0.3.
Here, y = 8, T is the temperature and Lsq is the SQUID inductance. From equation ( 2 ) , we can conclude that by increasing the shunt resistance R, the noise for a SQUID with a certain inductance decreases. However, equation (1) tells us that we can only increase the resistance when we decrease the junction capacitance, assuming that the critical current is fixed, i.e. assuming that pc = 0.3 to remove hysteresis, the shunt resistors can be increased when the junction capacitance is decreased. Figure 1 shows a contour plot of the energy resolution E = Sd2Ls, of a dc SQUID. It clearly shows that the sensitivity of a SQUID is strongly dependent on the junction capacitance and the SQUID inductance. Previously, it has been shown that by reducing the SQUID inductance, the energy resolution can be reduced to values close to the quantum limit. However, since the ability of signal coupling reduces when decreasing the SQUID inductance, in most practical applications, the SQUID inductance cannot be made too small [3]. It can be concluded that for a conventional resistively shunted dc SQUID with a fixed inductance, its noise characteristics can only be improved by reducing the junction capacitance and thus the junction size.
2. DIGITAL SQUIDS For specific applications like the readout of cryogenic particle detectors, the slew rate of conventional analogue SQUID systems is too small. The slew rate of these systems is limited to about lo6ads, which is mainly determined by the room temperature flux locked loop (FLL) electronics and not by the intrinsic properties of the SQUID itself. To enable a high count rate and a high sensitivity of cryogenic particle detectors, SQUID systems with both low noise and high slew rate are required. In a digital SQUID, e.g. the Smart DROS [4], the FLL circuitry and the SQUID itself are integrated on one single chip. Consequently, the Smart DROS has the potential to be both very fast and very sensitive. The slew rate of the Smart DROS can be orders of magnitude larger than that of conventional SQUID systems. However, the plasma frequency of the Josephson junctions,
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limits the maximum frequency at which that Smart DROS can be operated. The plasma frequency of the junctions can be increased by decreasing the junction capacitance so that the operating frequency of the Smart DROS can be increased. This results in flux slew rates up to lo8 @& for junction sizes around 1 pm2 [ 5 ] .
3. EXPERIMENTAL In the previous section, the importance of reducing the junction capacitance and thus the junction size was discussed. Since the size of planar junctions cannot be easily decreased down to the sub-pm2 level using standard photolithography, we have developed sub-pm2 junctions based on a ramp-type structure. Figure 2a shows a schematic overview of a low-T, ramp-type junction. The main advantage of these junctions is that the size in one direction can be made very small, since it is determined by the thickness of the Nb bottom layer. The junctions we have developed are based on standard NWAI technology and the ramps are fabricated using Ar-etching. As a first step towards very sensitive dc SQUIDs and very fast Smart DROSS, we have fabricated dc SQUIDs based on ramp-type junctions with a junctions size down to 0.2 x 2 pm2. The slope of the ramps is -45 degrees, the thickness of the Nb bottom electrode was 150 nm and the junction width was 2 pm or larger. Figure 2b shows a micrograph of the junction area of a dc SQUID based on ramp-type junctions with a width of 3 pm. 4. RESULTS
The first series of ramp-type junctions we have fabricated did not show hysteresis at 4.2 K. The I-V characteristics showed normal resistances much smaller than expected. This is most probably caused by the layout of the ramp-type junctions. As is shown in Fig. 2a, the layers of the two Nb electrodes are separated by a barrier trilayer of Al,AlO,,AI. Because of the proximity effect, the AI layers will become superconducting only when they are in close contact with Nb layers and the actual barrier is formed by the A10, layer. The thickness of this AlO, layer is about 1 nm. Since the AI,AlO,,AI trilayer lies under the complete Nb top electrode, it is very likely that the A10, layer is not completely closed. Consequently, when the Nb top electrode makes contact with the A1 bottom layer on top of the substrate the junction will be low ohmically shunted by the normal conducting A1 bottom layer [6]. At temperatures below 4.2 K, the .critical current of the ramp-type junctions increased drastically, i.e. the l o increased by a factor 25 when cooling down from 4.2 to -1.5 K. This phenomenon can also be explained as an effect of the AI bottom layer. As was discussed above, because of the proximity effect, the A1 layers become superconducting where they are in close contact with the Nb layers. At 4.2 K, this effect is of the order of tens of nm. However, at lower temperatures, the proximity effect increases until the critical temperature of AI is reached. At this point, the A1 layers become completely superconducting. As a result, the effective junction size increases drastically and thus the critical current increases also.
Figure 2. (a) Scheme of a low-T, ramp-type junction. (b) Micrograph of the ramp-type junctions of a dc SQUID. The junction width is 3 pm.The lower part in the micrograph is the SQUID washer, which forms the bottom electrode of the junctions.
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Although the non-hysteretic behavior of the ramp-type junctions is unwanted, this effect can be exploited to fabricate ramp-type dc SQUIDs without external shunt resistors. Figure 3a shows the experimental V-@ characteristics of a dc SQUID based on 0.2 x 12 pm2 ramp-type junctions at different bias currents and Fig. 3b shows the flux noise spectrum of this SQUID. The positions of the minimum and maximum voltage are interchanged from curve to curve, which is caused by resonances. These resonances are caused by the fact that no damping resistors are used in this SQUID. Because of the small output signal of the ramp-type SQUID, the noise was measured using a two-stage SQUID setup in which a second SQUID was used as a low-noise preamplifier [7]. The measured white noise is 1.2 p@~/dHz, represented by the dotted line, which corresponds to the theoretically calculated value.
5. CONCLUSION The junction capacitance is an important parameter in the design of IOW-T, SQUIDs. Decreasing the capacitance reduces the flux noise and for digital SQUIDs, it allows flux slew rates that are orders of magnitude larger than that of conventional SQUID systems. In order to reduce the junction capacitance, we have developed a junction fabrication process based on a ramp-type structure. This allows sub-pm2 Josephson junctions using standard Nb/AI technology and standard lithography. The first junctions showed non-hysteretic behavior caused by the AI bottom layer in the design. Based on these junctions, dc SQUIDs have been fabricated. Although these non-optimized SQUIDs showed promising results, the non-hysteretic behavior is unwanted and uncontrollable. Further research is necessary to improve the fabrication process, so that high quality, low capacitance Josephson junctions can be fabricated, which are required for high speed digital SQUIDs [2]. This means that junctions have to be designed in which the AI bottom electrode cannot shunt the junction.
References [l] Broom R.F., Oosenbrug A., Walter W., Appl. Phys. Lett. 37 (1980) 237-239. [2] Hunt B.D., LeDuc H.G., Cypher S.R., Stem J.A.,Appl. Phys. Lett. 55 (1989) 81-83. [3] Flokstra J., Bartolome E., Van Duuren M.J., Brons G.C.S., Veldhuis D., Rogalla H., J. Phys. IV France 8 (1998) 229-232. [4] Podt M., Keizer D., Flokstra J., Rogalla H., Physica C 326-327(1999) 1-6. [5] Podt M., Mieog A.J., Rolink B.G.A., Flokstra J., Rogalla H., Supercond. Sci. Technol. 14 (2001) 1027-1030. [6] Mizutani N., Uehara G., Yamasaki S., Adachi A., Takada Y., Kado H., Jpn. J. Appl. Phys. 33 (1994) 1515-1518.
[7] Podt M., Van Duuren M.J., Hamster A.W., Flokstra J., Rogalla H., Appl. Phys. Lett. 75 (1999) 23162318.
