Low-Temperature Bonding to 304 Stainless Steel for ... - IEEE Xplore

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 4, APRIL 2011

479

Low-Temperature Bonding to 304 Stainless Steel for High-Temperature Electronic Packaging Chu-Hsuan Sha and Chin C. Lee, Fellow, IEEE

Abstract— In this paper, silicon (Si) chips were bonded to 304 stainless steel (304 SS) substrates using silver–indium (Ag–In) binary system without any use of flux. 304 SS substrates were also bonded to 304 SS substrates to develop a low-temperature fluxless process to seal two 304 SS parts together. In the bonding design, Ag and In were deposited separately in a layered structure. Various processes and solutions were experimented to plate Ag on 304 SS. So far, we have not found a process that could plate Ag directly on 304 SS without an intermediate layer. At present, the most successful intermediate layer seems to be nickel (Ni). Thus, Ni was plated on 304 SS, followed by Ag. The resulting 304 304 SS substrates were annealed to increase Ag grain size if grain growth is needed for successful bonding. Nearly joints were produced on Si to 304 SS bonding and 304 SS to 304 SS bonding. The resulting joints consist of Ag, Ag-rich solid solution (Ag), Ag3 In, and Ag2 In. The joints were fabricated at only 190 °C. Yet, the resulting joints exceed 660 °C in melting temperature. This new bonding technique should be valuable for packaging electronic devices that need a high operating temperature. It is also useful for bonding 340 SS parts together at low temperature. Index Terms— Electronic packaging, electroplating, lowtemperature fluxless bonding, silicon, silver-indium alloys, stainless steel.

I. I NTRODUCTION

O

THER than resistance to corrosion, stainless steel (SS) has many valuable properties that make it an excellent packaging material for high-temperature operations. Among the various kinds of SS, 304 SS is particularly interesting not only because it is a solid solution of iron (Fe), chromium (Cr), and nickel (Ni), but also because of its many advantages including stainless, high melting temperature, relatively high conductivity, low yield strength, high tensile strength, nearly unbreakable, low cost, and ease of forging and machining. To explore the potential of 304 SS as a high-temperature packaging material, various processes need to be developed to bond 304 SS to semiconductor chips, 304 SS parts, interconnect structures, and insulators. Bonding temperature of Manuscript received June 9, 2010; revised September 23, 2010; accepted November 8, 2010. Date of publication March 10, 2011; date of current version April 8, 2011. This work was supported in part by Sandia National Laboratories. The work of C.-H. Sha was supported in part by the Materials and Manufacturing Technology Fellowship. Recommended for publication by Associate Editor Y.-S. Lai upon evaluation of reviewers’ comments. C.-H. Sha is with the Materials and Manufacturing Technology Program, University of California, Irvine, CA 92697 USA (e-mail: [email protected]). C. C. Lee is with the Materials and Manufacturing Technology Department of Electrical Engineering and Computer Science, University of California, Irvine, CA 92697 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCPMT.2011.2106211

some of these processes may have to be compatible with that of typical electronic packaging operations. We began by developing a basic bonding process using the silver-indium (Ag–In) system. Ag is selected as the electrode material owing to its low yield strength, which is only one-sixth of that of copper (Cu) and 1.1 times of Sn–Ag eutectic alloys [1], [2], and highest electrical conductivity (63 × 106 /m · ) and highest thermal conductivity (429 W/m·K) among all metals. With creative design, joints can be manufactured at low processing temperature, e.g., 190 °C, but can achieve high melting temperature after bonding, e.g., 650 °C. This is possible because of the compositional change of the bonding media during the bonding process. This basic process can be applied to bonding semiconductor chips to 304 SS, 304 SS to 304 SS, 304 SS to Cu, and 304 SS to ceramics. In this paper, we report fluxless bonding between Si/Cr/Au/Ag and SS/Ni/Ag/In/Ag and between SS/Ni/Ag and SS/Ni/Ag/In/Ag structures, respectively, at 190 °C in 90-mTorr vacuum. Nearly perfect joints were obtained. The bonding surfaces and the interfaces were evaluated by scanning electron microscopy (SEM) with energy dispersive X-ray spectroscopy (EDX). In what follows, we first present the experimental designs and procedures. Experimental results are then reported and discussed. Finally, a short summary is given. II. E XPERIMENTAL D ESIGNS AND P ROCEDURES SS substrates of two different sizes were prepared and cut from a 304 SS sheet with one side mirror-finished. The large substrates were 9 mm × 9 mm × 0.9 mm (width × length × thickness) and the small one were 5 mm × 5 mm × 0.9 mm. Afterwards, 2–3 μm Ni was first electroplated on the large substrates as a barrier and bonding layer, followed by plating 35–50-μm thick Ag layer. The Ag-cladded SS substrates were then annealed at 250 °C for 40 h to coarsen the Ag grains. After the annealing process, the surface was slightly polished to remove some bumps formed during the annealing. Indium of 5–10 μm thickness and 0.1 μm Ag were then plated on Ag-cladded 304 SS substrates. The thin outer Ag layer was used to inhibit indium oxidation. A thicker Ag layer was used to accommodate the coefficient of thermal expansion (CTE) mismatch between 304 SS (17 ppm/°C) and Si (3 ppm/°C). On the small 304 SS substrates, 1.5–4 μm Ni was first electroplated as a barrier and bonding layer, followed by plating of a 10-μm Ag layer. The small Ag-cladded SS substrates were also annealed at 250 °C for 40 h to coarsen the Ag grains. They were slightly polished after the annealing process.

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480


Si Cr/Au Ag + Ag In Ag Ni SS Acc V Spot Magn Det WD Exp 10 μm Plated Ag on SS/Ni 10.0 kV 3.0 5000x SE 9.6 1

Fig. 1.

Bonding Design I of Si/Cr/Au/Ag to SS/Ni/Ag/In/Ag (not to scale).

(a) TABLE I EDX D ATA ON THE C ROSS S ECTION OF A S AMPLE FABRICATED WITH D ESIGN I. A LL THE L OCATIONS C ORRESPOND TO P OINTS M ARKED IN F IG . 5(b)

Fig. 5(b) a b c d e

Ag composition (at. %) 94–00 72–91 64–68 74–83 95–100

In composition (at. %) 0–6 9–28 32–36 17–26 0–5

Locations (μm) (depth from Si/Ag interface) 10 15 25 38 54

Possible phases Ag (Ag) + Ag3 In Ag2 In (Ag) + Ag3 In Ag 20 μm Acc V Spot Magn Det WD Exp Plated Ag on SS/Ni 10.0 kV 3.0 15000x SE 9.6 1

To prepare Si chips for bonding experiments, 2 in. Si wafers were first deposited with 300 Å Cr and 1000 Å gold (Au) in a high vacuum e-beam evaporator in one vacuum cycle (3 × 10−6 Torr). The Cr/Au dual layers serve the adhesive layer as well as the seed layer for subsequent Ag electroplating process. Si chips of 5 mm × 5 mm were then diced from the resulting wafers. Thus, SS substrates and Si chips were ready for fluxless bonding experiments. The fluxless bonding experiments were conducted between Si/Cr/Au/Ag and SS/Ni/Ag/In/Ag and between SS/Ni/Ag and SS/Ni/Ag/In/Ag structures. The Si chip and SS substrate were held together with 150-psi static pressure to ensure intimate contact. The bonding process was performed at 190 °C with a dwell time of 10 min in 90 mTorr vacuum to avoid oxidation during bonding [3]. No flux was used during the bonding process. The same process was used to bond small 304 304 SS substrates to large 304SS substrates. SEM with EDX was used to study the Ag microstructure and to analyze the quality and chemical compositions. III. E XPERIMENTAL R ESULTS AND D ISCUSSION A. Bonding Design I Si/Cr/Au/Ag(20 μm) to SS/Ni(3 μm)/ Ag(50 μm)/In(10 μm)/Ag(0.1 μm) (with SS/Ni/Ag Annealed at 250 °C for 40 h) The bonding structure is depicted in Fig. 1. The Ag-rich Ag–In joint was successfully made between Si/Cr/Au/Ag and SS/Ni/Ag/In/Ag at 190 °C. The microstructure of the Ag layer plated on the large SS/Ni substrate before annealing is exhibited in Fig. 2. It is seen that Ag grains are less than

(b) Fig. 2. SEM images showing the microstructure of Ag layer plated on a large SS/Ni substrate. (a) At low magnification. (b) At high magnification.

0.5 μm. Based on our previous result [4], Ag with small grains tends to react with the indium-rich molten phase rapidly through grain boundary diffusion and form Ag2 In intermetallic compound (IMC). As a result, the bonding structure is not able to hold sufficient amount of molten phase during the bonding process. This leads to incomplete bonding or no bonding at all. To overcome this difficulty, the SS/Ni/Ag substrate was annealed at 250 °C for 40 h to increase the Ag grain size. The temperature of 250 °C was chosen because of a specific application concern. Fig. 3 is an SEM image of the Ag microstructure after the annealing. It is observed that the Ag grains have grown to more than 2 μm. A few cracks are seen at the Ag grain boundaries and boundaries between Ag hillocks on Figs. 2 and 3. The cracks are caused by stresses during the plating and annealing processes. Since the In layer will be plated over the Ag layer and gets melted during bonding, the molten phase will fill up and repair the cracks. Thus, the cracks are not expected to affect the bonding quality as long as they are in the micrometer size or less. The microstructure of Ag layer plated on Si chips was also evaluated with SEM, as displayed in Fig. 4. The Ag grains are 2–10 μm in size without annealing. It is interesting to note that Ag grain size and microstructure depend largely on the surface onto which the Ag atoms are deposited in the plating process. Comparing Fig. 2 with Fig. 4, it is observed that the

SHA AND LEE: LOW-TEMPERATURE BONDING TO 304 STAINLESS STEEL

Acc V Spot Magn Det WD Exp 10 μm Ag Microstructure after 250 °C 40 hrs 10.0 kV 3.0 5000x SE 9.6 1

481

100 μm Ag Microstructure on Si

Acc V Spot Magn Det WD Exp 10.0 kV 3.0 500x SE 10.2 1

(a)

(a)

2 μm Acc V Spot Magn Det WD Exp Ag Microstructure after 250 °C 40 hrs 10.0 kV 3.0 15000x SE 9.6 1

(b) Fig. 3. SEM images showing the microstructure of Ag layer plated on a large SS/Ni substrate after annealing at 250 °C for 40 h. (a) At low magnification. (b) At high magnification.

Ag grains on Si chips are much larger than those on the SS/Ni substrate. The Si chips are coated with a thin Cr layer followed by a thin Au layer with a perfect mirror finish. It appears that the Ag atoms prefer to grow into bigger grains on a smoother surface. Nevertheless, we have not been able to find a definite correlation between the Ag grain size and the substrate. We continue to search for the correlation as we plate Ag on a variety of substrates. Fig. 5 exhibits cross-sectional images of a bonded sample made at 190 °C. Nearly perfect bonding is observed and no voids are found over the entire cross section of the sample. Based on EDX data and known compounds listed in Table I, the joint is judged to consist of five regions: Ag, (Ag) plus Ag3 In, Ag2 In, (Ag) plus Ag3 In, and Ag. The compounds were estimated on the basis of the Ag–In phase diagram. A more precise technique is needed to confirm them. The 5 mm × 5 mm Si chips did not break after the bonded structures cooled down to room temperature despite the large CTE mismatch between Si and 304 SS. An indicator of the possible breakage due to CTE mismatch is the stress-free shear strain [5]. It is the strain calculated assuming that both the objects bonded are free to contract during cooling down. It is the maximum possible shear strain on the resulting joint. For this design, the stress-free shear strain is calculated to be 0.10.

Acc V Spot Magn Det WD Exp 10.0 kV 3.0 5000x SE 10.2 1

10 μm Ag Microstructure on Si

(b) Fig. 4. SEM images showing the microstructure of Ag layer plated on a Si chip. (a) At low magnification. (b) At high magnification.

The relatively small shear strain is from the result of the thick Ag layer chosen. The ductile Ag is able to handle it. Due to its high electrical and thermal conductivities, a thicker Ag joint improves the electrical and thermal performances of the bonded structure. The only possible concern is the cost of Ag. In that case, the cost of Ag should be considered in the design phase so that optimal Ag thickness is chosen for the reliability required. B. Bonding Design II SS/Ni(4 μm)/Ag(10 μm) (Small) to SS/Ni(3 μm)/Ag(45 μm)/In(5 μm)/Ag(0.1 μm) (Large) (with Large SS/Ni/Ag Annealed at 250 °C for 40 h) The bonding structure is shown in Fig. 6. Here, the objective is to bond small SS substrates to large SS substrates. The microstructures of as-plated and post-annealed Ag layers on large SS substrates, respectively, are similar to those in Figs. 2 and 3. Fig. 7 exhibits the microstructure of the Ag layer plated on a small SS substrate. It is observed that grains are quite small, less than 0.2 μm. We notice that the Ag grains of the Ag layer plated on large SS substrates are larger than those plated on small SS substrates. This is believed to be caused by the thicker Ag layer on large SS substrates, i.e., 50 μm, versus a thinner Ag layer, i.e., 10 μm, on small SS

482


Si chip

SS Expected bonding interface

Ni Ag + Ag In Ag Ni

Plated Ni SS

Large SS substrate Acc V Spot Magn Det WD Exp 20 μm SS/Ni/Ag/In/Ag + Ag/Au/Cr/Si 10.0 kV 3.0 1500x SE 10.1 1

(a)

Fig. 6.

Bonding Design II of SS/Ni/Ag to SS/Ni/Ag/In/Ag (not to scale).

Si chip

a b c d

e Acc V

20 μm Spot Magn Det WD Exp SS/Ni/Ag/In/Ag + Ag/Au/Cr/Si 10.0 kV 3.0 3000x SE 10.1 1

(b)

Acc.V Spot Magn Det WD Exp smaller SS/Ni/Ag 10.0 kV 3.0 5000x SE 28.3 1

10 μm

(a)

Plated Ag

Plated Ni

Large SS substrate

Acc V Spot Magn Det WD Exp 10 μm SS/Ni/Ag/In/Ag + Ag/Au/Cr/Si 10.0 kV 3.0 5000x SE 10.1 1

Acc.V Spot Magn Det WD Exp smaller SS/Ni/Ag 10.0 kV 3.0 10000x SE 28.3 1

5 μm

(c)

(b)

Fig. 5. Cross-sectional SEM images of the sample fabricated with Design I. The 50-μm Ag layer on large SS/Ni was annealed before plating In/Ag. (a) Overall bonding structure with an 83-μm thick joint between the Si chip and SS substrate. (b) Joint consisting of five distinct regions (EDX data on regions marked “a” to “e” are presented in Table I). (c) Well-bonded Ag/Ni/SS region.

Fig. 7. SEM images showing the microstructure of the Ag layer plated on a small SS/Ni substrate. (a) At low magnification. (b) At high magnification.

substrates. The Ag grains grow larger when more Ag atoms are deposited to build up the Ag layer. Small SS substrates were bonded to large SS substrates with the same bonding conditions as Design I. Fig. 8 displays the cross-sectional SEM image of a sample. Voids are found on the

bonding interfaces and the bonding region. The result indicates incomplete bonding, which is likely caused by incomplete wetting of the molten phase with the Ag layers. Based on our previous bonding results [4], Ag grain size plays an important role in successful bonding. For this bonding design, the small SS substrate plated with Ni and Ag layers was not annealed. Thus, the Ag grains on the small SS substrate are very small. The Ag atoms react rapidly with the molten phase to form


483

Small SS substrate Plated Ni

Small SS substrate Plated Ni

Expected bonding interface

Plated Ni Large SS substrate 20 μm Acc.V Spot Magn Det WD Exp SS/Ni/Ag/In/Ag + Ag/Ni/SS 10.0 kV 3.0 2500x SE 10.0 1

Acc.V Spot Magn Det WD Exp 20 μm SS/Ni/Ag/In/Ag + Ag/Ni/SS 10.0 kV 3.0 2000x SE 9.9 1

(a) Fig. 8. SEM image showing the bonding region of a sample made with bonding Design II. Many voids are observed, indicating incomplete bonding.

Small SS substrate Plated Ni f g h i

j 20 μm Acc.V Spot Magn Det WD Exp SS/Ni/Ag/In/Ag + Ag/Ni/SS 10.0 kV 3.0 3000x SE 10.0 1

(b) Acc.V Spot Magn Det WD Exp 10 μm 10.0 kV 3.0 5000x SE 9.8 1 Ag on SS/Ni after anneal 250 °C 40 hrs

(a)

Plated Ag

Plated Ni

Large SS substrate

10 μm Acc.V Spot Magn Det WD Exp SS/Ni/Ag/In/Ag + Ag/Ni/SS 10.0 kV 3.0 5000x SE 10.0 1

(c) Acc.V Spot Magn Det WD Exp 5 μm 10.0 kV 3.0 5000x SE 9.7 1 Ag on SS/Ni after anneal 250 °C 40 hrs

(b) Fig. 9. SEM image showing the microstructure of Ag layer plated on a small SS/Ni substrate after annealing at 250 °C for 40 h. (a) At low magnification. (b) At high magnification.

solid Ag2 In. The molten phase is consumed before it has a chance to flow and fill up the original bonding interface. With this understanding, we decided to anneal the small SS substrates as well. This leads to next bonding design.

Fig. 10. Cross-sectional SEM images of a sample made with Design III. (a) Bonded structure with a 54-μm joint between two SS substrates. (b) Joint consisting of five distinct regions (EDX data on regions marked “f” to “j” are given in Table II). (c) Well-bonded Ag/Ni/SS region.

C. Bonding Design III SS/Ni(1.5 μm)/Ag(10 μm) (Small) to SS/Ni(2 μm)/Ag(35 μm)/In(5 μm)/Ag(0.1μm) (Large) (with Both SS/Ni/Ag Annealed at 250 °C for 40 h) For Design III, both small and large SS substrates, after plating with Ni and Ag layers, were annealed at 250 °C for 40 h. Fig. 9 shows the microstructure of the Ag layer plated on a small SS substrate after annealing. It is seen that the

484


TABLE II EDX D ATA ON THE C ROSS S ECTION OF A S AMPLE FABRICATED WITH

Si or SS

D ESIGN III. A LL THE L OCATIONS C ORRESPOND TO P OINTS M ARKED IN

Plated Ag

F IG . 10(b) Ag composition (at. %) 97–100 74–91 65–67 76–87 98–100

Fig. 10(b) f g h i j

In composition (at. %) 0–3 9–26 33–35 13–24 0–2

Plated In

Locations (μm) (depth from Ni/Ag interface) 5 12 16 27 37

Plated Ag Possible phases Ag (Ag) + Ag3 In Ag2 In (Ag) + Ag3 In Ag

SS substrate

0 1000

10

20

90

AgIn2 IMC Ni

Si or SS Cr/Au orNi Plated Ag Plated Ag

80

Plated Ag(cap layer)

(a)

Ag2In Atomic Percent Indium 30 40 50 60 70

Cr/Au or Ni

100 SS substrate

961.93 °C

Mixture of molten phase and Ag2In Ni

900 (b)

700

695 °C

β

L 660 °C

670 °C

Si or SS

600 500 400

ζ

(Ag)

Ag2In

300

Plated Ag α'

100 0

Fig. 11.

205 °C 166 °C

187 °C

200

10 0 Ag

20

γ

AgIn2

Termperature ºC

800

30 40 50 60 70 Weight Percent Indium

Cr/Au or Ni Plated Ag Ag-rich solid solution andAg3In Ni

156.634 °C 144 °C

SS substrate

(In) (c)

80

90

100 In

Silver-indium phase diagram [6].

Ag grains have grown to about 2 μm. Since CTE mismatch between 304 SS and 304 SS is not an issue, the Ag thickness was reduced. Large SS substrates were plated with 2 μm Ni followed by 35 μm Ag. After annealing, they were plated with 5 μm In and a thin Ag cap layer. On small substrates, 1.5 μm Ni was plated followed by 10 μm Ag. They were then annealed. The small substrate was bonded to a large substrate with the same bonding conditions as before. Fig. 10 shows the cross sectional SEM image of a sample produced. The total joint thickness is 54 μm. EDX data and possible phases are presented in Table II. The constitutive regions of the joint are similar to those in design I. We have successfully bonded Si chips to 304 SS substrates, and two 304 SS substrates together. Here, we present our bonding model. To help understand it, we bring up the Ag–In phase diagram, shown in [6, Fig. 11]. There are seven equilibrium phases, among which two are identified as IMCs, i.e., Ag2 In and AgIn2. Fig. 12 illustrates the proposed bonding mechanism. The Ag plated on SS substrates, after annealing, reacts with In atoms close to the Ag layer to form AgIn2 while In is being plated [7], [8]. A thin Ag layer is then plated over In to prevent it from oxidation. Now the structure on large SS substrates would look like SS/Ni/Ag/AgIn2/In/Ag, shown in Fig. 12(a). Then the Si chip and a SS substrate or two SS substrates are held together, mounted on the heating stage in a vacuum chamber, and heated to 190 °C. As the temperature reaches 166 °C, the peritectic decomposition temperature of

Fig. 12. Proposed bonding mechanism. (a) As deposited and before bonding. (b) In the temperature range 166–190 °C. (c) After cooling down to room temperature.

AgIn2, the molten phase (L), and Ag2 In solid grains coexist on the bonding interface. Fig. 12(b) gives a better picture of what is happening at this stage. During the bonding process, Ag atoms on the large SS substrate diffuse slowly to the L phase due to the low density of the grain boundaries in the annealed Ag layer. The Ag2 In growth rate as controlled by grain boundary diffusion becomes much slower [9], [10]. Consequently, sufficient amount of L phase stays molten and long enough to flow and react with the Ag layer on the Si chip or the small SS substrate. A joint is essentially formed once the reaction takes place. Fig. 12(c) shows the expected structure after the sample cools down to room temperature. Since the Ag–In bonding process is a liquid–solid chemical reaction, to achieve a high-quality joint, complete wetting on the solid side of the bonding interface by the molten phase L is the most crucial factor. For the present design, the solid side is pure Ag. It is the upper Ag layer in Figs. 1 and 6. Thus, the molten phase must wet the upper Ag. For this to happen, there must be enough molten phase to fill up the gap on the interface caused by the uneven Ag surface. During the bonding process, the molten phase is sitting on the bottom Ag layer and continues to react with it to form solid Ag2 In. As a result, the amount of molten phase decreases even without wetting the top Ag layer. Thus, it is important to slow down the reaction between the molten phase and the bottom Ag. Ag with a larger grain size reacts more slowly with the molten phase and thus is able to hold the molten phase. This is why


an annealing step is added after the Ag layer is plated on the SS/Ni substrate to grow the Ag grains. From the Ag–In phase diagram shown in [6, Fig. 11], the melting temperature of the Ag/Ag2 In/Ag joint exceeds 660 °C. Thus, the bonding processes presented allow one to fabricate high-temperature joints (660 °C) at low-temperature (190 °C) ones. If needed, it is possible to further anneal the samples to convert the joint into Ag/(Ag)/Ag, where (Ag) is a solid solution of indium in Ag [11]. The (Ag) phase can contain up to 20 wt. % of indium. Its melting temperature is higher than 850 °C. IV. C ONCLUSION In this paper, we presented a technique to produce joints between Si chips and 304 SS substrates and between small 304SS substrates and large 304 SS substrates using the Ag– In binary system. Large SS substrates were plated with a Ni layer and a thick Ag layer, annealed at 250 °C for 40 h, and plated with In and a thin Ag capping layer. The thick Ag layer serves as a strain buffer to deal with the large CTE mismatch between Si and SS. The thin Ag capping layer prevents inner In from oxidation. Bonding results seem to support our previous model of the effect of Ag grain size in the bonding process [4]. The Ag microstructure controls Ag2 In growth rate and dictates the quality of joint formation. Small Ag grains result in fast reaction of Ag atoms with the molten phase L to grow solid Ag2 In compound. The molten phase is consumed too rapidly to have a chance to wet the Ag layer on the small SS substrate. To slow down the reaction of the Ag layer with the molten phase, an annealing step was added after the Ag layer was plated to coarsen the Ag grains. High-quality joints were successfully produced at 190 °C without any use of flux. Based on EDX results and the Ag–In phase diagram, the joint is estimated to contain Ag, (Ag), Ag3 In, and Ag2 In. Its melting temperature exceeds 660 °C. With an additional annealing step, it is possible to convert Ag3 In and Ag2 In compounds into (Ag) by further interdiffusion and reactions with Ag. The resulting joint will have a melting temperature higher than 660 °C and contain no IMCs. The new bonding technique presented should be valuable in packaging highpower electronic devices for high-temperature operations. It should also be useful to bond two 304 SS parts together at a low bonding temperature of 190 °C. R EFERENCES [1] J. R. Davis, Metals Handbook, vol. 2, 10th ed. Materials Park, OH: ASM, 1990, pp. 699–1113. [2] B. Yeung and J.-W. Jang, “Correlation between mechanical tensile properties and microstructure of eutectic Sn-3.5Ag solder,” J. Mater. Sci. Lett., vol. 21, no. 9, pp. 723–726, 2002. [3] C. C. Lee, D. T. Wang, and W. S. Choi, “Design and construction of a compact vacuum furnace for scientific research,” Rev. Sci. Instrum., vol. 77, no. 12, pp. 125104-1–125104-5, 2006. [4] P. J. Wang, C.-H. Sha, and C. C. Lee, “Silver microstructure control for fluxless bonding success using Ag-In system,” IEEE Trans. Compon. Packag. Technol., vol. 33, no. 2, pp. 462–469, Jun. 2010. [5] W. Engelmaier, “Solder attachment reliability, accelerated testing, and results evaluation,” in Solder Joint Reliability: Theory and Applications, J. H. Lau, Ed. New York: Van Nostrand, 1991, pp. 545–587.

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[6] H. Okamoto and T. B. Massalski, Binary Alloy Phase Diagram. Metal Park, OH: ASM, 1990, pp. 381–383. [7] B. Gollas, J. H. Albering, K. Schmut, V. Pointner, R. Herber, and J. Etzkorn, “Thin layer in situ XRD of electrodeposited Ag/Sn and Ag/In for low-temperature isothermal diffusion soldering,” Intermetallics, vol. 16, no. 8, pp. 962–968, Aug. 2008. [8] P. J. Wang, J. S. Kim, and C. C. Lee, “Intermetallic reaction between electroplated indium and silver layers,” J. Electron. Mater., vol. 38, no. 9, pp. 1860–1865, 2009. [9] V. Simi´c and Ž. Marinkovi´c, “Room temperature interactions in Agmetals thin film couples,” Thin Solid Films, vol. 61, no. 2, pp. 149–160, Aug. 1979. [10] R. Roy, “The kinetics of formation of intermetallics in Ag/In thin film couples,” Thin Solid Films, vol. 197, nos. 1–2, pp. 303–318, 1991. [11] J. S. Kim, P. J. Wang, and C. C. Lee, “Very high-temperature joints between Si and Ag-copper substrate made at low temperature using InAg system,” IEEE Trans. Compon. Packag. Technol., vol. 31, no. 4, pp. 782–789, Dec. 2008.

Chu-Hsuan Sha received the B.S. degree in materials science and engineering from National Taiwan University, Taipei, Taiwan, in 2005, and the M.S. degree in materials science and engineering from the University of Florida, Gainesville, in 2007. He is currently pursuing the Ph.D. degree from the Materials and Manufacturing Technology Program at the University of California, Irvine, where he works with Prof. C. C. Lee. His current research interests include flip-chip bonding, solid-state bonding, and fluxless oxidationfree bonding using pure Ag, Au, and Ag-In binary system.

Chin C. Lee (S’74–M’79–SM’89–F’01) was born in Taiwan. He received the B.E. and M.S. degrees in electronics from National Chiao-Tung University, Hsinchu, Taiwan, in 1970 and 1973, respectively, and the Ph.D. degree in electrical engineering from Carnegie-Mellon University (CMU), Pittsburgh, PA, in 1979. He was a Research Associate with CMU for a year and joined the Department of Electrical Engineering, University of California, Irvine, as a Research Specialist. In 1984, he was an Assistant Professor with the Department of Electrical Engineering, University of California, and became a Professor of electrical and computer engineering in 1994. He served as the Graduate Advisor of the Department of Electrical and Computer Engineering, University of California, from 1990 to 1994, and from 1999 to 2002. He is currently a Professor in the Department of Electrical Engineering and Computer Science, University of California, where he is also the Director of the School-Wide Materials and Manufacturing Technology Graduate Program. He has co-authored four book chapters and published more than 200 research papers. His current research interests include semiconductor devices, microwave devices, electronic packaging, thermal design of electronic devices, bonding technology, electromagnetic theory, acoustic waves, acoustic microscopy, integrated optics, and optoelectronics. Dr. Lee is a Fellow of the Photonics Society of Chinese-Americans, and a member of Tau Beta Pi. He is an Associate Editor of the IEEE T RANSAC TIONS ON C OMPONENTS AND PACKAGING T ECHNOLOGIES and the IEEE T RANSACTIONS ON E LECTRONICS PACKAGING M ANUFACTURING. Since 1998, he has been in the Program Committee of the IEEE Electronic Components and Technology Conference. He also serves as the Vice-Chair of the IEEE-Components, Packaging, and Manufacturing Technology (CPMT) Technical Committee 5. He received the Best Paper Award for the Diagnosis of Hybrid Microelectronics Using Transmission Acoustic Microscopy at the IEEE Reliability Physics Symposium in 1979, and the IEEE CPMT Exceptional Technical Achievement Award in 2007. He is listed in the Thomson-ISI Citation Database among 253 of the world’s most highly cited researchers in the engineering category.