Low-Voltage CMOS Switched Resistor Filters
Mohy A. Abo-El-soud", Roshdy A. AbdelRassoul", Senior Members, IEEE, Amany K. Farrag**, and Ahmad A. Taha***
Abstract This paper presents a switched resistor (SR) low-pass filter operated with a I.2V power supply. This filter is included in the analog font-end of the data transceiver used for wireless communication system. Such filter is realized in a standard 0.8 pm CMOS technology, with threshold voltage VT=+0.7V for NMOS transistors and 0.9 V for PMOS transistors. The filter circuit is designed using switched-opamp technique. This technique allows the operation of opamp is turned on and off by the clock frequency. The sampling clock frequency of the filter is 300 kHz and its 3dB cutoff frequency is 20 kHz Its power consumption is about 1.2 m W.
I. Introduction Recently, the interest toward low-voltage low-power VLSI circuits has increased in all areas of applications. Such trend is due to the increasing significance of portable equipment in different areas, such as telecommunications and consumer electronics. With the reduction in supply voltage of a novel integrated circuit is caused by the technology scaling as well as the power consumption of analog or digital circuits. At low supply voltage, sample-domain technique such as switched-capacitor (SC) circuits does not affect capacitor properties. But during on and off switches and the operation of the opamp becomes very difficult with reducing the supply voltage. In order to solve this problem there are three solutions: by using lower threshold [I], [2], using voltage multiplier [3], [4], and the switched-opamp technique [SI. The use of low threshold voltage is very expensive because it requires a particular technology. In order to use
voltage multiplier, it drives the switches with clock signals higher than the supply voltage. The popular and interesting development now is the switched-opamp technique. In this paper, a low-pass Sallen and Key switchedresistor filter operated from a 1.2V power supply is presented based on the switched-opamp technique. The switched-opamp technique is discussed in Section 11. The SR low pass filter using switched-opamp is described in Section 111. In Section IV simulation results are presented, and Section V gives a conclusion.
11. Switched-opamp design The design of switched-opamp operating at low supply voltage is discussed. The circuit of switched-opamp is shown in Fig. 1. The input stage must be taken into account when the supply voltage is reduced. The input transistors M1 and M2 are PMOS transistors in order to enhance the slew rate of the opamp [7]. The minimum supply voltage to operate properly at VDD,,,~"is given by [6]:
Where VT is the threshold voltage, and AV is the minimum voltage drop below the positive rail.
e
Vdd
,M5 c
4 Wl
* Electronics & Communications Eng. Dept.. Faculty of Engineering, Mansoura University. Mansoum 35516, Egypt. E-mail:
[email protected] ** National Telecommunications Institute (NTI), Cairo. Egypt. e** Egyptian Radio and Television Union (ERTU), Cairo, Egypt. 0-7803-7150-X/01/$10.00@2001 IEEE
Fig. 1
Switched-opamp schematic.
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The PMOS input transistors MI and M2 with NMOS load transistors M3 and M4 are used as shown in Fig. 1. The input stage of opamp, M1, M2, M3, M4, and M5, turns on, when the clock signal clk is applied. In order to achieve the maximal possible signal swing, the miller structure with three transistors M6, M7, and the switch transistor SI in the second stage are used. To achieve lower output impedance of the switched-opamp, NMOS transistors M8 and M9 are used.
I
and 6 kHz band-pass filter and interpolator for the received supervisory audio tone (SAT) signal [8].
1
h t e m
Do m convenion
E R
The voltage gain of the first stage of the circuit shown in Fig. 1 is given by [71:
FSK Mod-
UP
convesion
Where
Data Transceiver
Fig. 2
Data transceiver VLSI chip in wireless communication systems.
Fig. 3
Block diagram of the analog front-end.
gn,, is the device transconductance, and
go is the small signal output conductance, and assuming M1 and M2 are identical and M3 and M4 are also identical, the second stage gain is given by
(3)
The gain-bandwidth product can be obtained from:
g ml =-
(4) c c The transistors’ aspect ratios of the proposed switchedopamp are shown in Table I. WGBW
Table I Transistor sizes TRANSISTOR W/L TRANSISTOR IM8 MI 197 IM9 M2 197 148.5 I M10 M3 M4 I 48.5 1 SI I s2 M5 I97 M6 I97 I s3 I97 I
I
I
In this paper, we concerned only with the 20 kHz lowpass filter as a switched-opamp application based. Fig. 4 shows the schematic diagram of a biquad section for the sixth order Sallen and Key low-pass filter. By replacing the passive resistance in Fig. 4 with the switchedresistor elements, a switched-resistor biquad section is achieved.
IWL I 307.7 I 307.7 I 7.7 I 77
I 77 I
I
12.3
G2
I R1
111. SR filter design The block diagram of a data transceiver in wireless communication systems and its analog front-end components are shown in Figs. 2 and 3 respectively. The analog front-end consists of the receive module which interfaces the digital signal processing block through the comparators and the transmitter module which receives the output signals from the digital function block to generate the output waveforms. The analog front-end for incoming signals contains an anti-aliasing filter, 20 kHz low-pass filter for data signal, 430
R2
Vi
I
Fig. 4
Biquad section of the low-pass filter using passive resistors.
c4
Y C 2 l
C6
Vi
c-4
vo
Fig. 5
Sixth order low-pass filter using switched-resistortechnique.
Fig. 5 shows the complete schematic diagram of the sixth order low-pass filter that consists of three biquads in cascaded configuration. The switched-resistor equivalent consists of two transistors, one of them is NMOS transistor and the other is PMOS transistor connected in parallel. Both transistors are operating in the linear region. The equivalent resistance of Fig. 5 can be represented as:
is about 31 nV/d€€z. The total power consumption of the sixth order low-pass filter is about 1.2 mW. Table 11 Main performance summary
I Open-loop gain I GBW (C,=
Where
R,,
is the total on-resistance of the MOS switches, and
T z
- is the inverse of the duty cycle of the clock signal. Since the passband ripple is not allowed, the Butterworth filter scheme is chosen to achieve a maximally flat response within the passband. This filter is used to remove all unwanted signal components above 20 kHz, so its 3-dB cutoff frequency is 20 kHz and the sampling clock frequency is 300 kHz.
I
I Technology 1 pF)
IPhase margin Power consumption
0.8pm CMOS
I
I
64dB
I
I
80MHz
I
I
Offset voltage
I CMRR
61" 382 yW 52 pV
I
I I/P referred noise voltage @ lkHz I I O/P referred noise voltage (12 lkHz I
75dB 12.7 nV/dHz
I
19.4 yVldHz
I
Pi
a--
-\,,
i,\
\
'\
IV.Simulation results The designed switched-opamp has been simulated using SPICE program. This opamp was realized in a standard 0.8 ym CMOS technology with threshold voltages Vm = 0.7 V for NMOS and VTp =-0.9 V for PMOS transistors. The gain-bandwidth product is 80 MHz with a phase margin equal to 61". The power consumption is about 382 yW and the input-referred filter noise spectral density is 12.7 nV/dHz. The simulated main performance of the designed switched-opamp is summarized in Table 11. Fig. 6 shows the frequency response of the designed sixth order Sallen and Key low-pass filter implemented with switched-resistor technique. As shown in Fig. 6, the -3 dB frequency is 20 kHz with a sampling clock frequency of 300 kHz. As observed from Fig. 7, the input-referred filter noise
Frequency Fig. 6
I
Filter frequency response.
43 1
I
VI. References
Frequency
Fig. 7
Filter input-referred noise.
V. Conclusion In this paper, the switched-opamp has been presented. Such opamp has been applied to the design of switchedresistor filter to be used in the data transceiver in wireless communication systems. The filter is implemented in a standard 0.8 pm CMOS technology. A flat input-referred noise level of about 31 nVIdHz is obtained in the passband. The total power consumed by this filter is 1.2 mW.
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[I] Y. Matsuya and J. Tamada, ‘‘ 1 V-power supply low-power consumption AID conversion technique with swing suppression noise shaping,” IEEE J. Solid-State Circuits, vol. 29, pp. 1524-1530, Dec. 1994. [2] T. Adachi, et. al., ‘‘ A 1.4 V switched-capacitor filter,” in IEEE 1990 Custom Integrated Circuits Cor$, pp. 8.2.18.2.4. [3] J. F. Dickson, “On-Chip high-voltage generation in NMOS integrated circuits using an improved voltage niultiplier technique,” IEEE J. Solid-Stare Circuits, vol. I I, pp. 374378, June. 1976. [4] J. T. Wu, et. al. “ 1.2 V CMOS switched-capacitor circuits,” in IEEE Int. Solid-state Circuits Conf., Feb. 1996, pp. 388389. [5] J. Crols and M. Steyaert, “ Switched-opamp: An approach to realize full CMOS switched-capacitor circuits at very low power supply voltages,” IEEE J. Solid-State Circuits, vol. 29, pp. 936-942, Aug. 1994. [6] A. Bschirotto and R. Castello, “ A 1-V 1.8 MHz CMOS switched-opamp SC filter with rail-to-rail output swing,” IEEE J. Solid-State Circuits, vol. 29, pp. 1979-1986, Dec. 1997. [7] D. John and K. Martin, Analog Integrated Circuit Design, New York: Wiley, 1997. [8] S . H. Bang, J. Choi, B. J. Sheu, and R. C. Chang, “Acompact low-power VLSI transceiver for wireless communication,” IEEE Trans. Circuits Syst-I: Fund. Theory and Appl., vol. 42, pp. 933-945, Nov. 1995.
