MARTE sequence

Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verification Emad Ebeid, Davide Quaglia, Franco Fummi

Dept. of Computer Science - University of Verona, Italy [emadsamuelmalki.ebeidldavide.quaglialfranco.fummi]@univr.it

Abstract-Verification of real time embedded systems at high level of abstraction is a challenging task that requires the simulation of the system and the checking of its timing and functional properties as well as constraints. The paper presents a methodology

which starts from UML sequence diagrams

with MARTE timing constraints and generates a SystemCffLM model with checkers. The execution of the model allows to verify the specified sequence of exchanged information between components while checkers allow to verify that properties and

Library of

timing constraints are met. The application of the methodology

functions

to the design of a wireless sensor node shows the validity of the

IP blocks

and

approach and its simulation overhead. Index Terms-UML, Sequence diagram, MARTE, VSL, Sys­ temC/TLM, timing constraint.

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Fig. 1.

Proposed verification flow from UML/MARTE sequence diagram

INTRODUCTION

In the last years, Model-Driven Design and UML have gained an increasing attention for electronic system design. The most comprehensive effort towards a UML profile sup­ porting all the required concepts for real-time, embedded system design is MARTE (UML Profile for Modelling and Analysis of Real-time and Embedded Systems) [6]. The generation of executable code from UML diagrams is a growing area of interest due to its benefits essentially for design verification. The problem was firstly investigated in [9], which presented the benefits of combining UMLlSysML and SystemC, as a common and structured environment for system documentation and specification. The approaches in [4] cope with direct code generation by taking the UML model as Metadata Interchange file for the translation into Systemc. Habibi [3] suggested to generate the SystemC model by trans­ forming the UML model into an intermediate representation as state machine. UML 2.0 profile for SystemC [7] provides a graphical entry to SystemC designers, with a special attention to the code generation and back annotation capabilities. Most of the literature focuses on UML structural diagrams (e.g., composition diagrams) while behavioral diagrams (e.g., state charts and sequence diagrams) are not used to generate an executable model of the internal functionality of the system. Sequence diagrams are used to describe time-ordered data exchanges between system components. The work in [2] is a first contribution in the generation of an executable model of the system from UML sequence diagrams; however the generation of code describing system behavior is not enough for its verification since assertions should be also generated, i.e., code which checks system properties and eventually rises warnmg messages.

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UML sequence diagrams allow to specify "invariants", i.e., properties about system variables; furthermore, MARTE profile introduces a way to express time constraints between points of the sequence diagram. What is missing in this context is a methodology: •

•

•

to generate SystemC code from sequence diagrams with emphasis on simulation efficiency; to express timing observations and to check constraints inside SystemC as currently done by the Open Verifica­ tion Library (OVL) [1] for other HDLs; to generate SystemC assertions from invariants and time constraints.

The proposed work aims at filling these gaps by: •

•

•

showing the rules for the automatic generation of Sys­ temC/TLM transactions from UML sequence diagram interactions; creating C++ classes to manage time observation and their evaluation; finding a strategy to generate SystemC assertions from UML invariants and MARTE time constraints and to call them in the right position of the code.

The whole verification flow derived from this approach is depicted in Figure 1. The UMLIMARTE sequence diagrams describe both the behavior of the system (in terms of data exchanging between components) and the constraints it must satisfy. From this description a SystemCI1LM executable model is generated containing the assertion calls to check constraints (this step is the contribution of the paper). These entities should be linked to an external library providing the implementation in terms of either C/C++ functions or RTL IP

V

sd: Specification

cores. Simulation takes as input a suitable set of test benches and generates a trace in which failed constraints are reported. As a result of the verification process, new model information are obtained to refine the UML model and the constraints. The paper is organized as follows. Section II introduces sequence diagrams, time expression language and System­ CffLM modeling. Section III presents the proposed trans­ formation rules from sequence diagrams to SystemC/TLM code. Section IV experimentally validates the methodology by applying it to the design of a wireless sensor node and Section V draws some conclusions. II.

BACKGROUND

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Transaction-level modeling (TLM) is a high-level approach to model digital systems where details about the communi­ cation among modules are separated from the implementation details of functional units [8]. Two modeling styles are defined in TLM 2.0, i.e., Loosely Timed and Approximated Timed. The Loosely Timed (LT) modeling style is targeted for system and platform models, where data and timing are loosely con­ nected. TLM2.0 defines two timing points, the beginning time

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