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M
MCP3204/3208
2.7V 4-Channel/8-Channel 12-Bit A/D Converters with SPI™ Serial Interface Features
Description
• • • • • •
The Microchip Technology Inc. MCP3204/3208 devices are successive approximation 12-bit Analogto-Digital (A/D) Converters with on-board sample and hold circuitry. The MCP3204 is programmable to provide two pseudo-differential input pairs or four singleended inputs. The MCP3208 is programmable to provide four pseudo-differential input pairs or eight singleended inputs. Differential Nonlinearity (DNL) is specified at ±1 LSB, while Integral Nonlinearity (INL) is offered in ±1 LSB (MCP3204/3208-B) and ±2 LSB (MCP3204/3208-C) versions.
• • • • • •
• •
12-bit resolution ± 1 LSB max DNL ± 1 LSB max INL (MCP3204/3208-B) ± 2 LSB max INL (MCP3204/3208-C) 4 (MCP3204) or 8 (MCP3208) input channels Analog inputs programmable as single-ended or pseudo-differential pairs On-chip sample and hold SPI serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 100 ksps max. sampling rate at V DD = 5V 50 ksps max. sampling rate at VDD = 2.7V Low power CMOS technology: - 500 nA typical standby current, 2 µA max. - 400 µA max. active current at 5V Industrial temp range: -40°C to +85°C Available in PDIP, SOIC and TSSOP packages
Applications • • • •
Communication with the devices is accomplished using a simple serial interface compatible with the SPI protocol. The devices are capable of conversion rates of up to 100 ksps. The MCP3204/3208 devices operate over a broad voltage range (2.7V - 5.5V). Low current design permits operation with typical standby and active currents of only 500 nA and 320 µA, respectively. The MCP3204 is offered in 14-pin PDIP, 150 mil SOIC and TSSOP packages. The MCP3208 is offered in 16-pin PDIP and SOIC packages.
Functional Block Diagram
Sensor Interface Process Control Data Acquisition Battery Operated Systems
VDD
CH0 CH1
Package Types PDIP, SOIC, TSSOP 1 2 3 4 5 6 7
MCP3204
CH0 CH1 CH2 CH3 NC NC DGND
14 13 12 11 10 9 8
VDD VREF AGND CLK DOUT DIN CS/SHDN
PDIP, SOIC
Input Channel Mux
DAC
CH7*
Comparator 12-Bit SAR
Sample and Hold Control Logic
CS/SHDN DIN 1 2 3 4 5 6 7 8
MCP3208
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
16 15 14 13 12 11 10 9
2002 Microchip Technology Inc.
VSS
VREF
VDD VREF AGND CLK DOUT DIN
CLK
Shift Register
DOUT
* Note: Channels 5-7 available on MCP3208 Only
CS/SHDN DGND
DS21298C-page 1
MCP3204/3208 1.0
ELECTRICAL CHARACTERISTICS
PIN FUNCTION TABLE Name
Absolute Maximum Ratings*
VDD
Function +2.7V to 5.5V Power Supply
VDD...................................................................................7.0V
DGND
Digital Ground
All inputs and outputs w.r.t. VSS ............... -0.6V to VDD +0.6V
AGND
Analog Ground
Storage temperature .....................................-65°C to +150°C
CH0-CH7
Analog Inputs
Ambient temp. with power applied ................-65°C to +125°C
CLK
Serial Clock
Soldering temperature of leads (10 seconds) ............. +300°C
DIN
Serial Data In
DOUT
Serial Data Out
CS/SHDN
Chip Select/Shutdown Input
VREF
Reference Voltage Input
ESD protection on all pins.............................................> 4 kV *Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, V SS = 0V, VREF = 5V, TAMB = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE Parameters
Sym
Min
Typ
Max
Units
tCONV
—
—
12
clock cycles
Conditions
Conversion Rate Conversion Time Analog Input Sample Time
tSAMPLE
Throughput Rate
fSAMPLE
— —
— —
Integral Nonlinearity
INL
— —
Differential Nonlinearity
DNL
1.5
clock cycles 100 50
ksps ksps
VDD = VREF = 5V VDD = VREF = 2.7V
±0.75 ±1.0
±1 ±2
LSB
MCP3204/3208-B MCP3204/3208-C
—
±0.5
±1
LSB
No missing codes over-temperature
Offset Error
—
±1.25
±3
LSB
Gain Error
—
±1.25
±5
LSB
Total Harmonic Distortion
—
-82
—
dB
VIN = 0.1V to 4.9V@1 kHz
Signal to Noise and Distortion (SINAD)
—
72
—
dB
VIN = 0.1V to 4.9V@1 kHz
Spurious Free Dynamic Range
—
86
—
dB
VIN = 0.1V to 4.9V@1 kHz
Voltage Range
0.25
—
VDD
V
Note 2
Current Drain
— —
100 0.001
150 3.0
µA µA
CS = VDD = 5V
DC Accuracy Resolution
12
bits
Dynamic Performance
Reference Input
Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, particularly at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”, for more information.
DS21298C-page 2
2002 Microchip Technology Inc.
MCP3204/3208 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, V SS = 0V, VREF = 5V, TAMB = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Voltage Range for CH0CH7 in Single-Ended Mode
VSS
—
VREF
V
Input Voltage Range for IN+ in pseudo-differential Mode Input Voltage Range for IN- in pseudo-differential Mode
IN-
—
VREF+IN-
VSS-100
—
VSS+100
mV
Leakage Current
—
0.001
±1
µA
Switch Resistance
—
1000
—
Ω
See Figure 4-1
Sample Capacitor
—
20
—
pF
See Figure 4-1
Analog Inputs
Digital Input/Output Data Coding Format High Level Input Voltage
Straight Binary VIH
0.7 VDD
—
—
V
—
0.3 VDD
V
—
—
V
Low Level Input Voltage
VIL
—
High Level Output Voltage
VOH
4.1
Low Level Output Voltage
VOL
—
—
0.4
V
Input Leakage Current
ILI
-10
—
10
µA
Output Leakage Current
ILO
-10
—
10
µA
CIN,COUT
—
—
10
pF
Clock Frequency
fCLK
— —
— —
2.0 1.0
MHz MHz
Clock High Time
tHI
250
—
—
ns
Pin Capacitance (All Inputs/Outputs)
IOH = -1 mA, VDD = 4.5V IOL = 1 mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD VDD = 5.0V (Note 1) TAMB = 25°C, f = 1 MHz
Timing Parameters VDD = 5V (Note 3) VDD = 2.7V (Note 3)
tLO
250
—
—
ns
tSUCS
100
—
—
ns
tSU
—
—
50
ns
Data Input Hold Time
tHD
—
—
50
ns
CLK Fall To Output Data Valid
tDO
—
—
200
ns
See Figures 1-2 and 1-3
CLK Fall To Output Enable
tEN
—
—
200
ns
See Figures 1-2 and 1-3
CS Rise To Output Disable
tDIS
—
—
100
ns
See Figures 1-2 and 1-3
CS Disable Time
Clock Low Time CS Fall To First Rising CLK Edge Data Input Setup Time
tCSH
500
—
—
ns
DOUT Rise Time
tR
—
—
100
ns
See Figures 1-2 and 1-3 (Note 1)
DOUT Fall Time
tF
—
—
100
ns
See Figures 1-2 and 1-3 (Note 1)
Operating Voltage
VDD
2.7
—
5.5
V
Operating Current
IDD
— —
320 225
400 —
µA
VDD=VREF = 5V, DOUT unloaded VDD=VREF = 2.7V, DOUT unloaded
Standby Current
IDDS
—
0.5
2.0
µA
CS = VDD = 5.0V
Power Requirements
Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, particularly at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”, for more information.
2002 Microchip Technology Inc.
DS21298C-page 3
MCP3204/3208 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, V SS = 0V, VREF = 5V, TAMB = -40°C to +85°C,fSAMPLE = 100 ksps and fCLK = 20*fSAMPLE Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+85
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 14L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
108
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Thermal Resistance, 16L-PDIP
θJA
—
70
—
°C/W
Thermal Resistance, 16L-SOIC
θJA
—
90
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistance
Note 1: This parameter is established by characterization and not 100% tested. 2: See graphs that relate linearity performance to VREF levels. 3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, particularly at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”, for more information. tCSH CS
tSUCS tHI
tLO
CLK tSU DIN
tHD
MSB IN tEN
DOUT
FIGURE 1-1:
DS21298C-page 4
tR
tDO Null Bit
MSB OUT
tF
tDIS LSB
Serial Interface Timing.
2002 Microchip Technology Inc.
MCP3204/3208 Test Point
1.4V
VDD 3 kΩ
Test Point
3 kΩ
tDIS Waveform 2
VDD /2
tEN Waveform
DOUT
DOUT
100 pF
CL = 100 pF
tDIS Waveform 1
VSS
Voltage Waveforms for tR , tF
Voltage Waveforms for tEN VOH VOL
D OUT
CS tF
tR
1
CLK
2
3
4
Voltage Waveforms for tDO B11
DOUT CLK
tEN tDO
DOUT
Voltage Waveforms for tDIS CS
FIGURE 1-2:
Load Circuit for tR, tF, tDO.
VIH
DOUT Waveform 1*
90% TDIS
DOUT
10%
Waveform 2† * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. † Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control.
FIGURE 1-3:
2002 Microchip Technology Inc.
Load circuit for tDIS and tEN.
DS21298C-page 5
MCP3204/3208 2.0
TYPICAL PERFORMANCE CHARACTERISTICS
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = V REF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C. 1.0
2.0
0.8
Positive INL
1.0
INL (LSB)
0.4
INL (LSB)
VDD = VREF = 2.7 V
1.5
0.6 0.2 0.0 -0.2
Positive INL
0.5 0.0
-0.5
-0.4
Negative INL
Negative INL
-1.0
-0.6
-1.5
-0.8
-2.0
-1.0 0
25
50
75
100
125
0
150
10
20
Sample Rate (ksps)
FIGURE 2-1: vs. Sample Rate.
Integral Nonlinearity (INL)
50
60
70
80
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). 2.0
2.0
1.5
1.5
Positive INL
1.0
1.0
Positive INL
INL (LSB)
INL (LSB)
40
Sample Rate (ksps)
2.5
0.5 0.0 -0.5 -1.0
Negative INL
0.5 0.0 -0.5 -1.0
-1.5
Negative INL
-1.5
-2.0 0
1
2
3
4
-2.0
5
0.0
VREF (V)
FIGURE 2-2: vs. VREF.
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
Integral Nonlinearity (INL)
FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF (VDD = 2.7V).
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
INL (LSB)
INL (LSB)
30
0.2 0.0 -0.2
VDD = VREF = 2.7 V FSAMPLE = 50 ksps
0.2 0.0 -0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8 -1.0
-1.0 0
512
1024
1536
2048
2560
3072
3584
4096
Digital Code
FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).
DS21298C-page 6
0
512
1024
1536
2048
2560
3072
3584
4096
Digital Code
FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V).
2002 Microchip Technology Inc.
MCP3204/3208 Note: Unless otherwise indicated, VDD = V REF = 5 V, VSS = 0 V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C. 1.0
1.0 0.6
0.6
0.4
0.4
0.2 0.0 Negative INL
-0.2
VDD = VREF = 2.7 V FSAMPLE = 50 ksps
0.8
Positive INL
INL (LSB)
INL (LSB)
0.8
Positive INL
0.2 0.0 -0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
Negative INL
-1.0
-1.0 -50
-25
0
25
50
75
-50
100
-25
0
Temperature (°C)
FIGURE 2-7: vs. Temperature.
Integral Nonlinearity (INL)
1.0
2.0
0.8
1.5
75
100
VDD = VREF = 2.7 V
1.0
0.4
DNL (LSB)
DNL (LSB)
50
FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V).
0.6 0.2 Positive DNL
0.0 -0.2 -0.4
0.5 Positive DNL
0.0 -0.5
Negative DNL
-1.0
Negative DNL
-0.6
-1.5
-0.8 -1.0
-2.0 0
25
50
75
100
125
150
0
10
Sample Rate (ksps)
2.0
2.0
DNL (LSB)
3.0
Positive DNL
0.0 Negative DNL
-1.0
30
40
50
60
70
80
FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V).
3.0
1.0
20
Sample Rate (ksps)
FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate.
DNL (LSB)
25
Temperature (°C)
-2.0
VDD = VREF = 2.7 V FSAMPLE = 50 ksps Positive DNL
1.0 0.0
Negative DNL
-1.0 -2.0
-3.0
-3.0 0
1
2
3
4
VREF (V)
FIGURE 2-9: (DNL) vs. VREF.
Differential Nonlinearity
2002 Microchip Technology Inc.
5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VREF (V)
FIGURE 2-12: Differential Nonlinearity (DNL) vs. VREF (VDD = 2.7V).
DS21298C-page 7
MCP3204/3208 1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
DNL (LSB)
Note: Unless otherwise indicated, VDD = V REF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C.
0.2 0.0 -0.2 -0.4
0.2 0.0 -0.2 -0.4
-0.6
-0.6
-0.8
-0.8
-1.0
VDD = VREF = 2.7 V FSAMPLE = 50 ksps
-1.0 0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
Digital Code
FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part).
1.0
0.8
0.8
0.6
0.6
DNL (LSB)
DNL (LSB)
0.0
-0.2 Negative DNL
-0.6
3584
4096
Positive DNL
0.2 0.0 -0.2 -0.4
Negative DNL
-0.6
-0.8
-0.8
-1.0
-1.0 -50
-25
0
25
50
75
100
-50
-25
Temperature (°C)
0
25
50
75
100
Temperature (°C)
FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature.
FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V).
4
20
3
18
VDD = VREF = 2.7 V FSAMPLE = 50 ksps
2
Offset Error (LSB)
Gain Error (LSB)
3072
VDD = VREF = 2.7 V FSAMPLE = 50 ksps
0.4
Positive DNL
0.2
-0.4
2560
FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V).
1.0
0.4
2048
Digital Code
1 0 -1 -2
VDD = VREF = 5 V FSAMPLE = 100 ksps
-3
16 VDD = VREF = 5V FSAMPLE = 100 ksps
14 12 10 8
VDD = VREF = 2.7V FSAMPLE = 50 ksps
6 4 2
-4
0 0
1
2
3
4
VREF (V)
FIGURE 2-15:
DS21298C-page 8
Gain Error vs. VREF.
5
0
1
2
3
4
5
VREF (V)
FIGURE 2-18:
Offset Error vs. VREF.
2002 Microchip Technology Inc.
MCP3204/3208 Note: Unless otherwise indicated, VDD = V REF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C. 2.0
0.2 VDD = VREF = 2.7 V FSAMPLE = 50 ksps
-0.2
1.8
Offset Error (LSB)
Gain Error (LSB)
0.0 -0.4 -0.6 -0.8 -1.0
VDD = VREF = 5 V FSAMPLE = 100 ksps
-1.2 -1.4
VDD = VREF = 5 V FSAMPLE = 100 ksps
1.6 1.4 1.2 1.0
VDD = VREF = 2.7 V FSAMPLE = 50 ksps
0.8 0.6 0.4 0.2
-1.6
0.0
-1.8 -50
-25
0
25
50
75
-50
100
-25
0
Temperature (°C)
FIGURE 2-19:
Gain Error vs. Temperature.
100 80
FIGURE 2-22: Temperature.
80
SFDR (dB)
SNR (dB)
60 50 VDD = VREF = 2.7V FSAMPLE = 50 ksps
30
100
70 60 VDD = VREF = 2.7 V FSAMPLE = 50 ksps
50 40 30
20
20
10
10
0
0 1
10
Input Frequency (kHz)
FIGURE 2-20: Input Frequency.
100
Signal to Noise (SNR) vs.
1
10
100
Input Frequency (kHz)
FIGURE 2-23: Signal to Noise and Distortion (SINAD) vs. Input Frequency.
0
80
-10
VDD = VREF = 5 V FSAMPLE = 100 ksps
70
-20 -30
60
VDD = VREF = 2.7V FSAMPLE = 50 ksps
-40
SINAD (dB)
THD (dB)
75
VDD = VREF = 5 V FSAMPLE = 100 ksps
90
70
40
50
Offset Error vs.
100
VDD = VREF = 5 V FSAMPLE = 100 ksps
90
25
Temperature (°C)
-50 -60 -70
50
VDD = VREF = 2.7 V FSAMPLE = 50 ksps
40 30 20
-80
V DD = VREF = 5V FSAMPLE = 100 ksps
-90
10
-100
0 1
10
Input Frequency (kHz)
100
FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency.
2002 Microchip Technology Inc.
-40
-35
-30
-25
-20
-15
-10
-5
0
Input Signal Level (dB)
FIGURE 2-24: Signal to Noise and Distortion (SINAD) vs. Input Signal Level.
DS21298C-page 9
MCP3204/3208
12.0
12.00 11.75 11.50 11.25 11.00 10.75 10.50 10.25 10.00 9.75 9.50 9.25 9.00
11.5 11.0
ENOB (rms)
ENOB (rms)
Note: Unless otherwise indicated, VDD = V REF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C.
VDD = VREF = 5 V FSAMPLE =100 ksps
VDD = VREF = 2.7 V FSAMPLE = 50 ksps
10.5
VDD = VREF = 5 V FSAMPLE = 100 ksps
10.0 9.5 VDD = VREF = 2.7 V FSAMPLE = 50 ksps
9.0 8.5 8.0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1
VREF (V)
FIGURE 2-25: (ENOB) vs. VREF.
Effective Number of Bits
100
FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.
Power Supply Rejection (dB)
0
100
VDD = VREF = 5 V FSAMPLE = 100 ksps
90 80
SFDR (dB)
10
Input Frequency (kHz)
70 60 V DD = VREF = 2.7 V FSAMPLE = 50 ksps
50 40 30 20 10 0
10
Input Frequency (kHz)
FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
Amplitude (dB)
VDD = VREF = 5 V FSAMPLE = 100 ksps FINPUT = 9.985 kHz 4096 points
0
10000
20000
30000
Frequency (Hz)
40000
50000
FIGURE 2-27: Frequency Spectrum of 10 kHz input (Representative Part).
DS21298C-page 10
-20 -30 -40 -50 -60 -70 -80 1
100
10
100
1000
10000
Ripple Frequency (kHz)
FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency.
Amplitude (dB)
1
-10
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130
VDD = VREF = 2.7 V FSAMPLE = 50 ksps FINPUT = 998.76 Hz 4096 points
0
5000
10000
15000
20000
25000
Frequency (Hz)
FIGURE 2-30: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V).
2002 Microchip Technology Inc.
MCP3204/3208 Note: Unless otherwise indicated, VDD = V REF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C. 500
100 VREF = VDD All points at FCLK = 2 MHz, except at VREF = VDD = 2.5 V, FCLK = 1 MHz
450 400
80 70
300
IREF (µA)
IDD (µA)
350
V REF = VDD All points at FCLK = 2 MHz except at V REF = VDD = 2.5 V, FCLK = 1 MHz
90
250 200
60 50 40
150
30
100
20
50
10
0
0 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
VDD (V)
IDD vs. VDD.
FIGURE 2-31:
5.0
5.5
6.0
100 90
350
VDD = VREF = 5 V
80
300
70
VDD = VREF = 5 V
250 200
IREF (µA)
IDD (µA)
4.5
IREF vs. VDD.
FIGURE 2-34:
400
VDD = VREF = 2.7 V
150
60 50 40
VDD = VREF = 2.7 V
30
100
20
50
10 0
0 10
100
1000
10
10000
100
Clock Frequency (kHz)
FIGURE 2-32:
1000
IDD vs. Clock Frequency.
IREF vs. Clock Frequency.
FIGURE 2-35: 100
VDD = VREF = 5 V FCLK = 2 MHz
350
10000
Clock Frequency (kHz)
400
VDD = VREF = 5 V FCLK = 2 MHz
90 80
300
70
250
IREF (µA)
IDD (µA)
4.0
VDD (V)
200 VDD = VREF = 2.7 V FCLK = 1 MHz
150
60 50 40
VDD = VREF = 2.7 V FCLK = 1 MHz
30
100
20
50
10
0
0 -50
-25
0
25
50
75
100
-50
-25
Temperature (°C)
FIGURE 2-33:
IDD vs. Temperature.
2002 Microchip Technology Inc.
0
25
50
75
100
Temperature (°C)
FIGURE 2-36:
IREF vs. Temperature.
DS21298C-page 11
MCP3204/3208 Note: Unless otherwise indicated, VDD = V REF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 20* fSAMPLE,TA = 25°C. 2.0
70
Analog Input Leakage (nA)
80 VREF = CS = VDD
IDDS (pA)
60 50 40 30 20 10 0
1.8 1.6 1.4 1.2
VDD = VREF = 5 V FCLK = 2 MHz
1.0 0.8 0.6 0.4 0.2 0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-39: Analog Input Leakage Current vs. Temperature.
IDDS vs. VDD.
FIGURE 2-37:
-50
100.00 VDD = VREF = CS = 5 V
IDDS (nA)
10.00
1.00
0.10
0.01 -50
-25
0
25
50
75
100
Temperature (°C)
FIGURE 2-38:
DS21298C-page 12
IDDS vs. Temperature.
2002 Microchip Technology Inc.
MCP3204/3208 3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Name VDD
Function
3.7
Chip Select/Shutdown (CS/SHDN)
The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions.
+2.7V to 5.5V Power Supply
DGND
Digital Ground
4.0
AGND
Analog Ground
CH0-CH7
Analog Inputs
The MCP3204/3208 A/D converters employ a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the fourth rising edge of the serial clock after the start bit has been received. Following this sample time, the device uses the collected charge on the internal sample/hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3204/3208. See Section 6.2, “Maintaining Minimum Clock Speed”, for information on minimum clock rates. Communication with the device is accomplished using a 4-wire SPIcompatible interface.
CLK
Serial Clock
DIN
Serial Data In
DOUT
Serial Data Out
CS/SHDN
Chip Select/Shutdown Input
VREF
Reference Voltage Input
3.1
DGND
Digital ground connection to internal digital circuitry.
3.2
AGND
Analog ground connection to internal analog circuitry.
3.3
CH0 - CH7
Analog inputs for channels 0 - 7 for the multiplexed inputs. Each pair of channels can be programmed to be used as two independent channels in single-ended mode or as a single pseudo-differential input, where one channel is IN+ and one channel is IN. See Section 4.1, “Analog Inputs”, and Section 5.0, “Serial Communications”, for information on programming the channel configuration.
3.4
Serial Clock (CLK)
The SPI clock pin is used to initiate a conversion and clock out each bit of the conversion as it takes place. See Section 6.2, “Maintaining Minimum Clock Speed”, for constraints on clock speed.
3.5
Serial Data Input (D IN)
The SPI port serial data input pin is used to load channel configuration data into the device.
3.6
Serial Data Output (DOUT)
The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place.
2002 Microchip Technology Inc.
4.1
DEVICE OPERATION
Analog Inputs
The MCP3204/3208 devices offer the choice of using the analog input channels configured as single-ended inputs or pseudo-differential pairs. The MCP3204 can be configured to provide two pseudo-differential input pairs or four single-ended inputs, while the MCP3208 can be configured to provide four pseudo-differential input pairs or eight single-ended inputs. Configuration is done as part of the serial command before each conversion begins. When used in the pseudo-differential mode, each channel pair (i.e., CH0 and CH1, CH2 and CH3 etc.) is programmed to be the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to (VREF + IN). The IN- input is limited to ±100 mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be FFFh. If the voltage level at INis more than 1 LSB below VSS, the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, then the FFFh code will not be seen unless the IN+ input level goes above VREF level. For the A/D converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1.
DS21298C-page 13
MCP3204/3208 EQUATION
This diagram illustrates that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly effecting the time that is required to charge the capacitor (Csample). Consequently, larger source impedances increase the offset, gain and integral linearity errors of the conversion (see Figure 4-2).
4.2
4096 × V IN Digital Output Code = --------------------------V REF VIN = analog input voltage VREF = reference voltage
Reference Input
When using an external voltage reference device, the system designer should always refer to the manufacturer’s recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the operation of the A/D converter.
For each device in the family, the reference input (VREF) determines the analog input voltage range. As the reference input is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D converter is a function of the analog input signal and the reference input, as shown below. VDD
RSS
VT = 0.6V
CHx
CPIN 7 pF
VA
Sampling Switch SS
RS = 1 kΩ
ILEAKAGE ±1 nA
VT = 0.6V
C SAMPLE = DAC capacitance = 20 pF VSS
Legend VA
=
Signal Source
Ileakage
=
Leakage Current At The Pin Due To Various Junctions
Rss
=
Source Impedance
SS
=
Sampling switch
CHx
=
Input Channel Pad
Rs
=
Sampling switch resistor
Cpin
=
Input Pin Capacitance
Csample
=
Sample/hold capacitance
Vt
=
Threshold Voltage
FIGURE 4-1:
Analog Input Model.
Clock Frequency (MHz)
2.5 V DD = 5 V 2.0 1.5 1.0 VDD = 2.7 V 0.5 0.0 100
1000
10000
Input Resistance (Ohms)
FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (R S) to maintain less than a 0.1 LSB deviation in INL from nominal conditions.
DS21298C-page 14
2002 Microchip Technology Inc.
MCP3204/3208 5.0
SERIAL COMMUNICATIONS
Communication with the MCP3204/3208 devices is accomplished using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low (see Figure 5-1). If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and D IN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using single-ended or differential input mode. The next three bits (D0, D1 and D2) are used to select the input channel configuration. Table 5-1 and Table 5-2 show the configuration bits for the MCP3204 and MCP3208, respectively. The device will begin to sample the analog input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. Once the D0 bit is input, one more clock is required to complete the sample and hold period (D IN is a “don’t care” for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 12 clocks will output the result of the conversion with MSB first, as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 for more details on using the MCP3204/ 3208 devices with hardware SPI ports.
2002 Microchip Technology Inc.
TABLE 5-1:
CONFIGURATION BITS FOR THE MCP3204
Control Bit Selections
Input Configuration Single/ D2* D1 D0 Diff
Channel Selection
1
X
0
0
single-ended
CH0
1
X
0
1
single-ended
CH1
1
X
1
0
single-ended
CH2
1
X
1
1
single-ended
CH3
0
X
0
0
differential
CH0 = IN+ CH1 = IN-
0
X
0
1
differential
CH0 = INCH1 = IN+
0
X
1
0
differential
CH2 = IN+ CH3 = IN-
0
X
1
1
differential
CH2 = INCH3 = IN+
* D2 is a “don’t care” for MCP3204
TABLE 5-2:
CONFIGURATION BITS FOR THE MCP3208
Control Bit Selections
Input Configuration
Channel Selection
0
single-ended
CH0
1
single-ended
CH1
1
0
single-ended
CH2
0
1
1
single-ended
CH3
1
0
0
single-ended
CH4
1
1
0
1
single-ended
CH5
1
1
1
0
single-ended
CH6
1
1
1
1
single-ended
CH7
0
0
0
0
differential
CH0 = IN+ CH1 = IN-
0
0
0
1
differential
CH0 = INCH1 = IN+
0
0
1
0
differential
CH2 = IN+ CH3 = IN-
0
0
1
1
differential
CH2 = INCH3 = IN+
0
1
0
0
differential
CH4 = IN+ CH5 = IN-
0
1
0
1
differential
CH4 = INCH5 = IN+
0
1
1
0
differential
CH6 = IN+ CH7 = IN-
0
1
1
1
differential
CH6 = INCH7 = IN+
Single /Diff
D2
1
0
0
1
0
0
1
0
1 1
D1 D0
DS21298C-page 15
MCP3204/3208 tCYC
tCYC tCSH
CS tSUCS CLK
SGL/
DIN
Start DIFF D2
D1 D0
HI-Z
DOUT
Start SGL/ DIFF D2
Don’t Care
Null Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
HI-Z
tCONV tSAMPLE
tDATA **
* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output LSB first data, followed by zeros indefinitely (see Figure 5-2 below). ** tDATA: during this time, the bias current and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-1:
Communication with the MCP3204 or MCP3208.
tCYC tCSH
CS tSUCS
Power Down
CLK Start DIN
D2 D1 D0
Don’t Care
SGL/ DIFF
DOUT
HI-Z
* Null B11B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11 Bit
HI-Z
(MSB) tSAMPLE
tCONV
tDATA **
* After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out LSB first data or zeroes.
FIGURE 5-2:
DS21298C-page 16
Communication with MCP3204 or MCP3208 in LSB First Format.
2002 Microchip Technology Inc.
MCP3204/3208 6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3204/3208 with Microcontroller (MCU) SPI Ports
With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Because communication with the MCP3204/ 3208 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending ‘leading zeros’ before the start bit. As an example, Figure 6-1 and Figure 6-2 illustrate how the MCP3204/3208 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure 6-2 shows the similar case of SPI Mode 1,1, where the clock idles in the ‘high’ state. As is shown in Figure 6-1, the first byte transmitted to the A/D converter contains five leading zeros before the start bit. Arranging the leading zeros this way allows the output 12 bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D converter on the falling edge of clock number 12. Once the second eight clocks have been sent to the device, the MCU’s receive buffer will contain three unknown bits (the output is at high impedance for the first two clocks), the null bit and the highest order four bits of the conversion. Once the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Employing this method ensures simpler manipulation of the converted data. Figure 6-2 shows the same thing in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D converter outputs data on the falling edge of the clock and the MCU latches data from the A/D converter in on the rising edge of the clock.
2002 Microchip Technology Inc.
DS21298C-page 17
MCP3204/3208 CS MCU latches data from A/D converter on rising edges of SCLK SCLK
1
2
3
4
5
6
7
8
9
10
11 12 13 14
15 16
17 18
19 20
21 22
23 24
Data is clocked out of A/D converter on falling edges SGL/ Start DIFF D2
DIN
D1
DO
Don’t Don’tCare Care
NULL BIT B11 B10 B9 B8
HI-Z
DOUT
Start Bit MCU Transmitted Data SGL/ SGL/ D2 (Aligned with falling 0 0 0 0 0 1 DIFF DIFF D2 edge of clock) MCU Received Data (Aligned with rising ? ? ? ? ? ? ? ? edge of clock) Data stored into MCU receive register after transmission of first X = “Don’t Care” Bits 8 bits
FIGURE 6-1:
D1 DO D1 DO ? ?
X
X
X
X
X
X
X
0 ? 0 B11 B10 B9 B8 ? (Null) B11 B10 B9 B8
? ?
B6 B5 B4 B3 B2 B1 B0
B7
X
X
X
X
X
X
X
B7 B6 B6 B5 B5 B4 B4 B3 B3 B2 B2 B1 B1 B0 B0 B7
Data stored into MCU receive register after transmission of last 8 bits
Data stored into MCU receive register after transmission of second 8 bits
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
CS MCU latches data from A/D converter on rising edges of SCLK SCLK
1
2
3
4
5
6
7
8
9
10
11 12 13 14
15
16
17 18 19
20 21 22 23
24
Data is clocked out of A/D converter on falling edges SGL/
DIN
Start DIFF
FIGURE 6-2:
DS21298C-page 18
NULL BIT B11 B10 B9
B8
B7 B6 B5 B4 B3 B2 B1 B0
Start Bit
MCU Transmitted Data (Aligned with falling 0 edge of clock)
X = “Don’t Care” Bits
Don’t Care
D1 DO
HI-Z
DOUT
MCU Received Data (Aligned with rising edge of clock)
D2
0 ?
0 ?
0 ?
1 SGL/ DIFF D2
0 ?
?
?
?
D1 DO
?
Data stored into MCU receive register after transmission of first 8 bits
?
?
X
X
X
X
X
X
0 B11 B10 B9 B8 ? (Null)
Data stored into MCU receive register after transmission of second 8 bits
X
X
X
X
X
X
X
X
B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of last 8 bits
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
2002 Microchip Technology Inc.
MCP3204/3208 6.2
Maintaining Minimum Clock Speed
6.3
When the MCP3204/3208 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample capacitor while the conversion is taking place. At 85°C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2 ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 kHz). Failure to meet this criterion may introduce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met.
Buffering/Filtering the Analog Inputs
If the signal source for the A/D converter is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur (see Figure 4-2). It is also recommended that a filter be used to eliminate any signals that may be aliased back into the conversion results, as is illustrated in Figure 6-3, where an op amp is used to drive the analog input of the MCP3204/3208. This amplifier provides a low impedance source for the converter input, and a low pass filter, which eliminates unwanted high frequency noise. Low pass (anti-aliasing) filters can be designed using Microchip’s free interactive FilterLab™ software. FilterLab will calculate capacitor and resistor values, as well as determine the number of poles that are required for the application. For more information on filtering signals, see AN699, “Anti-Aliasing Analog Filters for Data Acquisition Systems”.
VDD 10 µF
4.096V Reference 0.1 µF
MCP1541
1 µF 1 µF IN+
VREF MCP3204
VIN
R1
C1
MCP601
IN-
+ R2
-
C2 R3
R4
FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a second order anti-aliasing filter for the signal being converted by the MCP3204.
2002 Microchip Technology Inc.
DS21298C-page 19
MCP3204/3208 6.4
Layout Considerations
6.5
When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device, placed as close as possible to the device pin. A bypass capacitor value of 1 µF is recommended. Digital and analog traces should be separated as much as possible on the board, with no traces running underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a “star” configuration can also reduce noise by eliminating return current paths and associated errors (see Figure 6-4). For more information on layout tips when using A/D converters, refer to AN688, “Layout Tips for 12-Bit A/D converter Applications”. VDD
The MCP3204/3208 devices provide both digital and analog ground connections to provide another means of noise reduction. As shown in Figure 6-5, the analog and digital circuitry is separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate, which has a resistance of 5 -10Ω. If no ground plane is utilized, then both grounds must be connected to VSS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be connected to the analog ground plane. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D converter. VDD MCP3204/08
Connection
Device 4
Device 1
Utilizing the Digital and Analog Ground Pins
Digital Side
Analog Side
-SPI Interface -Shift Register -Control Logic
-Sample Cap -Capacitor Array -Comparator
Substrate 5 - 10Ω DGND
AGND 0.1 µF
Device 3 Analog Ground Plane Device 2
FIGURE 6-5: Separation of Analog and Digital Ground Pins. FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths.
DS21298C-page 20
2002 Microchip Technology Inc.
MCP3204/3208 7.0
PACKAGING INFORMATION
7.1
Package Marking Information 14-Lead PDIP (300 mil)
Example: MCP3204-B I/P YYWWNNN
XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
14-Lead SOIC (150 mil)
Example: MCP3204-B XXXXXXXXXXX YYWWNNN
XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
14-Lead TSSOP (4.4mm) *
Example:
XXXXXXXX
3204-C
YYWW
IYWW
NNN
NNN
* Please contact Microchip Factory for B-Grade TSSOP devices
Legend:
Note:
*
XX...X YY WW NNN
Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
2002 Microchip Technology Inc.
DS21298C-page 21
MCP3204/3208 Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3304)
Example: MCP3208-B I/P YYWWNNN
XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
16-Lead SOIC (150 mil) (MCP3304)
XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN
DS21298C-page 22
Example: MCP3208-B XXXXXXXXXX IYWWNNN
2002 Microchip Technology Inc.
MCP3204/3208 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2 n
1 α
E A2
A
L
c A1
β eB
B1 p
B
Units Dimension Limits n p
MIN
INCHES* NOM 14 .100 .155 .130
MAX
MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MIN
Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing § eB .310 .370 .430 α Mold Draft Angle Top 5 10 15 β Mold Draft Angle Bottom 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005
2002 Microchip Technology Inc.
MAX
4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15
DS21298C-page 23
MCP3204/3208 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E E1
p
D
2 B
n
1 α h 45°
c A2
A
φ A1
L β Units Dimension Limits n p
Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic
A A2 A1 E E1 D h L φ c B α β
MIN
.053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0
INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12
MAX
.069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15
MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12
MIN
MAX
1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065
DS21298C-page 24
2002 Microchip Technology Inc.
MCP3204/3208 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E E1 p
D 2 1
n B
α
A c
φ β
A1
L
Units Dimension Limits n p
Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic
A A2 A1 E E1 D L φ c B1 α β
MIN
.033 .002 .246 .169 .193 .020 0 .004 .007 0 0
INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5
A2
MAX
.043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10
MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10
MIN
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087
2002 Microchip Technology Inc.
DS21298C-page 25
MCP3204/3208 16-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2 n
α
1 E
A2
A
L
c A1
β
B1
eB
p
B Units Dimension Limits n p
INCHES* NOM 16 .100 .140 .155 .115 .130 .015 .300 .313 .240 .250 .740 .750 .125 .130 .008 .012 .045 .058 .014 .018 .310 .370 5 10 5 10
MIN
MAX
MILLIMETERS NOM 16 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 .036 0.46 7.87 9.40 5 10 5 10
MIN
Number of Pins Pitch Top to Seating Plane A .170 Molded Package Thickness .145 A2 Base to Seating Plane A1 Shoulder to Shoulder Width E .325 Molded Package Width E1 .260 Overall Length D .760 Tip to Seating Plane L .135 c Lead Thickness .015 Upper Lead Width B1 .070 Lower Lead Width B .022 eB Overall Row Spacing § .430 α Mold Draft Angle Top 15 β Mold Draft Angle Bottom 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-017
DS21298C-page 26
MAX
4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15
2002 Microchip Technology Inc.
MCP3204/3208 16-Lead Plastic Small Outline (SL) – Narrow 150 mil (SOIC)
E E1
p
D
2 B
n
1 α h 45°
c A2
A
φ L
A1
β Units Dimension Limits n p
Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic
A A2 A1 E E1 D h L φ c B α β
INCHES* NOM 16 .050 .053 .061 .052 .057 .004 .007 .228 .237 .150 .154 .386 .390 .010 .015 .016 .033 0 4 .008 .009 .013 .017 0 12 0 12
MIN
MAX
.069 .061 .010 .244 .157 .394 .020 .050 8 .010 .020 15 15
MILLIMETERS NOM 16 1.27 1.35 1.55 1.32 1.44 0.10 0.18 5.79 6.02 3.81 3.90 9.80 9.91 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.33 0.42 0 12 0 12
MIN
MAX
1.75 1.55 0.25 6.20 3.99 10.01 0.51 1.27 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-108
2002 Microchip Technology Inc.
DS21298C-page 27
MCP3204/3208 NOTES:
DS21298C-page 28
2002 Microchip Technology Inc.
MCP3204/3208 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape® or Microsoft® Internet Explorer. Files are also available for FTP download from our FTP site.
Connecting to the Microchip Internet Web Site The Microchip web site is available at the following URL: www.microchip.com
SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world.
092002
The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events
2002 Microchip Technology Inc.
DS21298C-page29
MCP3204/3208 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional): Would you like a reply? Device: MCP3204/3208
Y
N Literature Number: DS21298C
Questions: 1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21298C-page30
2002 Microchip Technology Inc.
MCP3204/08 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
X
X
/XX
Device
Grade
Temperature Range
Package
Device:
Grade:
MCP3204: 4-Channel 12-Bit Serial A/D MCP3204T: 4-Channel 12-Bit Serial A/D (Tape and Reel) MCP3208: 8-Channel 12-Bit Serial A/D MCP3208T: 8-Channel 12-Bit Serial A/D (Tape and Reel)
Examples:
Converter Converter Converter Converter
B C
= ±1 LSB INL = ±2 LSB INL
Temperature Range:
I
=
Package:
P SL ST
= Plastic DIP (300 mil Body), 14-lead, 16-lead = Plastic SOIC (150 mil Body), 14-lead, 16-lead = Plastic TSSOP (4.4mm), 14-lead
a)
MCP3204-BI/P: ±1 LSB INL, Industrial Temperature, PDIP package.
b)
MCP3204-BI/SL: ±1 LSB INL, Industrial Temperature, SOIC package.
c)
MCP3204-CI/ST: ±2 LSB INL, Industrial Temperature, TSSOP package.
a)
MCP3208-BI/P: ±1 LSB INL, Industrial Temperature, PDIP package.
b)
MCP3208-BI/SL: ±1 LSB INL, Industrial Temperature, SOIC package.
c)
MCP3208-CI/ST: ±2 LSB INL, Industrial Temperature, TSSOP package.
-40°C to +85°C
Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3.
Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
DS21298C-page31
MCP3204/08 NOTES:
DS21298C-page 32
2002 Microchip Technology Inc.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, K EELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21298C - page 33
M WORLDWIDE SALES AND SERVICE AMERICAS
ASIA/PACIFIC
Corporate Office
Australia
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com
Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Rocky Mountain
China - Beijing
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338
Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104
Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
Kokomo 2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387
Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
China - Chengdu Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599
China - Fuzhou Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
China - Shanghai Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - Shenzhen
150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335
Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086
San Jose
China - Hong Kong SAR
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
New York
Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O’Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
Japan Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE Austria Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393
Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
France Microchip Technology SARL Parc d’Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany Microchip Technology GmbH Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 08/01/02
DS21298C-page 34
2002 Microchip Technology Inc.
