Mechanically flexible double gate a-IGZO TFTs Niko Münzenrieder, Christoph Zysset, Thomas Kinkeldei, Luisa Petti, Giovanni A. Salvatore and Gerhard Tröster Institute for Electronics Swiss Federal Institute of Technology Zurich Zurich, 8092, Switzerland
[email protected] Abstract—In this paper, the concept of double gate transistors is applied to mechanically flexible amorphous Indium-GalliumZinc-Oxide (a-IGZO) thin film transistors (TFTs) fabricated on free standing plastic foils. Due to the temperature sensitivity of the plastic substrate, a-IGZO is a suitable semiconductor since it provides carrier mobilities of ≈ 10 cm2/Vs when deposited at room temperature. Double gate TFTs with connected bottom and top gate are compared to bottom gate reference TFTs fabricated on the same substrate. Double gate a-IGZO TFTs exhibit a by 74% increased gate capacitance, a by 0,7 V higher threshold voltage, and therefore an up to 51% increased transconductance. The subthreshold swing and the on/off current ratios are improved as well, and reach excellent values of 69 mV/dec and 2x109, respectively. The mechanical flexibility is demonstrated by showing device operation while the TFT is exposed to tensile strain of 0.55%, induced by bending to a radius of 5 mm.
I.
INTRODUCTION
Electronic devices, especially thin-film transistors (TFTs) fabricated directly on flexible plastic substrates are a key requirement for a number of new large-area applications such as rollable displays, electronic skins or woven electronics for smart textiles [1]. While organic [2] and a-Si [3] based TFTs fabricated on flexible and temperature sensitive substrates in general suffer from low mobilities around 1 cm2/Vs, a-IGZO TFTs are nearly unaffected by the choice of the substrate (rigid or flexible), and offer mobilities above 10 cm2/Vs even when deposited at room temperature [4]. Besides the mobility, there are other important parameters to take into account for device performance, such as threshold voltage Vth, on-off current ratio Ion/Ioff, and subthreshold swing SS. TFT performance parameters aim at a large Ion/Ioff, a small SS, and a Vth which allows TFT operation between 0 V and 5 V (essential for the fabrication of digital circuits). In the past, several groups used different double gate structures [5], [6] to increase the coupling between the gate and the channel, and thereby improve the performance of a-IGZO TFTs, fabricated on rigid glass or Si substrates. Additionally, other approaches to increase the gate capacitance are the use of high k materials [7], or thinner gate oxide layers. In this work the double gate concept was combined with a 10 nm thin gate oxide and applied to a-IGZO TFTs fabricated
Figure 1. a) Micrograph of a fully processed flexible a-IGZO double gate TFT (W/L = 280 µm/ 10 µm), b) Double gate a-IGZO TFT schematic.
on flexible plastic foils. The bottom and the top gate were electrically connected to form an a-IGZO TFT controllable with a single gate voltage. The resulting n-type a-IGZO TFTs showed improved performance, and remained fully operational while subjected to mechanically induced strain of 0.55%. A-IGZO double gate TFTs while flat, as well as under mechanical strain, exhibit subthreshold slopes of 69 mV/dec and on-off current ratios > 109. In addition, the transconductance gm of double gate TFTs was increased by 51% when compared to single bottom gate reference TFTs, fabricated on the same substrate. II.
A micrograph of a fully processed flexible a-IGZO double gate TFT and the corresponding device cross section are shown in Figure 1. To ensure the successful fabrication of the presented a-IGZO double gate TFTs on flexible substrates, the following points had to be considered during the design: Atomic layer deposition (ALD) enables the deposition of thin (10 nm) and pinhole free Al2O3 isolation layers with good sidewall coverage. Evaporated Ti and Cr provide a sufficient adhesion on polyimide and a-IGZO, suitable for the fabrication of flexible TFTs. Additionally the work functions of these two materials are comparable (ΦTi = 4.33 eV, ΦCr = 4.44 eV) [8]. Therefore the work functions influence on the threshold voltage can be neglected if Ti and Cr are substituted as gate material. Ti, in contrast to other metals e.g. Au, Cu or Al, has a high resistivity against all wet etchants used to structure Al2O3, a-IGZO, and Cr. Hence, Ti is a suitable material for the bottom gate, which can be structured in a lift-off process, but should not be damaged by the chemicals used during further processing.
This work has been scientifically evaluated by the Swiss National Scientific Foundation (SNSF), and financed by the Swiss Confederation and Nano-Tera.ch.
978-1-4673-1708-5/12/$31.00 ©2012 IEEE
FABRICATION
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Figure 3. Typical a-IGZO TFT (W/L = 280 µm/10 µm) output characteristics; a) bottom gate reference transistor, and b) double gate transitor manufactured on the same substrate.
Figure 2. Typical a-IGZO TFT (W/L = 280 µm/10 µm) transfer characteristics measured in the linear and the saturation regime; a) bottom gate reference transistor, and b) double gate transitor manufactured on the same substrate.
Since wet etching is applicable to Cr, it is an appropriate material for the top gate contact. To determine the influence of the double gate structure, flexible a-IGZO double gate TFTs, as well as standard single bottom gate reference devices were fabricated on the same free standing 50 µm-thick Kapton®E polyimide foil from DuPont. The total substrate size was 7.6 cm x 7.6 cm. The manufacturing process for flexible a-IGZO TFTs on plastic substrates was as follows: A. Single gate reference TFTs Prior to fabrication, the substrate was cleaned by sonication in acetone and isopropanol for 5 minutes each, and was then pre-shrunk in a vacuum oven at 200 °C for 24 h. To increase the adhesion of the successive material layers, the top surface was treated with ozone for 60 minutes, using a UVOCS ultra violet ozone cleaning system. Next, negative MAN1420 photoresist and a Plassys MEB550SL e-beam evaporation system were used to deposit 35 nm Ti, and structure gate contacts in a lift-off process (photolithography mask 1). Resist leftovers were removed by an additional 60 min ozone treatment. A Picosun Sunale R-150B was used to deposit 10 nm Al2O3 as gate isolator by atomic layer deposition at 150 °C. Following, we deposited the 15 nm thick a-IGZO semiconducting layer using room temperature RF magnetron sputtering in a pure Ar atmosphere and a ceramic InGaZnO4 target. The semiconductor was patterned by standard photolithography (mask 2) and diluted hydrochloric acid [9] (HCl : H2O = 1 : 120). The Al2O3 gate isolator was structured into islands 20 µm wider than the semiconductor islands by photolithography mask 3 and AL-11 aluminium etchant from Cyantek heated to 50 °C [10]. We deposited and structured (mask 4) source and drain contacts (50 nm Ti) similar to the gate with another e-beam evaporation and lift-off step. A
second layer of Al2O3 was deposited and structured identical to the gate isolation layer. This concludes the fabrication process of the standard bottom gate TFTs, which served as reference for the fabricated double gate TFTs. In this case the second Al2O3 layer worked as device passivation [11]. B. Double gate TFTs Double gate TFTs with an additional top gate connected with the bottom gate were fabricated on the same substrate. Therefore, 50% of the completed bottom gate TFTs were covered with 50 nm thick evaporated Cr. The Cr was then structured by standard photolithography and wet etching using again mask 1. The top Al2O3 layer served as second gate oxide in this case. Thereby the structuring of the Al2O3 into small islands ensured the electrical contact of the bottom and top gate on both sides of the channel region, whereas the 50 nm thick Cr is thick enough to establish a contact across the sidewalls of all previously structured layers (2x 10 nm Al2O3 + 15 nm a-IGZO). III.
RESULTS AND DISCUSSION
TFTs were characterized under ambient conditions using an Agilent technologies B1500A parameter analyzer with current-voltage, and capacitance-voltage measurement capabilities. Performance parameters were extrapolated from the transfer characteristics measured in the saturation regime using standard MOSFET equations to model the transistor current [8]. A. TFT characteristics Figures 2a and 3a show transfer and corresponding output characteristics of a reference bottom gate a-IGZO TFT, and Figures 2b and 3b the equivalent measurements of an a-IGZO double gate TFT. Figure 4 compares the total measured gate capacitance of a bottom gate reference TFT and a double gate TFT. The W/L ratio is 280 µm/ 10 µm. Compared to the reference single bottom gate TFT, the maximum drain-source current IDS inside the double gate transistor is increased from 1.2 mA to 1.6 mA (VGS =4 V). This increase is related to the stronger coupling between the gate and the channel. The stronger coupling is represented by the increased absolute gate capacitance of the double gate TFT (Figure 4). Due to the additional top gate, the area which
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Figure 6. Subthreshold swing (∂logIDS/∂VGS)-1 of a bottom gate reference TFT and a dual gate TFT for different gate voltages.
Figure 4. Measured gate capacitance and ratio between double gate TFT, and corresponding bottom gate reference TFT capacities (drain and souce contacts are grounded). The W/L ratio is 280 µm/10 µm
TABLE I.
PERFORMANCE PARAMETERS OF A-IGZO DOUBLE GATE TFTS AND BOTTOM GATE REFERENCE TFTS.
Parameter
The effective field effect mobility is 8.3 cm2/Vs for the bottom gate reference TFT and 8.5 cm2/Vs for the double gate TFT (calculated using a by 74% increases capacitance). The small increase of 2.5% is within the process variations of the presented flexible a-IGZO TFT. The transconductance gm = ∂IDS/∂VGS for the reference single bottom gate TFT and the double gate TFT is shown in Figure 5. Due to the higher gate capacitance of the double gate TFTs, gm exhibits a steeper slope. At the same time, the increased threshold voltage of the double gate TFTs shifts the onset of the “on” region to higher VGS values. Therefore the two gm curves intercept at VGS = 1.8 V. The absolute value of gm at VGS = 4 V is increased from 0.7 mS to 1.06 mS due to the additional top gate. The threshold voltage of the double gate transistor is shifted by + 0.7 V, when compared to the reference single
Relative change
109 pF
191 pF
+ 74%
8.3 cm2/Vs
8.5 cm2/Vs
+ 2.5%
0.7 mS
1.06 mS
+ 51%
Threshold voltage
250 mV
950 mV
+ 700 mV
Subthreshold swing
defines the absolute capacitance is increased. The increased gate area of the double gate TFT results in a gate capacitance of 191 pF in the on regime (VGS =3 V). In contrast, the gate capacitance of the corresponding bottom gate reference TFT is 109 pF under equal measurement conditions. This corresponds to an increase of 74%.
Double gate
Gate capacitance (VGS =3 V) Effective field effect mobility Transconductance (VGS =4 V) On-off ratio
Figure 5. Calculated transconductance of a a-IGZO doube gate TFT, and coresponding bottom gate reference TFT for different values of V GS at VDS = 3.75 V. The W/L ratio is 280 µm/10 µm. The inset shows the square root of IDS used for the calculation.
Transistor Bottom gate reference
9 x 10
8
84 mV/dec
2 x 10
9
69 mV/dec
x 2.2 - 18%
bottom gate TFT. This shift is caused by the changed geometry [12] and in good agreement with previously published double gate TFTs [13]. The higher Vth value of 0.95 V ensures that the double gate TFT is totally turned off at VGS = 0 V. This results in a by more than one order of magnitude decreased off-current. The on-off current ratio is mainly improved due to the increased gate capacitance and therefore maximum drainsource current. The double gate TFT reaches a value of 2 x 109 In Figure 6, the subthreshold swings (inverse of subthreshold slope), for the double gate a-IGZO TFT and the reference single bottom gate TFT, are calculated using the measurements shown in Figure 2. In [14] bottom gate a-IGZO TFTs with a similar geometry but 25 nm thick Al2O3 gate oxide exhibited a SS of 180 mV/dec. Due to the reduction of the gate oxide thickness [8] to 10 nm, the reference bottom gate TFT in this paper showed a decreased SS of 84 mV/dec. Furthermore, the additional top gate of the double gate aIGZO TFT further improves the control of the channel potential [12] and reduces SS to 69 mV/dec. The performance parameters of double gate TFTs and corresponding reference bottom gate TFTs are summarized in Table 1. However, due to the thin gate oxide and the added top gate additional effects were observed. First, tunneling of carriers through the 10 nm thin gate oxide (single and double gate TFT) increases the gate leakage current IGS in the “off” state
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improved performance parameters compared to single bottom reference TFTs fabricated on the same substrate. The by 74% increased absolute gate capacitance increased the transconductance up to 51% (VGS = 4 V). On-off current ratio increased by more than a factor of 2, while the subthreshold swing reached a value of 69 mV/dec. This is to our knowledge the smallest value ever reported on flexible a-IGZO TFTs. Tensile mechanical strain of 0.55%, induced by bending the flexible a-IGZO double gate TFTs to a radius of 5 mm did not impair the device functionality significantly. In particular, the subthreshold swing remained unchanged while µFE decreased by 7% and Vth increased by 25 mV. REFERENCES [1] Figure 7. Transfer characteristic of the same a-IGZO double gate TFT (W/L = 280 µm/35 µm) measured while flat, and bent to a tensile radius of 5 mm. The inset shows the bent substrate during the measuremnt.
(Figure 2). The tunnel current increases with increasing VDS, but does not impair devices operated with a supply voltage of 5 V. Second, the larger interface area of the double gate TFT induces a by at least one order of magnitude higher gate leakage current IGS (Figure 2b). B. Bendability To investigate the flexibility of the fabricated a-IGZO double gate TFTs, bending tests were performed as follows: TFTs were attached to double sided tape and wound around a rod, in the way that tensile strain was applied parallel to the TFT channel. The radius of the employed rod was 5 mm, which corresponds to a tensile mechanical strain of 0.55%, calculated using the strain theory developed in [15]. The bent transistors were contacted with probe needles as usual. Figure 7 shows the transfer characteristic of an a-IGZO double gate TFT before bending, and while bent to a radius of 5 mm, as well as a photograph of the bent and contacted TFT. The measurement demonstrated that the transistor remained fully operational when bent to a radius of 5 mm. The applied tensile strain induced a positive threshold voltage shift of 25 mV and a reduction of the effective field effect mobility by 7%, while the subthreshold swing stayed constant within the measurement inaccuracies. Compared to previous bending experiments with bottom gate a-IGZO TFTs [14], the observed shifts correspond to compressive strain in the TFT channel. This indicates different mechanical properties caused by the changed geometry of the double gate devices. Bending to even smaller radii is not possible because of the formation of cracks starting in the brittle Cr top gate contact. We believe that the use of more ductile metals like Cu would enable bending radii between 1 mm and 2 mm without the need of modifying the device structure. IV. CONCLUSION A double gate structure was combined with 10 nm thick Al2O3 gate oxide layers to fabricate TFTs on free standing flexible plastic foils. Double gate a-IGZO TFTs yield
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