Memory Basics (Morris Mano – Chapter 9)

Memory Basics (Morris Mano – Chapter 9)

• • • •

Basic Concepts Address/Data/Control Lines Read/Write Operations Read Only Memory (ROM) – Programmable g ROM – ROM Look-up Tables

• •

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Random Access Memory (RAM) M Memory Address Add Si Size E Expansion i

1

Types of Semiconductor Memory Devices •

Read Only y Memoryy (ROM) ( ) A memory device that maintains its data permanently (or until the device is reprogrammed). reprogrammed)

•

–

– Non-volatile: It maintains its data even without power supply.

•

•

Random Access Memory y (RAM) ( ) A memory device that contains temporary information.

–

Used to store – Programs such as the BIOS. – Data such as lookup tables • e.g. the bit pattern of the characters in a dot-matrix printer printer.

•

A ROM device can be

•

1. Masked ROM (Programmed by the manufacturer) f t ) 2. Programmable ROM (can be program-erased-reprogrammed many times ti ACOE201

Volatile: It looses its data when the power supply is switched-off When the supply is switched-on it contains t i random d d t data

Used to store – –

User p programs g that are loaded from a secondary memory (disk) Temporary data used by programs such as variables and arrays. y

A RAM device can be 1. Static 2. dynamic

2

Basic Concepts •

A memory y device can be viewed as a single column table. – Table index (row number) refers to the address of the memory. – Table entries refer to the memory contents or data data.

Memory Address

Memory Contents

Binary 00 0000 0000 00-0000-0000

Hex 000

10011001

00-0000-0001

001

00111000

00-0000-0010 00-0000-0011

002 003

11001001 00111011

11-1111-1100 11-1111-1101

3FC 3FD

01101000 10111001

11-1111-1110

3FE

00110100

11-1111-1111 11 1111 1111

3FF

00011000

– Each table entry is referred as a memory location or as a word.

•

The size of a memory device is specified as the number of memory locations X width or word size (in bits). – F For example l a 1K X 8 memory device has 1024 memory locations, with a width of 8 bits.

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1024 X 8 (or 1KX8) Memory

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Address Lines • Three types of lines or connections: Address, Data, and Control. • Address Lines: The input lines that select a memory location within the memory device. – Decoders are used, inside the memory chip, to select a specific location – The number of address pins on a memory chip depends specifies the number of memory locations locations. • If a memory chip has 13 address pins (A0..A12), then it has: 213 = 23 X 210 = 8K locations. • If a memory chip has 4K locations, then it should have N pins:

A00 A01

An-2 An-1

Y00 Y01 Y02 Y03

Location 000 Location 001 Location 002 Location 003

YFC YFD YFE YFF

Location 0FC Location 0FD Location 0FE Location 0FF

2N = 4K = 22 X 210 = 212 → N=12 address pins (A0..A11)

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Data Lines • Data Connections: All memory y devices have a set of data output p p pins ((for ROM devices), or input/output pins (for RAM devices). – Most RAM chips have common bi-directional I/O connections. – Most memory devices have 1, 8 or 16 data lines.

Data Input Lines (DI0..DIn-1) k- address lines (A0..Am-1)

2m words

Read (RD) Write (WR)

n-bits per word d

k- address lines (A0..Am-1)

2m words d

k- address lines (A0..Am-1)

2m words d

Read/Write (R/W)

n-bits per word

Output Enable (OE)

n-bits per word

Chip Select (CS)

Chip Select (CS)

Chip Select (CS)

Data Output Lines (DO0..DOn-1) (2m X n) RAM with separate I/P and O/P Data lines

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Data Input/Output Lines (D0..D Dn-1 n 1) (2m X n) RAM with common I/P and O/P Data lines

Data Output Lines (D0..Dn-1) (2m X n) ROM with only O/P Data lines

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Control Lines • Enable Connections: – All memory devices have at least one Chip Select (CS) or Chip Enable (CE) input, used to select or enable the memory device. • If a device is not selected or enabled then no data can be read from, or written into it. • The CS or CE input is usually controlled by the microprocessor through the higher address lines via an address decoding circuit. • Control Connections: – RAM chips have two control input signals that specify the type of memory operation: the Read (RD) and the Write (WR) signals. • Some RAM chips have a common Read/ Write (R/W) signal. – ROM chips can perform only memory read operations, thus there is no need for a Write (WR) signal. • In most real ROM devices the Read signal is called the Output Enable (OE) signal. signal ACOE201

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Memory Read Operations • A memory y read operation p is carried out in the following g steps: p – The processor loads on the Address bus the address of the memory location to be read (Step 1).

• Some of the address lines select the memory devices that owns the memory location to be read (Step 1a), while the rest point to the required memory location within the memory device. – The processor activates the Read (RD) signal (Step 2).

• The selected memory device loads on the data bus the content of the memory y location specified p by y the address bus ((Step p 3). ) – The processor reads the data from the data bus, and resets the RD signal (Step 4). Clock

T1

Address Bus

T2

T3

Valid Address

Chip Enable Read (RD) Data Bus

Invalid Data Step 1a Step 1

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Step 2

Valid Data Step 3

Step 4

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Memory Write Operations • A memory y write operation p is carried out in the following g steps: p – The processor loads on the Address bus the address of the memory location (Step 1).

• Some of the address lines select the memory devices that owns the memory location to be written (Step 1a) 1a), while the rest point to the required memory location within the memory device. – The processor loads on the data bus the data to be written (Step 2). – The processor activates the Write (WR) signal (Step 3).

• The data at the data bus is stored in the memory location specified by the address bus (Step 4) 4). Clock

T1

Address Bus Data Bus

T2

T3

Valid Address Valid Data

Chip Enable Write (WR) Step 2 Step 1 Step 1a Step 3

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St 4 Step

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A Read Only Memory Example • Implementation p of an 8X4 ROM using g a decoder and OR-gates g Address A2 A1 A0

Data D3 D2 D1 D0

0 0 0

0 0 1 1

0 0 1

0 0 1 0

0 1 0 0 1 1

0 1 0 0 0 0 0 0

1 0 0

1 0 1 0

1 0 1 1 1 0

0 0 0 0 0 1 0 1

1 1 1

1 0 0 0

A0 A1 A2 CS

3/8 DEC. Y0 Y1 A0 Y2 A1 Y3 Y4 A2 Y5 Y6 E Y7

OE

D3

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D2

D1

D0

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Programmable Read Only Memory (PROM) 8X4 PROM using a decoder and OR gates with switched links. Electronic Switch

A0 A1 A2 CS

3/8 DEC. Y0 Y1 A0 Y2 A1 Y3 Y4 A2 Y5 Y6 E Y7

OE

D3 D2 D1 D0 ACOE201

• One-Time-Programmable (OTP) ROM: ¾Fusible links are used as electronic switches ¾Programmed only once, using a PROM programmer. • Ultra-Violet Ult Vi l t Erasable(UV) E bl (UV) EPROM: EPROM ¾Special transistors are used as electronic switches ¾Erased by placing the placing the EPROM under UV light (blue light) ™All locations are erased ¾Programmed many times using an EPROM programmer. • Electrically Erasable EEPROM: Spec a ttransistors a s sto s a are e used as e electronic ect o c ¾Special switches ¾Erased and programmed with electronic signals ™No need to remove it from the board ™No need for EPROM programmers ™Only the selected location is erased ¾Also known as the Flash Memory. 10

ROM Design Homework ROM devices are usually y used in digital g systems y as look-up p tables. Some examples p are the following exercises: 1. Design a 2-bit full adder that will produce at its output the sum of the two 2-bit numbers (A3A2) and (A1A0), ) that is, is (D3D2D1D0) = (A3A2) + (A1A0). ) 2. Design a 2-bit multiplier that will produce at its output the product of the two 2-bit numbers (A3A2) and (A1A0), that is, (D3D2D1D0) = (A3A2) * (A1A0). 3 Design a 3 3. 3-bit bit bar bar-graph graph decoder decoder. This is circuit that has as input a 3 3-bit bit binary number and generates a code that switches ON or OFF eight LEDs as shown in figure (a) below. 4. Eight LEDs are placed on a board in a circular form. Design a circuits that will switch ON t two off the th LEDs LED att a titime iin such h a way tto give i th the iimpression i th thatt th the LED LEDs are rotating. Assume that the speed of rotation is controlled by a 0.25Hz timer.

(a)

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111 1

110 1

101 1

100 1

011 0

010 0

000 0

001 0

(b)

Repeat questions 3 and 4 in software using arrays as look-up tables 11

RAM Cells Static RAM ((SRAM): ) • The basic element of a static RAM cell is the D-Latch. • Data D t remains i stored t d iin th the cellll until til it is intentionally modified. • SRAM is fast ((Access time: 1ns). ) • SRAM needs more space on the semiconductor chip than DRAM. • SRAM more expensive i th than DRAM • SRAM consumes power always. • SRAM is used as a Cache

Dynamic y RAM ((DRAM): ) • DRAM stores data in the form of electric charges in capacitors. Ch lleak k out, t th thus need d tto • Charges refresh data every few ms. • DRAM is slow ((Access time: 60ns). ) • DRAM needs less space on the semiconductor chip than SRAM. • DRAM lless expensive i th than SRAM • DRAM consumes power only when accessed. • DRAM is used as the main memory

Bit Select

Bit Select Data In

D

Q

Data Out

Data Out

Data In W it Write

En RAM Cell

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DRAM Cell

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Static RAM – Bit Slice •

• • •

•

•

A number of Ram Cells can be connected together to form a column of memory cells, called a bit slice RAM. The Word Select signal specifies the row to be used. The Bit Select signal activates the whole column (bit slice). The Write Enable signal copies the bit value at the Data In line to the RAM Cell selected through the Word Select signal. This is true only if the Bit Select signal is activated. Th Read The R d Enable E bl signal i l copies i th the bit value l of the RAM Cell selected through the Word Select signal to the Data Out line. This is true only if the Bit Select signal is activated. The Write Enable, Read Enable and Bit Select signal is active low (Enabled when 0).

Word Select 0

Select

D

En RAM Cell

Word Select 2n -1

Select

D

Q

En RAM Cell

Data In Write Logic

Bit Select Logic

Read Logic

Write Enable Bit Select

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Q

Read Enable Data Out

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Static RAM using bit slices (16X4 RAM) A2 A1 A0

A B

Y0 Y1

C D

Y2

R0

R0

RAM Cell

R1

4 to 16 Decode er

A3

Y15

RAM Cell

R1

RAM Cell

R2

R0

Rn

WR

CS

Dout

Din

WR

CS

RAM Cell

R2

Rn

Rn

RAM Cell

RD

RAM Cell

R1

RAM Cell

R2

Rn

RAM Cell

Din

RAM Cell

R1

RAM Cell

R2

R0

RAM Cell

RD

Dout

Din

WR

CS

RAM Cell

RD

Dout

Din

WR

CS

RD

Dout

DIN3 DIN2 DIN1 DIN0 WR RD CS DOUT3 DOUT2 DOUT1 DOUT0

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Static RAM Chips using RAM Bit Slices 16X4 RAM using g four 16X1 bit slices and one decoder (page (p g 14)) • A SRAM chip can be constructed by using a number of RAM bit slices. • The Word Select signals are connected on the outputs of a decoder. • The Bit Select lines are connected together on a Chip Select line. • The Read Enable and Write Enable lines are connected on the RD and WR lines respectively. • The disadvantage of this circuit is that for normal sized RAM chips (few Kbytes up to Mbytes) the decoder must have thousands of outputs, hence thousands of gates t (one ( AND gate t for f each h output). t t) • This disadvantage can be avoided by using the Coincident Selection. – Use one decoder to select a row,, and another to select a column (a ( group g p of columns) – The circuit on the next page shows how a 32X2 RAM can be implemented using four 16X1 bit slices. – Note that instead of a 5X32 decoder (with 32 output AND gates) a 4X16 and a 1X2 decoders are used (with 16 and 2 output AND gates respectively) – For a 64 Kbyte RAM organized as a 1K 1K-row row X 64 64-column column matrix the number of decoder AND gates is reduced from 65535 to 1088 (ie 1024+64). ..see page 16 ACOE201

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Static RAM A3 A2 A1

A B

Y0 Y1

C D

Y2

R0

R0

RAM Cell

R1

4 to 16 Decode er

A4

Y15

RAM Cell

R1

RAM Cell

R2

R0

Rn

WR

CS

Dout

Din

WR

CS

RAM Cell

R2

Rn

Rn

RAM Cell

RD

RAM Cell

R1

RAM Cell

R2

Rn

RAM Cell

Din

RAM Cell

R1

RAM Cell

R2

R0

RAM Cell

RD

Dout

Din

WR

CS

RAM Cell

RD

Dout

Din

WR

CS

RD

Dout

DIN1 DIN0 WR RD

A0 CS

1/2 Dec. A Y0 CS Y1

DOUT1 DOUT0

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Rn

Rn

RAM Cell

Doout

WR W

RAM Cell

Diin

Diin

WR W

RAM Cell

Doout

RD D

CS S

WR W

Din(7:0) WR RD

Din(7:0) WR

A10 A11

CS RD Dout(7:0)

A15 CS

(a)

Dout(7:0)

6 to 64 Dec c.

Diin

RAM Cell

RD D

Rn

Y1023 RAM Cell

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RAM Cell

CS S

RAM Cell

R1

WR W

Rn

Y65535

R1

Diin

A9

R1

RAM Cell

Doout

RAM Cell

RAM Cell

RD D

R1

RAM Cell

R0

CS S

A2

R0

Doout

A15

A1 RAM Cell

R0

Y0 Y1

RD D

A2

A0

CS S

A1

R0

Y0 Y1

10 to 1023 Decoder

A0

16 to 65536 6 Decoder

64Kbyte Static RAM using (a) 64Kbit slices and (b) 1Kbit slices

Y0 Y1

Y63 (b)

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Semiconductor Memory Expansion • The size of memory y devices is usually y less than the memory y requirements q of a computer system. • In all computers, more than one memory devices are combined together to form the main memory of the system. – Any computer must have at least one ROM chip and one RAM chip. • Word size memory expansion: – Most memory devices have a word size (number of data lines) of 8 or 16 bits. – The word size of today’s microprocessors is 32 bits (80386, 80486) or 64 bits (Pentium) • Address size memory expansion: – The size of common memory chips is usually less or in the order of 1M-byte. – Most personal computers have more than 256 Mbytes of RAM. – Workstations and other high throughput computers have more than 1Gbytes of RAM RAM. ACOE201

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Memory Expansion on Motherboards

Memory Expansion Using 4 SIMMs on the Motherboard

Memory Expansion using 4 Memory Chips on a SIMM

Motherboard Slot 3

Slot 4

Slot 1

Slot 2

SIMM/DIMM

SIMM/DIMM

SIMM/DIMM

Processor

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Memory Address Size Expansion • More than one memory devices can be used to expand the number of memory locations on the system. • To expand the address size do the following: – Determine the number of memory chips required, by dividing the required memory size i with ith the th size i off the th memory devices d i t be to b used. d – Connect the data lines of each memory chip in parallel on the data lines of the processor. – Connect the address lines of each memory chip in parallel with the lower address lines of the processor. – Connect the CS lines of each memory device with the high address lines of the processor through an address decoding circuit. – Connect together g all WR and all RD lines of each memory y device. ACOE201

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Address Size Expansion: (32X4 RAM module using 8X4 RAM chips) D3 D2 D1 D0 8X4 D3 D2 D1 D0 RAM

0

8X4 D3 D2 D1 D0 RAM

0

1

A0

2

A0

3

8X4 D3 D2 D1 D0 RAM

0

1

2

A0

3

1

2

A0

3

2 3

A1 4 A2

A1 4 A2

A1 4 A2

A1 4 A2

6

6

6

6

7

7

7

7

RD

5

WR CS

RD WR A0 A1 A2 2X4 DEC DEC.

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0

1

5

A3 A4 A5 A6 A7

8X4 D3 D2 D1 D0 RAM

A B CS

RD

5

WR CS

RD

5

WR CS

RD

WR CS

Examples: M[0Ch] ← 6h M[03h] ← 9h M[1Ah] ← 3h M[14h] ← 2h M[08h] ← 5h M[00h] ← 1h M[0Fh] ← 0h M[10h] ← Ah M[18h] ← 4h M[07h] ← 8h M[1Fh] ← Eh M[17h] [ ] ← 7h

Y0 Y1 Y2 Y3

Address Selection

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Memory Maps • Tables that show the addresses occupied p by y each memory y device in a system. y • In the previous example it is assumed that the processor has 8 address line, line thus it can address 256 memory locations. • The size of the RAM memory module is 32 bytes, bytes thus the module can be mapped to occupy one out of the eight available memory blocks in the memory map. • The memory block occupied by the memory module depends on the connection of the address selection circuit (AND gate) that enables the decoder.

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A5 A6 A7

A5 A6 A7

00 - 07 08 - 0F 10 - 17 18 - 1F

RAM1 RAM2 RAM3 RAM4

20 - 3F

Not Used

40 - 5F

60 - 7F

80 - 9F

A0 - bF

Not Used Not Used Not Used Not Used

A5 A6 A7

A5 A6 A7

00 - 1F

N t Not Used

00 - 1F

N t Not Used

00 - 1F

N t Not Used

20 - 3F

Not Used

20 - 3F

Not Used

20 - 3F

Not Used

40 - 47 48 - 4F 50 - 57 58 - 5 5F

RAM1 RAM2 RAM3 RAM4

40 - 5F

Not Used

40 - 5F

Not Used

60 - 7F

60 - 7F

Not Used

60 - 7F

Not Used

Not Used

80 - 9F

Not Used

80 - 9F

Not Used

A0 - A7 A8 - AF b0 - b7 b8 - bF

RAM1 RAM2 RAM3 RAM4

A0 - bF

Not Used

C0 - dF

Not Used

E0 - E7 E8 - EF F0 - F7 F8 - FF

RAM1 RAM2 RAM3 RAM4

80 - 9F

A0 - bF

Not Used Not Used

C0 - dF

Not Used

C0 - dF

Not Used

C0 - dF

Not Used

E0 - FF

Not Used U d

E0 - FF

Not Used U d

E0 - FF

Not Used U d

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Three of the eight possible Memory Map for previous example.

Address Selection Circuit

A5 A6 A7

Address Selection Circuit

A5 A6 A7

Address Selection Circuit

A5 A6 A7

A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map

A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map

A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map

0 0 0 0 0 0 0 0 00 RAM1 0 0 0 0 0 1 1 1 07

0 0 0 0 0 0 0 0 00 Not 1 0 0 1 1 1 1 1 9F Used

0 0 0 0 0 0 0 0 00 Not 1 1 0 1 1 1 1 1 DF Used

0 0 0 0 1 0 0 0 08 RAM2 0 0 0 0 1 1 1 1 0F

1 0 1 0 0 0 0 0 A0 RAM1 1 0 1 0 0 1 1 1 A7

1 1 1 0 0 0 0 0 E0 RAM1 1 1 1 0 0 1 1 1 E7

0 0 0 1 0 0 0 0 10 RAM3 0 0 0 1 0 1 1 1 17

1 0 1 0 1 0 0 0 A8 RAM2 1 0 1 0 1 1 1 1 AF

1 1 1 0 1 0 0 0 E8 RAM2 1 1 1 0 1 1 1 1 EF

0 0 0 1 1 0 0 0 18 RAM4 0 0 0 1 1 1 1 1 1F

1 0 1 1 0 0 0 0 B0 RAM3 1 0 1 1 0 1 1 1 B7

1 1 1 1 0 0 0 0 F0 RAM3 1 1 1 1 0 1 1 1 F7

0 0 1 0 0 0 0 0 20 Not 1 1 1 1 1 1 1 1 FF Used

1 0 1 1 1 0 0 0 B8 RAM4 1 0 1 1 1 1 1 1 BF

1 1 1 1 1 0 0 0 F8 RAM4 1 1 1 1 1 1 1 1 FF

1 1 0 0 0 0 0 0 C0 Not 1 1 1 1 1 1 1 1 FF Used

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Design Example: Design an 8KX8 RAM module using 2KX8 RAM chips. The module should be connected on an 8-bit 8 bit processor with ith a 16 16-bit bit address dd b bus, and d occupy th the address dd range starting t ti ffrom th the address A000. Show the circuit and the memory map. • Number of memory devices needed = 8K/2K = 4 • Decoder needed = 2X4 • Number of address lines on each 2KX8 memory chip = 11 2m = 2K = 21 x 210 = 211 ⇒ (A0..A10) • Decoder needed = 2X4 ⇒ 2 address lines are needed for the decoder. ⇒ (A11..A12) • Number N b off address dd li lines needed d d for f the address selection circuit = 16 - 11 - 2 = 3 ⇒ (A13, (A13 A14, A14 A15) ACOE201

Starting Address = A000 = 1010 1010-0000-0000-0000 0000 0000 0000 ==> A15 = 1, A14 = 0 and A13 = 1 A13 Address Selection Circuit A14 A15 A15 A14 A13 A12 A11 A10

A0

Mem. Map

0 1

0 0

0 0

0 1

0 1

0 1

0 0000 1 9FFF

1 1

0 0

1 1

0 0

0 0

0 1

0 1

A000 RAM1 A7FF

1 1

0 0

1 1

0 0

1 1

0 1

0 1

A800 RAM2 AFFF

1 1 1

0 0 0

1 1 1

1 1 1

0 0 1

0 1 0

0 1 0

1 1

0 1

1 0

1 0

1 0

1 0

1 0

1

1

1

1

1

1

1

B000 RAM3 B7FF B800 RAM4 BFFF C000 Not FFFF Used

Not Used

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Circuit Diagram

D7 D0

D7

2Kx8 RAM D0

D0

D7

2Kx8 RAM

D0

D7

2Kx8 RAM

D0

D7

2Kx8 RAM

A0

A0

A0

A0

A10

A10

A10

A10

RD WR CS

RD WR CS

RD WR CS

RD WR CS

RD WR A0

A13 A14 A15

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A15

2X4 DEC. A11 A Y0 A12 B Y1 Y2 CS Y3

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Memory expansion Homework 1. Design g an 128KX8 RAM module using g 16KX8 RAM chips. p The module should be connected on an 8-bit processor with a 20-bit address bus, and occupy the address range starting from the address 40000H. Show the circuit and the memory map. 2. Design an 12KX8 RAM module using 4KX8 RAM chips. The module should be connected on an 8-bit processor with a 16-bit address bus, and occupy the address range starting from the address C000H. Show the circuit and the memory map. 3. Design an 384KX8 RAM module using 64KX8 RAM chips. The module should be connected on an 8-bit processor with a 20-bit address bus, and occupy the address range starting from the address 80000H. Show the circuit and the memory map.

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