This paper is a postprint of a paper submitted to and accepted for publication in IET Electronics Letters journal and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library.
Memristor-based parallel sorting approach using one-dimensional cellular automata I. Vourkas, D. Stathis and G.Ch. Sirakoulis
In this letter we present a novel memristor-based circuit-level Cellular Automata (CA)-inspired approach to the solution of the classic sorting problem of n Keys in a linear array. The presented system utilizes the structural simplicity of CA combined with the threshold-type switching behaviour of memristors and composite memristive components; the latter are used both for information encoding and computation. We focus on a threshold-type model for memristors for the implementation of the fundamental CA cell and verify the overall CA operation via simulations.
Introduction: Since the dawn of computing the sorting problem has been one of the most extensively researched subjects [1]. The main purpose of sorting information is to optimize its usefulness for specific tasks which require sorted input data. Sorting networks, which use comparators built of series of reciprocally placed memristors, were previously studied in [2]. Memristors (concatenation of “memory resistors”) constitute a recently discovered class of two-terminal passive nonvolatile resistance-switching devices which have so far shown abilities that could revolutionize hardware (HW) computing architectures [3-7]. However, the aforementioned network-based HW approach has the following disadvantages which render its practical use questionable: i) the comparators’ output levels gradually degrade through cascading, thus signal rectification is occasionally required; ii) the complexity of interconnections increases significantly as the size of the problem (the number of inputs) increases. This letter addresses the classic sorting problem of n values (Keys) in a linear array by proposing a novel memristor-based circuit-level parallel approach inspired by one-dimensional (1-d) cellular automata (CA) [8]. CA constitute a well-studied, inherently parallel, efficient, and robust computing paradigm [9]. Due to their ability to capture globally emerging behaviour from the local collective interaction of simple components, CA have been successfully applied to several computational problems [8-10]. Indeed, when CA-based algorithms are implemented in HW they are executed fast by exploiting the parallel structure of CA; HW design reduces to the design of a single CA cell whereas the overall layout results regular with local interconnections. Here we present the design of the fundamental memristive CA cell which implements the CA update rule and which we employed it in the creation of a 1-d computational structure which executes parallel sorting of input Keys. Within the cells, information is encoded in the resistive states of threshold-type switching memristors and composite memristive components. Compared with [2], the proposed design combines the computational capabilities and the size-independent simple structure of CA with the unique circuit properties of memristors, to provide a HW capable of executing computations within memory.
(
) (
1 , Keyit ≥ Keyit+1 ∩ Keyit > Keyit−1 SL = else 0 ,
(
) (
)
1 , Keyit < Keyit+1 ∩ Keyit+1 ≥ Keyit+ 2 SR = else 0 ,
t +1 i
Key
Keyit−1 , S L = 1 = Keyit+1 , S R = 1 Key t , else i
(1a)
)
(1b)
(2)
Sorting CA: Each cell of the 1-d CA is assigned a Key to be ordered. Sorting is performed by the parallel local exchange of Keys between neighbouring cells. A cell exchanges its Key with either its right or its left neighbour; priority is given to the right swap in case a conflict is
detected. All cells operate using the same update rule without knowing neither their index i nor the length n of the array. Fig. 1a shows the CA neighbourhood which consists of four cells. The state of each cell is defined by three memory elements: an integer value for the Key, and two binary elements for the Left/Right swapping rules, SL and SR. Fixed boundary conditions are applied to the extreme cells of the array. The CA update rule is described by (1) and (2). Each computation step comprises two stages: first the swapping rules are computed; then Key exchanges are locally performed. At a certain moment, the array is sorted and there are no more valid exchanges to take place; the swapping rules remain the same. Execution of the CA could be stopped (i) either via a global control mechanism which would supervise at each step if at least a swap has occurred, or (ii) by determining the worst-case for the computational time to sort the array, thus bounding the total steps to a fixed limit. The worst-case occurs when the Keys are initially in the inverse order and the required time complexity is O(2n-3). Here we assume the (i) of the aforementioned termination mechanisms; the system stops functioning when the Keys have been finally sorted in descending order. Circuit implementation: Fig. 1b describes the overall function of the memristor-based sorting CA. First the CA array is initialized with the integer Keys to be ordered. Afterwards the CA evolves and it stops when no more changes occur in the global CA state. CA cell circuit operation consists of three consecutive computational stages: (i) reset stage: all memristors are reset to the high resistive state (ROFF); (ii) set stage: CA cells compute their next state; (iii) read stage: the recently computed cell-state is stored and the cell’s output is defined. For readability reasons we have separated the whole circuit in separate schematics corresponding to the particular stages.
a
b Fig. 1 Sorting Cellular Automaton (CA) a 1-d CA neighbourhood comprising four cells. b Flow chart describing the overall memristive CA operation. The circuit for the set stage is shown in Fig. 2a. SL and SR define how the input Keys will affect the next cell-state by controlling two switches while operating according to (1a) and (1b). The Key value is stored in the state of a composite memristive component. Such device consists of n parallel memristors which have different VSET thresholds, namely VSET,1 < VSET,2 < … < VSET,n, but equal memristance ranges [RON, ROFF]. All memristors are formerly reset to the ROFF state. Since gradual resetting is not important, we assume a common negative threshold VRESET for all memristors; unconditional application of a negative voltage higher than |VRESET| will reset all memristors. However, under positive applied voltage the composite device operates as a multithreshold memristive device. When the voltage amplitude falls between
1 DOI: 10.1049/el.2014.2912
VSET,1 and VSET,2 only the first memristor switches to RON. If the voltage amplitude is between VSET,2 and VSET,3 two of the memristors switch states, etc. Finally, a voltage higher than VSET,n causes all n memristors to switch. Regardless of possible variation in memristance boundaries, a high enough ratio ROFF/RON assures that the equivalent memristance will evolve while taking values which approximate the following: {ROFF/n, RON, RON/2, RON/3, …, RON/n} depending on the number of memristors that are set to RON. Hence, the number of parallel memristors determines the max value of the Key. A current-controlled DC voltage source stores the next cell-state both for internal use as well as to define cell’s output.
show the current Key and the two binary elements for the swapping rules (SL and SR); the latter remain the same between the last two sorting steps, something which is indicative of the termination of the process. The presented example constitutes a proof of concept of a general methodology for the implementation of fast, parallel data-sorting HW components exploiting the unique processing-in-memory property of emerging memristive technologies and the structural simplicity of CA.
Fig. 3 Simulation result for sorting four Keys. Parameters SL, Key, and SR are shown for each CA cell Boundary condition for SL1 (SR4) corresponds to applied voltage which is higher than max Key (lower than min Key). Simulation is completed after five CA evolution steps. a
Conclusion: We presented a circuit-level CA-inspired early approach to perform sorting in a linear array. Threshold-type memristors and composite multi-state memristive components were used both for information encoding and computation. A simulation-based verification of the proposed design was presented. Integration of the sorting system with applications requiring sorted data, will be part of our future work. I. Vourkas, D. Stathis and G.Ch. Sirakoulis (Department of Electrical and Computer Engineering, Democritus University of Thrace, Greece) E-mail:
[email protected] References
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1. Knuth, D.E.: ‘volume 3: Sorting and Searching’ in ‘The Art of Computer Programming’ (Addison-Wesley, Reading, MA, USA, 1998, second edition) 2. Klimo, M., Such, O.: ‘Memristors can implement fuzzy logic’, (2011) arXiv:1110.2074v1 [cs.ET] 3. Corinto, F., Ascoli, A.: ‘Memristive diode bridge with LCR filter’, IET El. Lett., 2012, 48, (14), pp. 824-825, doi:10.1049/el.2012.1480 4. Park, S., Park, J., Kim, S., Lee, W., Lee, B.H., Hwang, H.: ‘Programmable analogue circuits with multilevel memristive device’, IET El. Lett., 2012, 48, (22), pp. 1415-1417, doi:10.1049/el.2012.3179 5. Yakopcic, C., Hasan, R., Taha, T.M., McLean, M., Palmer, D.: ‘Memristor-based neuron circuit and method for applying learning algorithm in SPICE?’, IET El. Lett., 2014, 50, (7), pp. 492-494, doi:10.1049/el.2014.0464 6. Zidan, M.A., Omran, H., Radwan, A.G., Salama, K.N.: ‘Memristor-based reactance-less oscillator’, IET El. Lett., 2011, 47, (22), pp. 1220-1221, doi:10.1049/el.2011.2700 7. Vourkas, I., Sirakoulis, G.Ch.: ‘On the Analog Computational Characteristics of Memristive Networks’, 20th IEEE Int. Conf. Electronics, Circ., Syst., Abu Dhabi, UAE, December 2013, pp. 309-312, doi:10.1109/ICECS.2013.6815416 8. Gordillo, J.L., Luna, J.V.: ‘Parallel sort on a linear array of cellular automata’, IEEE Int. Conf. Syst., Man, Cybernetics, Humans, Inf. and Techn., San Antonio, TX, October 1994, pp. 1903-1907 vol.2, doi:10.1109/ICSMC.1994.400129 9. Chopard, B.: ‘Cellular Automata Modeling of Physical Systems’ in Meyers, R.A. (Ed.): ‘Computational Complexity’ (Springer, New York, 2012) 10. Adamatzky, A.I: ‘Computation of shortest path in cellular automata’, Math. Comput. Modell., 1996, 23, (4), pp. 105–113, doi:10.1016/08957177(96)00006-4 11. Vourkas, I., Batsos, A., Sirakoulis, G.Ch. (2013), ‘SPICE modeling of nonlinear memristive behavior’, Int. J. Circ. Theor. Appl., doi: 10.1002/cta.1957
Fig. 2 Circuit schematics corresponding to the computational stages of the CA update rule a Set stage. The memristive composite component is shown in detail. b Read stage. This is better explained in Fig. 2b which shows the circuit which implements the read stage. The composite device is read by applying a positive DC voltage VREAD of low enough amplitude which does not exceed any of the switching thresholds. The device is connected to a current-to-voltage converter (I/V) of variable external gain RF/RC, where the feedback resistor is RF = RON and RC is the variable composite memristance of the parallel memristors. The I/V output is approximately given by m × VREAD, where m is the number of memristors that are in RON. Only when all of the n parallel memristors are in ROFF, it is RC ≈ (ROFF / n) >> RF and the I/V output voltage is very small. Based on the I/V output, the current-controlled DC voltage source is adjusted to hold the next Key value (cell’s output). Simulation results: Fig. 3 shows the simulation result from the application of the proposed approach to a set of Keys which are initially in the inverse order. In simulation we used a threshold-type model of voltage-controlled memristors [11]. Three parallel memristors are used in the CA cells to be able to encode the max of the Key values. For the memristors we assume [RON, ROFF] = [2, 650]KΩ, {VSET,1, VSET,2, VSET,3} = {0.5, 1.5, 2.5}V, and VRESET = -3V. The amplitude of the applied set voltage is 1, 2, or 3V, depending on the corresponding stored Key. The applied voltages for the read and the reset stages are 1V and -4V, respectively. During the read stage the memristors are reversely polarized, therefore their state is not affected since VREAD < |VRESET|. Fig. 3 presents the sequence of Key-exchanges during five sorting steps; computation stops when no more exchanges occur. For each CA cell we
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