Announcements. • HW7 Due Apr. 14. • Reading. • MOSFETS I & II (Silva). • 5.1 –
5.3, 7.1 - 7.5 (Sedra/Smith). 2. Page 3. MOSFET Circuit Symbols. NMOS. PMOS.
ECEN325: Electronics Spring 2017 Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)
Sam Palermo Analog & Mixed-Signal Center Texas A&M University
Announcements • HW7 Due Apr. 13
2
ECEN 326 in Fall 2017 • I will be teaching ECEN 326 (Electronic Circuits) in Fall 2017 • Lecture MWF 9:10-10 • Labs R 8-10:50 or 11:10-2:00
• Prerequisite for important senior-level analog design classes (474) • Topics • Differential amplifiers, opamp circuits, frequency response, feedback, stability, output stages 3
MOSFET Circuit Symbols NMOS
PMOS
• MOSFETs are 4-terminal devices • Drain, Gate, Source, & Body
• Body terminal generally has small impact in normal operation modes, thus device is generally considered a 3-terminal device • Drain, Gate, and Source are respectively similar to the Collector, Base, and Emitter of the BJT
• 2 complementary MOSFETS: NMOS, PMOS 4
NMOS Physical Structure
n+
n+
[Karsilayan] 5
CMOS Physical Structure
[Karsilayan] 6
VT Definition [Silva]
• The threshold voltage, VT, is the voltage at which an “inversion layer” is formed • For an NMOS this is when the concentration of electrons equals the concentration of holes in the p- substrate 7
MOS Equations in Triode Region (Small VDS) [Sedra/Smith] Current from Source to Drain : I
dQ dQ dx Qd ( x) dt dx dt
Incremental Charge Density : Qd ( x) COX W (VGC x VT ) Gate - to - Channel Voltage : VGC x VT VGS VCS ( x) VT Electron Velocity : n E x n
dv x dx
I DS I COX W (VGS VCS ( x) VT ) n
dv x dx
L
I 0
dx
C n
ox
OX
W (VGS VT VCS ( x))dv x
0
I DS nCOX
I I DS Capacitance per unit gate area : Cox
DS
VDS
W 1 VGS VT VDS VDS L 2
t ox
Electron mobility : n 8
Triode or Linear Region [Silva]
VDS
x=0
V 0 0
V x VDS
x L
x=L
V L VDS
VGC x VGS V x VGS VDS
x L
• Channel depth and transistor current is a function of the overdrive voltage, VGS-VT, and VDS • Because VDS is small, VGC is roughly constant across channel length and channel depth is roughly uniform I DS
W nCOX VGS VTn 0.5VDS VDS L
RDS
For small VDS
1
W Cox VGS VTn L
9
MOS Equations in Triode Region (Large VDS) VGS
GND
Drain current: Expression used in SPICE level 1
VDS
I DS
tox N+
W
N+
ID
L
GND
VGS
VDS
W nCOX VGS VTn 0.5VDS VDS L
Linear approximation
This doesn’t really happen
IDsat
tox N+
N+
Non-linear channel
W
VGS > VT VDS VDSsat
VDSsat VGS VTn
Triode Region Channel Profile [Sedra/Smith]
VGC x VGS V x VGS VDS
x L
• If VGC is always above VT throughout the channel length, the transistor current obeys the triode region current equation 11
Saturation Region Channel Profile VGC x VGS V x VGS VDS
x L
• When VDS VGS-VT=VOV, VGC no longer exceeds VT, resulting in the channel “pinching off” and the current saturating to a value that is no longer a function of VDS (ideally)
[Sedra/Smith] 12
Saturation Region [Silva]
VDSsat=VGS-VT
x=0
V 0 0
V x VDS
VDS-VDSsat
x L
VGC x VGS V x VGS VDS
x L
x=L
V L VDS
• Channel “pinches-off” when VDS=VGS-VT and the current saturates • After channel charge goes to 0, the high lateral field “sweeps” the carriers to the drain and drops the extra VDS voltage I DS nCOX
W VDS V V GS VDS Tn 2 VDS VGS VTn L
I DS
nCOX W 2
L
VDSsat VGS VTn
VGS VTn 2 13
NMOS ID – VDS Characteristics VOV VGS VTN
[Sedra/Smith]
14
MOS “Large-Signal” Output Characteristic [Sedra/Smith]
Note: Vov=VGS-VT
15
What about the PMOS device? NMOS
PMOS [Silva]
• The current equations for the PMOS device are the same as the NMOS EXCEPT you swap the current direction and all the voltage polarities NMOS W nCOX VGS VTn 0.5VDS VDS L W nCOX VGS VTn 2 Saturation: I DS 2L
Linear: I DS
PMOS
W p COX VSG VTp 0.5VSD VSD L 2 W I SD p COX VSG VTp 2L
I SD
16
PMOS ID – VSD Characteristics VOV VSG VTP
[Karsilayan]
(Saturation)
17
NMOS DC Operation (w/ infinite rout) Region
Bias Condition
I DS
Cutoff
VGS VTN
I DS 0
Triode (Linear)
VGS VTN , VDS VGS VTN
Saturation (Active) VGS VTN , VDS VGS VTN
[Karsilayan]
I DS nCox
I DS
V W VGS VTN DS VDS L 2
nCox W 2
L
VGS VTN 2
• In transistor model, often combine nCox term as a parameter KPN with units A/V2 • In lab, we combine nCox(W/L) term as a parameter N with units A/V2 18
PMOS DC Operation (w/ infinite rout) Region
Bias Condition
I SD
Cutoff
VSG VTP
I SD 0
Triode (Linear)
VSG VTP , VSD VSG VTP
Saturation (Active) VSG VTP , VSD VSG VTP
[Karsilayan]
I SD p Cox
I SD
V W VSG VTP SD VSD L 2
p Cox W 2
L
V
SG VTP
2
• In transistor model, often combine pCox term as a parameter KPP with units A/V2 • In lab, we combine pCox(W/L) term as a parameter P with units A/V2 19