All of the program memory and external data memory are transferred to the CPU ..... In standard 16-bit mode, the externa
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MICRO PROCESSOR and MICRO CONTROLLER
UNIT –VIII Topics in the unit :Advanced Microcontrollers: MCS – 96 Microcontrollers: Important Features, Pin Diagram, Internal Architecture, Memory Map, Addressing Modes, Instruction set. ARM Microcontrollers: ARM Core Architecture, Versions of ARM, Important Features.
Micro-Controller - 80C196 Features The 80c196 is an 16-bit microcontroller made by Intel using CHMOS technology. The 80c196 integrates on a single chip all interface elements which are generally in the close environment of a microprocessor. The 80c196 provide : 232 internal byte registers A register-to-register architecture Dynamically configurable 8-bit or 16-bit buswidth DMA capability A 16x16-bit 2.3 microsecond multiply (at 12MHz) A 32/16-bit 4.0 microsecond divide (at 12MHz) 28 interrupt sources with 16 vectors 6 16-bit timers, up/down counters or software timers A high speed I/O subsystem A serial port A 10-bit digital-to-analog converter with sample-and-hold 5 8-bit I/O ports A 16-bit watchdog timer Powerdown and idle modes Additional 256 bytes of on-chip RAM (KC only)
80c196 architecture Block diagram The 80c196 is mainly based on : A CPU which is turn composed of a 16-bit ALU with temporary registers, a 256-byte RAM used as 24 special registers and 232 general registers, and a microprogrammed sequencer. A memory controller with a 4-byte FIFO queue to prefetch instructions and data from the program memory. A set of I/O interfaces.
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MICRO PROCESSOR and MICRO CONTROLLER
The CPU gets his information only through the memory controller and the special registers also called Special Function Registers (SFRs). The ALU, is associated to a set of temporary registers (with shifter, counter, constants) and thus called RALU (Register ALU). The RALU doesn't use an accumulator but instead is ablt to directly work with any of the 256 special or general registers All I/O operations are controlled through the SFRs.
80c196 block diagram
Memory controller All of the program memory and external data memory are transferred to the CPU through the memory controller. The memory controller consists of a slave program counter, an instruction queue and a bus controller. The slave program counter keeps track of the instructions fetched from the program memory. Instructions fetched by the memory controller are stored in the queue. The slave program counter may be up to four bytes ahead of the main program counter (which is located in the RALU), because it is pre-fetching the instructions. The bus controller accesses program memory (on-chip EPROM) and external data memory and arbitrates between instruction fetches and data reads and writes. The bus controller supports both 8-bit and 16-bit external bus modes. Memory access requests to the bus controller can come from either the RALU or the queue, with priority given to the queue accesses. If the address sequence changes because of a jump, interrupt, call or return, the slave PC is loaded with a new value, and the queue is flushed. Reloading the slave PC, flushing the queue and fetching the the first byte of
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MICRO PROCESSOR and MICRO CONTROLLER the new instruction stream takes 4 state times. This is reflected in the conditional jump taken/not-taken execution times. The CPU The CPU is controlled by a microcode sequencer and can perform operations on any byte, word or doubleword in the 256-byte register space. Instructions to the CPU are taken from the pre-fetch queue and temporarily stored in the instruction register. The sequencer decodes the instruction and generates the correct sequence of events to have the RALU perform the desired operation. The RALU Most calculations performed by the 80c196 take place in the RALU. The RALU contains a 17-bit ALU Arithmetic and Logic Unit, the flag register also called PSW - Program Status Word, the main PC - Program Counter, a loop counter and three temporary registers. All registers are 16-bits or 17-bits wide.
The Register Arithmetic and Logic Unit The PC has a separate incrementor as to access operands. However, PC changes due to jumps, interrupts, calls and returns are handled through the ALU. Two of the temporary registers have their own shift logic. These registers are used for the instructions which require logical shifts, including Normalize, Multiply and Divide. The upper word and lower word registers are used together for the 32-bit instructions and as temporary registers for many other instuctions. Repetitive shifts are counted by the 6-bit loop counter. A third temporary register stores the second operand of two-operand instructions. To perform subtractions the output of this register can be complemented before being placed into the input of the ALU. The RALU also stores several constants such as 0,1 and 2 to speed up certain operations like getting a 2's complement, incrementing or decrementing
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MICRO PROCESSOR and MICRO CONTROLLER
2.4 Instruction set 2.4.1 Initializations CLR - Clear Word CLRB - Clear Byte CLRC - Clear Carry Flag CLRVT - Clear Overflow Trap SETC - Set Carry Flag
2.4.2 Data transfer BMOVE - Block Move (80c196KB only) LD - Load Word LDB - Load Byte LDBSE - Load Integer with Short-Integer LDBZE - Load Word with Byte ST - Store Word STB - Store Byte
2.4.3 Stack operations POP - Pop Word POPA - Pop All (80c196KB only) POPF - Pop Flags PUSH - Push Word PUSHA - Push All (80c196KB only) PUSHF - Push Flags
2.4.4 Arithmetic operations ADD - Add Words ADDB - Add Bytes
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MICRO PROCESSOR and MICRO CONTROLLER ADDC - Add Words with Carry ADDCB - Add Bytes with Carry DEC - Decrement Word DECB - Decrement Byte DIV - Divide Integers (signed) DIVB - Divide Short Integers (signed) DIVU - Divide Words (unsigned) DIVUB - Divide Bytes (unsigned) EXT - Sign Extend Integer into Long-Integer EXTB - Sign Extend Short-Integer into Integer INC - Increment Word INCB - Increment Byte MUL - Multiply Integers (signed) MULB - Multiply Short Integers (signed) MULU - Multiply Words (unsigned MULUB - Multiply Bytes (unsigned NEG - Negate Integer NEGB - Negate Short-Integer SUB - Subtract Words SUBB - Subtract Bytes SUBC - Subtract Words With Borrow SUBCB - Subtract Words With Borrow
2.4.5 Logical operations AND - Bitwise Logical AND Words ANDB - Bitwise Logical AND Bytes NOT - Complement Word NOTB - Complement Byte OR - Bitwise Logical OR Words
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MICRO PROCESSOR and MICRO CONTROLLER ORB - Bitwise Logical OR Bytes XOR - Bitwise Logical XOR Words
2.4.6 Shifts SHL - Left Shift Word SHLB - Left Shift Byte SHLL - Left Shift Double-Word SHR - Logical Right Shift Word SHRA - Arithmetic Right Shift Word SHRAB - Arithmetic Right Shift Byte SHRAL - Arithmetic Right Shift Double-Word SHRB - Logical Right Shift Byte SHRL - Logical Right Shift Double-Word
2.4.7 Comparisons CMP - Compare Words CMPB - Compare Bytes CMPL - Compare Long (80c196KB only)
2.4.8 Jumps and calls BR - Branch Indirect LCALL - Long Call LJMP - Long Jump RET - Return from Subroutine SCALL - Short Call SJMP - Short Jump
2.4.9 Conditional jumps DJNZ - Decrement and Jump if not Zero
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MICRO PROCESSOR and MICRO CONTROLLER DJNZW - Decrement and Jump if Not Zero Word (80c196KB only) JBC - Jump if Bit Clear JBS - Jump if Bit Set JC - Jump if Carry JE - Jump if Equal JGE - Jump if Greater or Equal (signed) JGT - Jump if Greater than (signed) JH - Jump if Higher (unsigned) JLE - Jump if Less or Equal (signed) JLT - Jump if Less than (signed) JNC - Jump if No Carry JNE - Jump if Not Equal JNH - Jump if Not Higher (unsigned) JST - Jump if Sticky bit JV - Jump if Overflow JVT - Jump if Overflow Trap
CONTROL INSTRUCTIONS DI - Disable Interrupts EI - Enable Interrupts IDLPD - Idle / Powerdown (80c196KB only) NOP - No Operation RST - Reset System SKIP - Two-byte NOP TRAP - Software Trap
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MICRO PROCESSOR and MICRO CONTROLLER
Addressing modes Operands are accessed within the address space of the 80c196 with one of 6 basic addressing modes. Some of the details of how these addressing modes work are hidden by the assembler language. AX, BX, CX, DX are 16-bit registers AL, AH are the lower byte and the higher byte of AX respectively BL, BH are the lower byte and the higher byte of BX respectively CL, CH are the lower byte and the higher byte of CX respectively DL, DH are the lower byte and the higher byte of DX respectively These are the same as the names for the general data registers used in the 8086. It is important to understand that in the 80c196 these are not dedicated registers, but merely the symbolic name assigned by the programmer to four words within the on-chip 232 general registers. Direct addressing The register-direct mode is used to directly access a register, selected by an 8-bit field within the instruction. The register address must conform to the operand's type alignment rules. Examples ADD INCB
AX,BX,CX CL
; (AX)16
