Micromachined High Aspect Ratio Coplanar Waveguide with High Impedance and Low Loss on Low Resistivity Silicon Shane T. Todd #1 , John E. Bowers #2 , and Noel C. MacDonald ∗3 # Department
of Electrical and Computer Engineering and ∗ Department of Mechanical Engineering University of California, Santa Barbara Santa Barbara, CA, USA 93106
1
[email protected],
2
[email protected],
Abstract—A micromachining process has been developed to create high impedance and low loss high aspect ratio coplanar waveguide (HARC) on low resistivity silicon. The process uses silicon DRIE to create an array of tall mesas that are spaced with a precise pitch. The silicon mesa array is then merged into a single solid SiO2 mesa using thermal oxidation. The solid SiO2 mesa creates a wide dielectric for use in high impedance HARC. The complete fabrication process includes DRIE, thermal oxidation, electroplating, planarization, and substrate removal to create HARC on low resistivity silicon with a planar surface. A high impedance HARC has been fabricated on silicon using this method. Measurements show that silicon substrate removal increases the line impedance from 20 Ω to 57 Ω, reduces effective dielectric constant from 6 to 2, and reduces attenuation constant from 33 dB/cm to 4 dB/cm @ 30 GHz. Measurements are compared to an analytical model derived for HARC. Index Terms—coplanar waveguides, high aspect ratio, micromachining, transmission lines, RF CMOS, MEMS.
I. I NTRODUCTION Monolithic microwave integrated circuits (MMICs) fabricated on silicon using CMOS technology have received much attention in the last decade. While compound semiconductor MMICs have better performance than CMOS MMICs, CMOS offers advantages including lower fabrication costs and higher integration with electronic circuits. The scaling down of CMOS transistor dimensions have increased the cutoff frequency of CMOS transistors. This has allowed the creation of several types of millimeter-wave CMOS MMICs [1]. A fundamental problem with CMOS MMICs is that the conductivity of the Si substrate can cause substantial dielectric loss in transmission lines. Much work has been dedicated to mitigating the substrate loss. The most common approach to reducing substrate loss is to fabricate transmission lines over a ground plane that shields the lines from the substrate. Microstrip and CPW transmission lines have been fabricated on Si using this approach [2]. The transmission lines are typically made from the metal layers of the CMOS process with metal 1 serving as the ground plane shield. Losses are typically greater than 3 dB/cm at 30 GHz for 50 Ω lines in these types of devices. Micromachining methods have also been employed to reduce the substrate loss of silicon. A popular micromachining
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[email protected]
approach is to reduce field exposure to the substrate through Si removal or transmission line elevation [3]. Micromachining can also be used to increase the transmission line dimensions which can also contribute to lower loss in lines on Si substrates [4, 5]. The increased dimensions reduce conductor loss through current spreading and reduce substrate loss by improved field confinement and/or ground plane shielding. Problems with these types of micromachined transmission lines include difficult and expensive fabrication methods and non-planar surfaces. Au conductor
SiO2 dielectric
ground signal ground
etched cavity
Si
Fig. 1.
3-D schematic of HARC fabricated on silicon.
Micromaching methods can be used to create high aspect ratio coplanar waveguide (HARC). Advantages of HARC include low conductor loss and excellent field confinement, which both lead to low attenuation and high isolation between transmission lines. Previously, we introduced a micromachining method that created HARC with a planar surface [6]. A problem with the method in [6] was that long thermal oxidation times limited the width of the SiO2 dielectric to less than 15 μ m. This limited the process to creating HARC with low impedance (around 20 Ω). In this paper, we incorporate a mesa merging method for creating wide SiO2 mesas in relatively short thermal oxidation times. The mesa merging method has been reported previously in literature for obtaining wide SiO2 structures [7]. The mesa merging method has been proven to effectively grow SiO2
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mesas with very large widths. This makes the fabrication of high impedance HARC possible using relatively short oxidation times. A 3-D schematic of the HARC transmission lines is shown in Fig. 1. II. FABRICATION
Step 6: Au Electroplating
Step 1: Si DRIE
The HARC is fabricated on low resistivity Si (resistivity ≈ 7 Ω·cm) in a process that combines DRIE, thermal oxidation, electroplating, and planarization (DTOEP). The fact that HARC is fabricated on low resistivity silicon makes the transmission lines potentially compatible with CMOS microwave circuits. The fabrication method, shown in Fig. 2, starts with Si DRIE to create mesas and trenches which define the topology of the HARC dielectric. The mesa widths are approximately 4.4 μ m and the trenches between mesas are 5.6 μ m. Next, wet thermal oxidation at 1050 ◦ C transforms the Si mesas into thermal oxide, creating a low-loss dielectric for the transmission lines. Thermal oxidation causes the silicon mesas to transform into solid SiO2 where the width of each individual mesa expands until it contacts and merges with an adjacent mesa. The mesa/trench pitch must be carefully designed so that the mesas merge at the exact instance when all of the silicon is consumed within the mesas. If the pitch is made too small, there will be a gaps between adjacent mesas. If the pitch is made too large, silicon slivers will exist at the center of each mesa. If the pitch is correct, a solid and wide SiO2 mesa forms with no silicon remaining in the center of the individual mesas. After the solid dielectric is formed during thermal oxidation, topside SiO2 and DRIE etches define trenches for the conductor of the transmission line. A Ti/Au seed layer is then deposited using a sputtering system with good step coverage. Good step coverage covers the sidewalls of the SiO2 mesas with conductor, which allows Au electroplating to fill both the ground and signal trenches with conductor in the next step. Next, the top of the structure is planarized using lapping and CMP to electrically isolate the signal and ground lines. A final backside DRIE removes the Si underneath the HARC which isolates the electric field from the Si substrate. This lowers the effective dielectric constant, raises the line impedance, and lowers the attenuation due to the conductivity of the Si substrate. The DTOEP method has been successfully implemented to fabricate high impedance HARC transmission lines. Thru, short, and 1600 μ m long transmission lines were fabricated for TRL calibration. The signal width, dielectric gap width, and conductor height of the HARC are 80, 80, and 60 μ m respectively. After the first DRIE etch, the Si mesa width and trench width were measured by cleaving the sample and examining the cross section in an SEM. Figure 3 (a) shows an SEM micrograph of the cross section where the mesa and trench widths were measured to be approximately 4.7 μ m and 5.3 μ m respectively. The trench depth was measured to be 63.5 μ m. Wet thermal oxidation was performed at 1050 ◦ C for 100 hours to ensure that the mesas were completely oxidized
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Step 5: Ti/Au Seed Layer
Step 2: Thermal oxidation Step 7: Planarization
Step 3: Topside SiO2 etch Step 8: Backside Si DRIE
Step 4: Topside Si DRIE Final HARC Structure G Si
SiO2
Fig. 2.
S
G
Au
The DTOEP process flow for creating HARC.
(a)
(b) Si mesa
trench
mesa merge at interface
Fig. 3. SEM micrographs of a cleaved cross section of mesas (a) before thermal oxdiation (b) after thermal oxidation.
and merged at the interfaces. Figure 3 (b) shows an SEM micrograph of a cleaved cross section after thermal oxidation. After Au electroplating, lapping and CMP planarized the top surface, yielding a final Au conductor thickness of 60 μ m. A backside 430 μ m etch of silicon to the bottom of the transmission lines completed the process. The Au resistivity was measured to be 28.5 nΩ·m. Fig. 4 shows SEM micrographs of the topside and backside of the HARC transmission line after the processing was complete. Notice that silicon grass exists on the backside of the transmission line. The silicon grass contributes to dielectric loss since the fields of the transmission line will penetrate the silicon grass region. III. T RANSMISSION L INE M ODEL A quasi-TEM HARC transmission line model has been developed by combining the element equations of parallel
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(a)
SiO2 dielectric
ground plane
(b)
center conductor
ground plane
parameter F0 represents the behavior of the fringing fields. Therefore the model conveniently represents the contributions from fields between the conductors and fringing fields by the equations described above. This is extremely useful for design optimization in terms of minimizing loss and maximizing isolation between transmission lines.
residual Si SiO2 dielectric
transmission line backside
IV. E XPERIMENTAL R ESULTS Fig. 4. SEM micrographs of a HARC thru line showing (a) the topside after planarization and (b) the backside after backside Si DRIE.
plate waveguide and infinitely thin CPW. Due to lack of space, the derivation of the model will not be discussed in detail, rather we will summarize the approximate forms for the transmission line output parameters including characteristic impedance, effective dielectric constant, and attenuation which are respectively given by
η0 Z0 ≈ 2 (h/d + 2F0 ) (εr h/d + (1 + εsub )F0 ) εe f f ≈
(1)
εr h/d + (1 + εsub )F0 h/d + 2F0
(2)
α = αc + αd .
(3)
Material properties are defined as follows: ω is the angular frequency, μ0 is the permeability of free space, η0 is the impedance of free space, εr is the dielectric constant of SiO2 , εsub is the dielectric constant of silicon, σ is the conductivity of Au, σsub is the conductivity of silicon, and tanδ is the effective loss tangent of the dielectric gap (including contributions from SiO2 and the residual silicon). The HARC geometrical properties are defined as follows: h is the conductor height, d is the dielectric gap width, s is the signal line width, and F0 is a parameter that depends on s and d and is derived using conformal mapping to analyze infinitely thin CPW [8]. The attenuation is given by the sum of conductor loss, αc , and dielectric loss, αd . The conductor loss is approximated by (h/d)2 Rs /h + (2F0 )2 RGSG 1 . (4) αc ≈ 2Z0 (h/d + 2F0 )2 The conductor loss is found by combining the resistance of parallel plate waveguide and infinitely thin CPW. Rs = 2ω μ0 /σ is the surface resistivity of Au. The infinitely thin CPW resistance is shown in Eq. 4 as RGSG and is derived by combining perturbation theory and Wheeler’s inductance rule. The dielectric loss is approximated by
αd ≈ Z0 (ωε0 εr tanδ h/d + σsub F0 ) .
(5)
These equations provide a relatively simple forms forms for analyzing the device output parameters. Notice that equations depend heavily on the height to gap aspect ratio, h/d, and the parameter F0 . The parameter h/d represents the parallel plate waveguide contributions to the behavior of the device and the
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Microwave measurements were taken using an Agilent E8364A network analyzer and are compared to the analytical transmission line model. The transmission line parameters were measured before and after Si was removed underneath the substrate. The characteristic impedances of the transmission lines were measured by first performing a short-open-loadthru (SOLT) calibrations using a 50 Ω calibration substrate from 1 - 50 GHz. Next, S parameters were measured from the HARC thru line and converted into ABCD parameters using the 50 Ω reference impedance.The characteristic impedance was calculated using Z0 = Re( B/C). Fig. 5 shows measurements and model calculations of characteristic impedance versus frequency of the thru line. The impedance of the line increases after silicon is removed because the effective dielectric constant becomes lower and the lossy substrate no longer draws current. Fig. 5 shows that the measured impedance is much lower than the calculated impedance before silicon is removed. This is because the model depends on a quasi-TEM approximation. This approximation is not as accurate when a lossy substrate is present. The model does not account for all the extra current that is drawn into the substrate and therefore predicts a higher than actual impedance. When silicon is removed, the quasi-TEM approximation is more accurate because current will not flow through the substrate. Thus the model predictions better match measurements after silicon is removed. Thru-reflect-line (TRL) calibrations of the HARC transmission lines were performed to extract the propagation constant from 1 - 50 GHz. After calibration, S parameters were measured in each line and converted to ABCD parameters, and the propagation constant was calculated using α + jβ = (1/L)cosh−1 (A) where α is the attenuation constant, β is the phase constant, and L is the line length. Fig. 6 shows measurements and calculations of effective dielectric constant versus frequency of the 1600 μ m long line. The lower effective dielectric constant after Si is removed is demonstrated in Fig. 6. Also demonstrated is the fact that the effective dielectric constant stays relatively constant with frequency after silicon is removed. This is important because it shows that dispersion is greatly decreased by removing the lossy substrate. The model predictions match the measurements well both before and after silicon is removed. Fig. 7 shows measurements and calculations of attenuation constant versus frequency of the 1600 μ m long line. Fig. 7 shows that the loss decreases substantially after silicon is removed. This is because the impedance increases and the field is no longer exposed to the lossy substrate. Although the measured loss is much lower after Si is removed, it
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Attenuation Constant, α (dB/cm)
Characteristic Impedance, Z0 (Ω)
80 70 60 50 40 30 20 Before Si removal After Si removal Analytical Model
10 0
0
10
20
30
40
40 35 30 25 20 15 10 5 0
50
Frequency (GHz)
Before Si removal After Si removal Analytical Model
45
0
10
20
30
40
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Frequency (GHz)
Fig. 5. Characteristic impedance versus frequency of the thru line before and after Si removal.
Fig. 7. Attenuation constant versus frequency of the 1600 μ m long line before and after Si removal.
could be lowered even more if the residual silicon can be eliminated underneath the transmission lines. Using the model, we calculated that the residual silicon causes the effective loss tangent to be approximately 0.13. Thus the loss can be further lowered by improving the fabrication process. Fabrication improvement for removing residual silicon is presently being pursued.
2, and the attenuation constant to be 4 dB/cm at 30 GHz. Ongoing work is being pursued to improve device performance by removing residual silicon. ACKNOWLEDGMENTS We thank Bob York for discussion on modeling and Chuck Hirbour at Technic, Inc. for help with Au electroplating. This research was supported by the Kavli Foundation.
Effective Dielectric Constant, εeff
20 Before Si removal After Si removal Analytical Model
18 16 14 12 10
R EFERENCES
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[1] H. Shigematsu, T. Hirose, F. Brewer, and M. Rodwell, “Millimeter-wave CMOS circuit design,” IEEE Trans. Microwave Theory Tech., vol. 53, no. 2, pp. 472–477, Feb. 2005. [2] C. H. Doan, S. Emami, A. M. Niknejad, and R. W. Brodersen, “Millimeter-wave CMOS design,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 144–155, Jan. 2005. [3] C. Y. Chi and G. M. Rebeiz, “Planar microwave and millimeter-wave lumped elements and coupled-line filters using micromachining techniques,” IEEE Trans. Microwave Theory Tech., vol. 43, no. 4, pp. 730– 738, Apr. 1995. [4] E. R. Brown, A. L. Cohen, C. A. Bang, M. S. Lockard, B. W. Byrne, N. M. Vandelli, D. S. McPherson, and G. Zhang, “Characteristics of microfabricated rectangular coax in the Ka band,” Micro. Opt. Tech. Let., vol. 40, no. 5, pp. 365–368, Mar. 2004. [5] T. L. Willke and S. S. Gearhart, “LIGA micromachined planar transmission lines and filters,” IEEE Trans. Microwave Theory Tech., vol. 45, no. 10, pp. 1681–1688, Oct. 1997. [6] S. T. Todd, X. T. Huang, J. E. Bowers, and N. C. MacDonald, “High aspect ratio CPW fabricated using silicon bulk micromachining with substrate removal,” in APMC 2009, Singapore, Dec. 2009. [7] C. Zhang and K. Najafi, “Fabrication of thick silicon dioxide layers for thermal isolation,” J. Micromech. Microeng., vol. 14, pp. 769–774, 2004. [8] C. P. Wen, “Coplanar waveguide: A surface strip transmission line suitable for nonreciprocal gyromagnetic device applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 17, no. 12, pp. 1087–1090, Dec. 1969.
6 4 2 0
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Frequency (GHz) Fig. 6. Effective dielectric constant versus frequency of the 1600 μ m long line before and after Si removal.
V. C ONCLUSION A novel micromachining process has been developed to create high aspect ratio coplanar waveguides on a low resistivity silicon substrate. A high impedance line was created using a mesa merging process for creating wide SiO2 dielectric gaps. Silicon was removed underneath the transmission line to raise impedance and lower loss. Microwave measurements showed the impedance to be 57 Ω, effective dielectric constant to be
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