microprocessor-controlled, shunt voltage-regulator for

MICROPROCESSOR-CONTROLLED, SHUNT VOLTAGE-REGULATOR FOR SATELLITE SYSTEMS

A THESIS SUBMITTED TO THE COLLEGE OF ENGINEERING OF SADDAM UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE IN ELECTRONIC ENGINEERING & COMMUNICATIONS

BY

SUFYAN TAIH FARAJ ( B.Sc. Eng., 1992 )

December 1994

Rajab 1415

‫بسم اهلل الرمحن الرحيم‬

‫واتقوا اهلل‬ ‫ويعلمكم اهلل‬ ‫واهلل بكل شئ عليم‬ ‫صدق اهلل العظيم‬ ‫من األيت ‪/ 282‬سورة البقرة‬

DEDICATION:

To the Wind Beneath My Wings

My Beloved Father, Mother, Montadhar, Suhaib, & Raghad

Sufyan

ACKNOWLEDGMENTS

"Praise be to ALLAH, Lord of the whole creation"

Then, I would like to express my deepest gratitude and appreciation to my supervisor Dr. Majid A. Al-Taee who gave me great support, encouragement, and valuable advice throughout the progress of this work. I also would like to direct my sincere appreciation to Dr. Kader H. AlShara for his co-supervision and untiring efforts throughout my study.

Gratitude is owed to Prof. Mazin A. Kadhim, Dean of the College of Engineering for his generous care for postgraduate students. Great thanks are devoted to the former head of the Department of Electronic Engineering and Communications: Prof. Faiq J. Al-Azzawi, and to the present head Prof. Fawzi M. Al-Naima for their continuous encouragement and support.

My thanks are due to the staff members of Electronic Engineering and Communications Department, especially to Fatin and Batool, for making available the department facilities. Finally, I would like to express my thanks to my colleagues and friends.

ABSTRACT In this thesis, an approach to design a space-based shunt voltage-regulator is presented in which a microprocessor is used as a controller. The proposed system meets the demands of spacemissions, i.e., reliable, efficient, flexible, low weight, low volume, and less development time. Such system responds to future demands by permitting real-time modification of system parameters for system optimization which has a special importance in the event of an anomaly. The design and performance of the individual components of such a regulator system are discussed in detail with a particular reference to 30 W prototype. However, the prototype design is such that it can be easily expanded to higher ratings.

The bus voltage regulation is achieved by two stages. First, coarse regulation is done by switching the solar array sections on and off via a solar array switching unit (SASU). Second, fine regulation is done using a small PWM shunt that is designed to regulate the output of one solar array section. Thus, power losses are reduced and assembly of the unit is simplified. The design reliability of the system is enhanced further by constructing a second (Standby) regulator system to come into action in case of the original (Active) regulator becomes faulty. As the microprocessor needs not be dedicated to control the SASU and PWM, it can simultaneously be used for the entire power system monitoring and housekeeping. Hence, a single-integrated power conditioning and control unit (PCCU) to achieve various jobs that are required by the space-based systems can be implemented.

The power stage design of the PWM shunt regulators is based on power MOSFET as the main switching device and a simple switching-aid network to ensure safe and reliable operation. The behavior and performance of this stage are analyzed theoretically by deriving a mathematical model. The validity of proposed model is examined by comparing the predicted regulator performance with that measured experimentally. A reasonable correlation between the predicted and measured performance is obtained at various operating conditions.

CONTENTS Page No. ABSTRACT................................................................................................

ACKNOWLEDGMENTS...........................................................................

ABBREVIATIONS and SYMBOLS..........................................................

CONTENTS................................................................................................

Chapter 1: INTRODUCTION..................................................................... 1.1 General Background.............................................................................. 1.2 Literature Review.................................................................................. 1.3 Scope of the Work.................................................................................

Chapter 2: MICROPROCESSOR-CONTROLLED SHUNT REGULATORS, STATE OF THE ART................................................ 2.1 Introduction............................................................................................ 2.2 Solar Cell Array..................................................................................... 2.2.1 Solar Cells......................................................................................... 2.2.2 Solar Array Modeling....................................................................... 2.3 Shunt Regulators.................................................................................... 2.4 Microprocessor Control of Shunt Regulators........................................ 2.5 Fault Tolerance Aspects......................................................................... 2.5.1 Standby Sparing................................................................................ 2.5.2 Watchdogs......................................................................................... 2.6 Summary and System Specifications.....................................................

Chapter 3: MICROPROCESSOR-BASED SYSTEM CONTROLLER........................................................................................ 3.1 Introduction............................................................................................. 3.2 Hardware Design.....................................................................................

3.2.1 Microprocessor System....................................................................... 3.2.2 PWM Modulator.................................................................................. 3.2.3 Solar Array Switching Unit................................................................. 3.2.4 Fault Tolerance.................................................................................... 3.3 Software Design....................................................................................... 3.3.1 Microprocessor System Design............................................................ 3.3.2 Regulation Software............................................................................. 3.3.3 Fault Tolerance Software...................................................................... 3.4 Controller Performance..............................................................................

Chapter 4: POWER CIRCUIT DESIGN AND PERFORMANCE…….......... 4.1 Introduction................................................................................................. 4.2 Solar Array Section Simulators.................................................................. 4.3 Power Circuit Elements.............................................................................. 4.3.1 MOSFET Shunt Regulator.................................................................... 4.3.2 Output Filter.......................................................................................... 4.3.3 System Duplication............................................................................... 4.4 Theoretical Analysis.................................................................................. 4.5 Model Validity........................................................................................... 4.6 System Performance..................................................................................

Chapter 5: CONCLUSIONS AND FUTURE WORK.................................... 5.1 Conclusions............................................................................................... 5.2 Future Work...............................................................................................

REFERENCES.................................................................................................

APPENDICES

ABBREVIATIONS and SYMBOLS

ADC

Analog-to-digital converter

BSR

Bit set/reset

C

Capacitance

o

Degree Centigrade

C/D

Control/data

C&DH

Communications & data handling

CLK

Clock

CR/DR

Charge regulator/discharge regulator

CS

Chip select

EPROM

Erasable programmable read-only memory

F

Farad

f

Switching (modulation) frequency

g

Transconductance

H

Hexadecimal

I

Current

I/O

Input/output

IPS

Isolated power supply

J

Joule

K

Boltzman's constant

o

Degree Kelvin

LED

Light-emmiting diode

MPP

Maximum power point

MPU

Microprocessor unit

N

Number of solar array sections

np

Parallel-connected array sections

ns

Series-connected array sections

P

Power

PCCU

Power conditioning & control unit

PPI

Programmable peripheral interface

PWM

Pulse width modulation

C

K

Q

Electronic charge

R

Resistance

RAM

Random-access memory

rs

Solar array internal series resistance

rsh

Solar array internal shunt resistance

SASU

Solar array switching unit

SBPS

Space-based power system

T

Modulation period ( = 1/f )

To

Absolute temperature

USART

Universal synchronous/asynchronous receiver/transmitter

Vbus

Bus voltage

Voc

Solar array open circuit voltage

Vref

Reference voltage that represents the regulated bus voltage

W

Watt

η

Efficiency

τ

Pulse width

Chapter 1: INTRODUCTION

1.1 GENERAL BACKGROUND Since the advent of space age, photo voltaic cells have been used as the main energy source for spacecraft power generation. Other types of generators (such as nuclear generators) are not of a practical use for most of space applications ( e.g. communications satellites) yet. As space-based power systems (SBPSs) pose severe problems mainly due to mass and volume limitations, they should be of a minimum weight and volume, high reliability, flexibility, efficiency, and of a low cost as possible [1]. The SBPS consists of: a) A primary energy source; which is usually solar cells array that converts the electromagnetic sun radiation into an electrical energy. b) A secondary source; which can be substituted when needed, e.g., during an eclipse period (usually a battery of electrochemical accumulators is used). c) Power conditioning and control circuits.

The outputs of the solar cells array and storage battery are to be conditioned so as to match with the requirements of the various on-board equipment. The power delivered by the solar array depends on the selected operating voltage and the extent of irradiation degradation of the solar cells. Also, the solar cell voltage is strongly dependent on temperature as during an eclipse, the cell temperature can drop to -180 oC. So just after an eclipse, during the illumination phase when the temperature is in order of a few tens of degrees, the voltage delivered by the cell is about 2.5 times its nominal operating value [2]. The storage battery has to be charged from the solar array during the orbital day and discharged to provide power during the orbital night or when the load demand exceeds the solar array capability. All these functions are carried out by the power conditioning and control unit (PCCU) which can be classified according to their operating principle into two main types [3]:

(i) Dissipative systems; which do not extract maximum power from the solar array, and hence dissipate any unused power by employing linear shunt regulators. (ii) Nondissipative systems; which can extract the maximum power from the solar array and hence dissipate very little power internally. A comparison between dissipative and nondissipative power systems is presented in Table (1.1).

Irrespective whether the PCCU uses dissipative or nondissipative techniques, the bus voltage can be regulated or unregulated. Hence, PCCUs can also be grouped into [2,3]:

(i) Unregulated bus system; where the battery is placed in parallel with the solar array, hence it defines its operating voltage together with the user load characteristics. Any surplus energy is then dissipated using some kind of damping facility, as shown in Fig.(1.1-a). Table (1.2) summarizes the advantages and disadvantages of the unregulated bus systems. (ii) Regulated bus system; in which a shunt regulator defines the solar generator's voltage. The storage battery is connected to the power supply through a charge/discharge regulator, as shown in Fig.(1.1-b). The advantages and disadvantages of the regulated bus systems are given briefly in Table (1.3).

In both cases of regulated and unregulated buses, the spacecraft or satellite subsystems require different positive and negative voltages. Therefore, the bus voltage is further regulated, leveled up, leveled down, and/or inverted using regulators and dc-dc converters. If the process of further regulation, etc., is carried out in the main power system for all loads, then such concept is known as a centralized regulation concept. In the other side, if this process is carried out separately at each load, then such concept is known as a decentralized regulation concept [3].

1.2. LITERATURE REVIEW In spite of the fact that the problem of designing efficient and highly reliable power systems to work on spacecraft begins in the first days of space age, only a limited number of technical papers were published on this subject. Moreover, most of these published papers do not go into the details of the real engineering difficulties and their problems' solutions. However, some important insights concerning the subject that can be found in the literature are summarized as follows:

Chetty, P. [4] had discussed in 1978 some new techniques to improve the performance of spacecraft power systems. He has presented a technique to improve the PCCU for regulated bus spacecraft power systems. The regulated bus concept of the PCCU has several advantages over the unregulated bus concept for geostationary spacecraft applications (Table 1.2). However, the regulated bus concept has two main drawbacks, these are:

a) Excess solar power has to be totally or partially dissipated in a shunt regulator; this affects the thermal and mechanical design of the power system. b) Three types of regulators are required to control the power flow to and from the bus during the various operating modes encountered. These constraints lead to a complex bus voltage control when redundancy is to be incorporated.

A design approach to PCCU has been presented primarily to minimize the effects of the above two drawbacks by building a single common control unit, consisting of a reference voltage source, error amplifier, attenuator, and pulse-width modulator; drives the power stages of shunt, charge, and discharge regulators.

Chetty, P. et. al. [1] had presented in 1980 a new approach to the design of satellites' power systems in which a microprocessor unit (MPU) was used as a controller for a digital shunt regulator (DSR). In their work, a dissipative analog shunt was used to achieve fine regulation. While, the MPU's job was simply to add or remove solar array sections from the bus, thus coarse regulation could be achieved. They claim that for solar power systems, the DSR has superior performance compared with other types of shunt regulators.

Deskevich, J. [5] and Chetty, P. [3] were presented in 1984 and 1985 respectively, the main features of the Fairchild Leascraft power system. Various building blocks of the Leascraft power system were described. Also, results of detailed trade-off studies for the selection of the regulation concept were presented.

Cho, B. and Lee, C. [6] had developed in 1988 a comprehensive

large-scale power system

modeling technique using a multiport coupling method to facilitate the design and analysis of the spacecraft power system. Power subsystem or component model development from empirical data and reduced-order model generation using the complex curve-fitting technique were also introduced. It was shown that the modular approach allows the model to be flexible, verifiable, and

efficient for meeting various modeling and analysis needs for dc, small-signal, and large-signal analysis.

Lee, J. et.al. [7] presented in 1988 the modeling of a complete spacecraft power processing system. Component models were developed, and several system models including a solar array switching system, partially shunted solar array system, and Cosmic Background Explorer (COBE) system were simulated. They had declared the use of solar array switching as a replacement for conventional techniques to regulate the bus voltage for advanced space missions. The modes of operation of the power system such as shunt, battery-charge, and battery-discharge modes were simulated for a complete orbit cycle.

Nelms, R. and Grigsby, L. [8] presented in 1989 a modular state variable approach for dc spacecraft power system modeling and simulation. Each modular component was treated as a multiport network, and a state model was written with the port voltages as the input. The state model of a component was solved independently of the other components using its state transition matrix. The state variables of each component were updated assuming that the inputs are constant. Network analysis principles were then utilized to calculate the component inputs.

1.3. SCOPE OF THE WORK The work presented in this thesis includes the design and implementation of a space-based shunt voltage-regulator. The centralized regulation concept that utilizes a nondissipative regulated bus is considered with the aim of using the proposed system in a small or medium capacity communications satellite. The overall system control is achieved using 8-bit microprocessor. The scope of the work reported in this thesis can be summarized as follows:

Chapter 2 reviews the basic components of the microprocessor-controlled shunt regulators. These include the solar cell array, shunt regulators, microprocessor control, and various fault tolerance aspects. This chapter is concluded with a specification of the proposed regulator system.

Chapter 3 presents the design of both the hardware and software of the microprocessor-based system controller. This includes the microprocessor system, the solar array switching unit, the PWM modulator, and the fault tolerance. The controller performance is also considered in this chapter.

Chapter 4 describes the design and performance of the power circuit. This includes of the solar array simulators, MOSFET shunt regulator, output filter, and the system duplication. Then, the system performance is investigated by comparing the results obtained from the theoretical analysis with these obtained experimentally.

Finally, the most important conclusions of the work are summarized in chapter 5 together with suggestion for topics of future investigation.

TABLE (1.1): Comparison of Dissipative and Nondissipative Spacecraft Power Systems [3].

Parameter

Dissipative Systems

Radiation damage

Slow degradation of solar array occurs with accompanying shift in operating voltage. Additional power at the beginning of life is not properly utilized.

Change in battery voltage

The array voltage varies with battery voltage changes and load condition in un regulated bus systems.

Array design constraints

Thermal and mass constraints

Nondissipative Systems More power is available at the beginning of life to operate additional equipment or increase its operating time.

Improved array loading efficiency, especially at the end of eclipse when battery voltage is low and array voltage is high. The choice of array voltage Array voltage can be depends on electronics, battery, selected independently . thermal design, etc.; array The design is simple. design freeze is delayed. In periods of excess power, heat is usually dissipated in electronic circuit which, therefore, require heavy heat sinks.

Heat dissipation is limited to a low and nearly constant value.

TABLE (1.2): Advantages and Disadvantages of Unregulated Bus Power Systems [3]. Advantages

Disadvantages

1- Easy to avoid single-point failure.

1- Load regulator/converter units complex.

2- Simple interface. 3- Units are buffered from noise on bus.

2- Significant weight penalty, particularly with input filter if unit must work over a wide bus voltage range. Unit switch-on surge currents may prevent operation of solar array at maximum power point.

TABLE (1.3): Advantages and Disadvantages of Regulated Bus Power Systems [3]. Advantages 1- Permits lighter load regulator/converter units.

Disadvantages 1- Buffering of units from bus is limited.

2- Dissipation of excess solar array power in 2- Some loads may run directly from bus. shunt regulator (for dissipative systems). 3- Low bus impedance. 4- Solar array operating point is fixed.

3- Three types of regulators are required (shunt, charge, and discharge regulators).

Chapter 2: MICROPROCESSOR-CONTROLLED SHUNT REGULATORS, STATE OF THE ART

2.1 INTRODUCTION In this chapter a brief theoretical background related to the basic elements of the microprocessor for controlled shunt regulators is presented. Firstly the primary energy source in space power systems, the solar cells, is introduced with explanation of the maximum power transfer principle. Then, different types of shunt regulators are discussed along with the importance of using the MPU for controlling the shunt regulator in a SBPS. Finally, this chapter is concluded with a specification for a particular prototype system.

2.2 SOLAR CELL ARRAY Solar radiation is the only external energy source for most of space systems. On-board energy sources (nuclear generators), are not yet satisfactory for geostationary telecommunications satellites or for most of other space applications. Nevertheless, during the first few hours following the injection into transfer orbit and prior to the deployment of solar panels, the electrochemical accumulators are the primary energy source [2].

2.2.1 Solar Cells When a voltage is developed due to radiation falling on a p-n junction, it is known as photovoltaic effect and the device is called a photovoltaic cell. Solar cells are basically photovoltaic cells with an increased active area [9]. Silicon is the most widely used material in solar cells. A typical current to voltage (I-V) characteristic is shown in Fig.(2.1). The I-V characteristic depends on the temperature (voltage falls by 50 percent if the temperature varies from 27 oC to 150 oC). The average output

efficiency of a cell decreases under the effect of the radiation and drops by about 30 percent in seven years [2]. Recently, more efficient cells using materials such as Aluminum and Gallium Arsenide were introduced to replace Silicon cells.

The I-V and power-voltage (P-V) characteristics of the solar cell array are temperature dependent as shown in Fig. (2.2). The solar cell array output vanishes completely when the satellite enters an eclipse. Further, when the satellite leaves an eclipse, the solar cell array output is extremely high for some time as the array temperature is very low. So, it is evident that the array voltage at maximum power output varies. In order to minimize the thermal problems and to improve the efficiency of the overall power system, it is necessary that the maximum power point (MPP) be continuously tracked. Hence, the maximum power tracking approach must be used. As summarized below, there are various techniques for maximum power tracking [3]: 

Technique 1 - This technique is based on the characteristic of any solar cell array, that is the ratio of voltage at the MPP and that at open circuit of the array is approximately constant (between 0.70 and 0.75). Hence, an auxiliary (small) array which is maintained in the same environment as the main array and an loaded is employed to monitor the open circuit voltage. This is used to control the operating point on the main solar array such that the maximum power is continuously transferred to the loads and the battery.



Technique 2 - Usually, temperature is the main factor affecting the MPP of a solar cell array. Hence, the temperature of the solar array is measured continuously to control its operating point.



Technique 3 - The solar cell array is connected to the battery through an interface which provides maximum power transfer. As the battery voltage remains constant during a switching period at this interface, the current ripple is representative of the power ripple. The operating point on the solar array is moved continuously from open circuit voltage towards short circuit current side. As this process is continued, the ripple reaches a peak. The peak is sensed by a peak detector and the process is reversed. Thus, the operating point is maintained near the MPP.



Technique 4 - The product of output current and voltage is generated continuously as the solar cell array is loaded. This is fed to a peak detector. When the peak is sensed, the loading is reversed. This facilitates operation close to the MPP.



Technique 5 - Referring to Fig.(2.3), it is seen that the ac and dc impedences of a solar cell array are equal at the MPP. This property is made use in sensing the MPP. A ripple is injected into the solar array bus, and dV/dI and V/I are continuously measured and compared to control the operating point such that the maximum power is transferred from the solar array.



Technique 6 - As any solar cell array is loaded gradually, the rate of change of power output with respect to output current changes its slope as the MPP is crossed. A low-frequency perturbing signal is injected into the solar array which causes small changes in the array power. The value of dP/dI is continuously measured and the operating point is controlled such that dP/dI becomes zero. Thus, the operating point is held close to the MPP and the maximum power is transferred from the solar cell array.

2.2.2 Solar Array Modeling Several approaches were proposed for modeling the solar array [6]. First, it is possible to represent an array by interconnecting individual solar cell models. Advantages of this approach are that the parameters for the individual-cell model readily obtained using established measurement and calculation procedures, and the effect of parameters variation can easily be included. However, this approach becomes inefficient when larger arrays are treated due to large memory an amount of computation required.

Another approach is to use a single-cell model to simulate the entire array (macro model approach). Parameters can be obtained by incorporating the measurement/calculation of the individual cells and their interconnection scheme, or simply by making terminal measurements of the array itself. The major advantage of this approach is the ability to minimize computational time and memory requirements. However, shadowing and individual cell faults here cannot be included easily like in the case of individual-cell model approach.

Another approach can be developed using a combination of the macro model and the individual-cell model. This requires to determine at least two sets of model parameters - one set for the group of individual cells and one set for the group of macro models. Using the macro model approach, shown in Fig.(2.4), a dc and small-signal models can be obtained as follows [6]:

a) DC Model: A standard solar cell dc model is shown in Fig.(2.5-a). This model provides good first order predications of the dc behavior of the solar cell. The analytical macro model, Fig.(2.5-b), is described with lumped parameters as a function of the number of cells in series (ns) and parallel (np) as follows:

𝐼𝑜 = 𝑛𝑝 𝐼𝑠 − 𝐼𝑑𝑜 𝑒𝑥𝑝

𝑄.𝑉𝑑 𝐾.𝑇𝑜

𝑉

−1 −𝑟𝑑

𝑠ℎ

(2.1)

where, 𝑉

𝐼

𝑉𝑑 = 𝑛0 + 𝑛𝑜 𝑠

𝑝

(2.2)

and, Is = light generated current, Ido = reverse saturation current, Io = output current, Vo = output voltage, Q = magnitude of the electronic charge (1.602 * 10-19 C), K = Boltzman constant (1.381 * 10-23 J/oK), To = absolute temperature, and rsh = internal shunt resistance. The Newton Iteration Method can be used to solve Vo or Io for Io or Vo, respectively. b) Small Signal Model: The standard small-signal ac solar cell model is shown in Fig.(2.6-a). This model is simple and produces good first-order results just like the dc model. As shown in Fig.(2.6-b), an equivalent macro model can be generated with lumped parameter values as a function of ns and np based on cell parameter values.

2.3 SHUNT REGULATORS Shunt regulator is one form of feedback regulators. The control device (usually either a power bipolar transistor or a power MOSFET) in this case is in the shunt path. While, the control device is used in the series path in the case of series regulators. Although the shunt regulator is not as efficient as the series regulator, it has the advantage of greater economy, simplicity, and lower size and weight. It is recommended for power systems were load do not change very often, such as communications satellites [1,10].

Basically, in regulated bus systems, the shunt regulator is connected in parallel with the solar array to define the solar generators voltage, as illustrated in Fig.(1.1-b). Excess solar array power is dissipated in the shunt regulator. This is termed a full-shunt regulation. One disadvantage of the full-shunt regulator is that: under a zero-load condition it must dissipate the whole output power of the entire array. Another technique is to use a partial-shunt regulation concept, as shown in Fig. (2.7), which reduces the peak power dissipation 30-50 percent of the dissipated power in functionally equivalent full-shunt [7].

In a partial-shunt system, the power sections are placed across a part of the total number of the series-connected solar cells. Hence, the solar cell array is divided into two sections, upper and lower. The shunt current used to regulate the bus voltage is supplied by the lower solar array. The output current of the lower solar array is the sum of the shunt and the current of the upper solar array. Shunt regulation can be achieved using either a dissipative analogue shunt or a pulse-width modulated (PWM) shunt:

a) Dissipative Analogue Shunt: The dissipative analog shunt, shown in Fig.(2.8), comprises a shunt transistor operating in active mode as the control device [11]. The regulated dc output voltage across RL is the same as the voltage across the shunt branch containing the power transistor. The voltage of the shunt branch, in turn, is determined by the amount of current in the base circuit, which is controlled by a comparison amplifier. The difference between the sensed voltage and the fixed reference voltage is used to control the current through the shunt. The output voltage of this circuit is maintained constant because the current drawn by the shunt transistor is varied as the unregulated dc input voltage or the load current changed.

b) PWM Shunt: The PWM shunt uses the control device as a switch, usually a power transistor operated in its most efficient states; ON or OFF. Therefore, the power dissipation is considerably less compared with the analogue shunt and consequently, a smaller rating devices and heat sinks can be used. The response time of the PWM shunt is somewhat slower than the dissipative analogue shunt, however, this can be improved by increasing the PWM modulated frequency [10].

Fig.(2.9) shows a schematic of a PWM shunt regulator. The amplifier error-voltage is compared with a sawtooth or triangular waveform to generate the PWM signals. The width of the generated pulses is proportional to the supplied error-voltage. The PWM signal is used to switch the transistor

(Q) into its ON or OFF states. Thus, the emitter current of the transistor (i.e. through R sh) is controlled and the bus voltage is regulated [4].

The type and characteristics of the control device used to construct the shunt regulator affect the performance of the regulator system significantly. During the recent years, the Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs) have become established in a wide variety of power control and conversion applications. Most of these applications require the MOSFET to be switched on and off at a high frequency [12]. Prior to the development of power MOSFETs, the only device available for high-speed, medium-power applications was the power bipolar transistor due to high average chip current density and good geometrical control of the active transit (base) region width [13]. Despite the attractive power ratings achieved for bipolar transistors, there exist several fundamental drawbacks in their operating characteristics. In comparison to power MOSFETs, bipolar devices have lower input impedance, longer switching times, smaller safe operation area, and less efficient parallel operation due to current hogging and the need for ballast resistors [14]. Also, the bipolar transistor is a current controlled device. A large base drive current, typically one-fifth to one-tenth of the collector current, is required to maintain the transistor in the on-state. Even large reverse base drive currents are necessary for obtaining high speed turn-off [15].

The power MOSFET is controlled by a signal applied to the gate of the MOSFET. The control signal is essentially a bias voltage with no significant steady-state current flow in either the on-state or off-state. Even during the switching of the device between these states, the gate current is small at typical operating frequencies (which can be made up to 100 kHz). The high input impedance is a primary feature of the power MOSFET that greatly simplifies the gate drive circuitry and reduces the cost of the power electronics.

2.4 MICROPROCESSOR CONTROL OF SHUNT REGULATORS Microprocessor control of power-electronic equipment is attractive because it offers the possibility of improved reliability and increased flexibility. These advantages inevitably result from a reduction in the complex control circuitry, which may be progressively replaced by microprocessor software. It is then possible to change the system characteristics without altering the hardware. The aim of all microprocessor-control design is to implement as many of the control functions as possible in software, thereby increasing reliability and reducing hardware and manufacturing costs. Improvements in maintenance and servicing of power-electronic equipment are also achieved using

microprocessor-based fault monitoring, self-interrogatory and diagnostic capabilities. For example, system variables such as current and voltage can be monitored and stored in memory prior to a fault. This information can then be used for alarm, shutdown, or diagnostic purposes [16].

It is possible to proceed directly and attempt to implement, using a microprocessor, one of the previously developed hardwired analogue or discrete digital-control techniques. However, to take full advantage of the shift in emphasis from hardware to software design, and to make effective use of the computing power of the microprocessor, a new and more fundamental approach to system design is required.

In general, the design constraints differ in the various hardwired analogue and microprocessor implementations, and therefore careful consideration of the implication of the various hardware/software trade-offs, and there effects on the speed, accuracy, and timing of the various control loops are necessary in order to achieve the optimum design solution. These considerations may well involve rethinking the whole control philosophy, in terms of the microprocessor control technology, if space demands for high reliability and flexibility, low cost, and minimum weight and volume voltage regulators are to be met.

Solar power systems require bus regulators, of which the DSR (Digital Shunt Regulator) is superior compared to other types of shunt regulators because its weight and volume do not increase in proportion to power requirements as others do, which is the main advantage of DSR. The DSR also offers high reliability and it is of a low cost. Solar array switching technique is used as a part of the PCCU to regulate the bus voltage croasly. This was recently recommended for advanced space missions [1,7]. A block diagram of a power system using an MPU-controlled DSR is shown in Fig.(2.10). The microprocessor is used to switch the solar array sections ON and OFF according to the value of the shunt current. As illustrated in Fig.(2.10), the DSR contains a small dissipative analogue shunt for fine regulation.

There are four basic configurations for the solar array switching unit (SASU), which are: seriesswitching series-array, shunt-switching series-array, series-switching parallel-array, and shuntswitching parallel-array configurations. They are shown in Fig.(2.11).

2.5 FAULT TOLERANCE ASPECTS Fault tolerance is an attribute that is designed into a system to achieve some design goal. Just a design must meet many functional and performance goals, it must numerous other requirements as well. The most prominent of the additional requirements are: reliability, availability, safety, performability, dependability, maintainability, and testability. Fault tolerance is one system attribute capable of fulfilling some or all of such requirements.

The applications of fault tolerant systems can be categorized into four primary areas: long-life applications, critical computations, maintenance postponement, and high availability. Each application presents different design requirements and challenges. Satellites are common examples of long-life applications as they are required to function correctly in space for extended period of time. The cost of designing, building, and launching of a satellite is much too high to allow electronic failures to render the satellite ineffective in space. Even though the space shuttle is now capable of retrieving satellites for repair, the cost of such repair is still extremely high, and many satellites are in orbits beyond the reach of the shuttle. Consequently, fault tolerance is considered an essential requirement in satellite systems. Unlike other applications, long-life systems can often allow extended outages as long as the system can eventually be made operational once again [17].

To implement a fault tolerant system, redundancy has to be added to the original system. This include the addition of information, resources, or time beyond what is needed for normal system operation. The redundancy can take one of the following forms [17,18];

- Hardware redundancy; which is the addition of extra hardware, usually for the purpose of either detecting or tolerating faults. - Software redundancy; which is the addition of extra software, beyond what is needed to perform a given function, to detect and possibly tolerate faults. - Information redundancy; which is the addition of extra information beyond that required to implement a given function. Error detecting codes are examples of such type of redundancy. - Time redundancy; which uses additional time to perform the functions of a system such that fault detection and often fault tolerance can be achieved.

As semiconductor components have become smaller and less expensive, the concept of hardware redundancy has become more common and more practical. There are three basic forms of hardware

redundancy; passive, active, and hybrid. Each form has advantages and disadvantages that are important in different applications. The key differences are as follows: 

Passive techniques rely strictly on fault masking.



Active techniques do not use fault masking but instead employ detection, location, and recovery techniques (reconfiguration).



Hybrid approaches employ both fault masking and reconfiguration.

The choice of hardware approach depends heavily on the application. Critical computation applications usually mandate some form of either passive or hybrid redundancy because momentary, erroneous results are not acceptable in such systems. The highest reliability is usually achieved using the hybrid techniques. In long-life and high availability applications, active approaches are often used because it is typically acceptable to have temporary, erroneous outputs on condition that the system can be restored quickly to an operational state using reconfiguration techniques. In terms of hardware, the cost of the redundancy techniques increases as the designer go from active to passive and finally to hybrid.

Active hardware redundancy does not attempt to prevent faults from producing errors within the system. They rather attempt to achieve fault tolerance by error detection, error location, and error recovery. Consequently, active approaches are most common in applications that can tolerate temporary, erroneous results as long as the system reconfigures and regains its operational status in a satisfactory length of time. Satellites are good examples of applications of active redundancy. Typically, it is not catastrophic if satellites have infrequent, temporary failures. In fact, it is usually preferable to have temporary failures than to accommodate the high degree of redundancy necessary to achieve fault masking.

2.5.1 Standby Sparing One form of active hardware redundancy is the standby sparing technique shown in Fig.(2.12). In standby sparing, one module is operational and one or more modules serve as standby(s), or spare(s). Various error detection schemes are used to determine when a module has become faulty, and fault location is used to determine exactly which module, if any, is faulty. If a fault is detected and located, the faulty module is removed from operation and replaced with a spare. The reconfiguration operation in standby sparing can be viewed conceptually as a switch whose output is selected from one, and only one, of the modules providing inputs to a switch. The switch

examines error reports from the error detection circuitry associated with each module to decide which module's output to use. When all modules are providing error-free results, the selection can be made using a fixed priority. Any module that provides erroneous results is eliminated from consideration[17].

Using standby sparing, a system can be brought back to full operation capability after the occurrence of a fault, however, it requires that a momentary disruption in performance occur while the reconfiguration is performed. If the disruption in processing must be minimized, a hot standby sparing can be used. In the hot standby sparing technique, the spares operate in synchrony with the on line modules and are prepared to take over at any time. On the other hand, the cold standby sparing in which the spares are unpowered until needed to replace a faulty module. The disadvantage of cold standby sparing approach is the time required to apply power to a module and perform initialization prior to bringing the module into active service. The advantage of cold standby sparing is that spares do not consume power until needed to replace a faulty module. In satellites, where power consumption is extremely critical, cold standby sparing may be desirable, or required. An important aspect of the standby sparing approach is the error detection scheme used to identify the faulty module.

2.5.2 Watchdogs The concept of a watchdog is that, the lack of an action is indicative of a fault. A watchdog can be used to detect faults in both the hardware and the software of the system. The watchdog provides good fault detection capability for certain types of faults such as when processor ceases its function or when a processor becomes overloaded and requires unusual amounts of time to perform its function. Generally, there are two principal types of watchdogs [19]:

a) A master watchdog addresses the system (the processor) at appropriate intervals and expects a particular response. This type simplifies the implementation, however, it does not guarantee the operation of the whole firmware; only a part of the system (usually the processor ) is checked. b) A slave watchdog is addressed periodically by the system (the processor). If the interval between accesses is too long, the watchdog takes action (typically be a non-maskable interrupt or a reset ). The addressing may be a side effect as a result of accessing some vital hardware. This technique has the advantage that watchdog service must be designed into the main firmware which is monitoring.

2.6 SUMMARY AND SYSTEM SPECIFICATIONS To minimize the weight, size, and cost; and to maximize the efficiency and flexibility of the power system, it is decided that the centralized regulation concept utilizing a nondissipative regulated bus is the appropriate choice for this project. Also, for the solar array, the series-switching parallel-array configuration is selected for its low stress on the solar array during shadowing, low wiring complexity, and simple switch drive electronics. Thus, system modeling based on the process of solar array sections switching can be achieved easily using the individual-cell modeling approach.

A microprocessor system based on 8-bit (8085A) MPU is used to control the ON/OFF switching of solar array sections for coarse regulation of the bus voltage. A small PWM shunt which is designed to perform fine regulation, is proposed to regulate the bus voltage within the capability of one section of the solar array. The PWM shunt employs a power MOSFET as the main switching device due to its many advantages compared with bipolar power transistor. In addition to the switching control of the solar array sections, the microprocessor is also used to generate the PWM signals required to control the PWM shunt. These functions can be extended to consider the control of the charge and discharge regulators, battery management, and to continuously monitoring the status of the overall power system. This reflects the importance of using the microprocessor system to control the proposed regulator system. In addition to the functions stated above, the use of the microprocessor improves the system reliability, flexibility, and reduces size and weight.

The proposed prototype system is designed to meet the following specifications:

- Number of solar cell array sections = 5. - Output voltage = 30 V. - Maximum ripple voltage = 0.5 V. - Maximum output power = 30 W. - Maximum shunt current = 300 mA. - Modulation frequency = 9.6 kHz.

Chapter 3: MICROPROCESSOR-BASED SYSTEM CONTROLLER

3.1 INTRODUCTION The essential hardware and software considerations of the proposed MPU-based system controller are presented in this chapter. Before the system be designed or implemented, it had been put in forward to make the design as simple and flexible as possible. However, some parts would look to be overdesigned. In fact, that is to allow future developments to be done easily. As an example, incorporating charge/discharge regulators controlled by the same originally used processor can be done without much effort.

The controller hardware includes the solar array switching unit, PWM modulator, fault tolerance and the MPU hardware. The controller software includes a main program and a number of carefully designed subroutines to achieve the desired system performance. Finally, the performance considerations of the system controller is also presented in this chapter.

3.2 HARDWARE DESIGN The controller hardware is essentially based on the 8085 MPU and simple associated electronic circuits, as shown in Fig.(3.1). The entire hardware design of the controller can be divided into four main parts; the microprocessor system, solar array switching unit (SASU), PWM modulator, and the fault tolerance. The detailed circuit diagram of the controller system is documented in the Appendix (A).

3.2.1 Microprocessor System In this section, the hardware of the 8085 microprocessor system is presented. This includes the microprocessor with its standard bus architecture and peripheral components. The components involved in the assembled system together with its communication and control lines are shown in Fig.(3.2).

a) The 8085 MPU and Its Bus Architecture: The 8085 MPU is an 8-bit general purpose MPU capable of addressing 64 kByte of memory. The device has forty pins, requires +5 V single power supply, and can operate with a 3-MHz single phase clock (maximum). To increase the driving capacity of the high-order address bus, the 74244 octal bus driver is used as illustrated in Fig.(3.2). The low-order address bus is multiplexed by using the ALE (Address Latch Enable) and the 74373 latch. The driving capacity of the data bus is also increased using the 74245 as an 8-bit bidirectional bus driver. The direction of the data flow in the 74245 is determined by the direction control line (DIR) which was connected to the 𝑅𝐷 signal from the MPU. The 8085 generates three control signals: IO/ 𝑀 (I/O or memory), 𝑅𝐷 (read), and 𝑊𝑅 (write). The IO/ M signal differentiates between I/O and memory functions. Hence, appropriate control signals can be generated by combining IO/ 𝑀 with 𝑅𝐷 and 𝑊𝑅 signals [20].

b) Memory Design: The assembled microprocessor system includes two types of memory devices: 4 kByte of EPROM, and 8 kByte of RAM. By combining address lines with decoding lines of the Chip Selector (3-to-8 Decoder) illustrated in Fig.(3.2), the memory map of the EPROM ranges from 0000H to 0FFFH as shown below:

A15 A14 A13

A12

A11 . . . . .

0

0

0

X

0

0

0000H

0

0

0

X

1

1

0FFFH

Decoder Input

. A0

Lines to Decode EPROM

Address

While the RAM memory map ranges from 4000H to 5FFFH as shown below:

A15

A14 A13

A12 .

0

1

0

0

0

4000H

0

1

0

1

1

5FFFH

Decoder

.

.

. .

. A0

Address

Lines to Decode

Input

RAM

c) The 8255A PPI: The 8255A PPI (Programmable Peripheral Interface) has 24 I/O pins that can be grouped as three ports: A, B, and C. The port C can be used as individual bits or be grouped in two 4-bit ports: C upper (Cu) and C lower (Cl)as shown in the Appendix (B). The 𝐶𝑆 signal is the master chip select, and A0 and A1 specify one of the I/O ports or the control register, as given below: 𝑪𝑺

A1

A0

0

0

0

Port A

0

0

1

Port B

0

1

0

Port C

0

1

1

Control Register

1

X

X

8255A is not selected

Selection

The contents of the control register, called the control word, specify the I/O function for each port. Functions of the 8255A PPI can be classified into two modes: the Bit Set/Reset (BSR) mode and the I/O mode. The BSR mode is used to set or reset bits in port C. The I/O mode is further divided into three modes: Mode 0, Mode 1, and Mode 2. In Mode 0, all ports functions as simple I/O ports. Mode 1 is a handshake mode whereby ports A and/or B use bits from port C as handshake signals. In this mode, two types of I/O data transfer can be implemented: status check and interrupt. In Mode 2, port A can be setup for bi-directional data transfer using handshake signals from port C, and port B can be used either in Mode 0 or Mode 1. Thus, port C performs functions similar to that of the status register in addition to providing handshake signals [20]. In the present system, the

8255A PPI is used for reading the bus voltage and for communications required for fault tolerance. The I/O configuration used for the PPI ports are summarized as follows:

I/O Port

Active Controller

Standby Controller

Port A

Output Port

Input Port

(Mode 1)

(Mode 1)

Input Port

Input Port

(Mode 0)

(Mode 0)

Port C

Output Port

Output Port

(bits other than that used to

(Mode 0)

(Mode 0)

Port B

provide Mode 1 handshake signals)

d) The RS427 ADC: The RS427 ADC (Analog-to-Digital Converter) is an 8-bit, successive approximation, MPU compatible, fast conversion ADC. Its conversion time is 10 msec. Operation is from +5 V and -3 V to -30 V dc. Commonly the End of Conversion signal is connected to the Output Enable. The input analogue voltage must not exceed the reference voltage [21]. The ADC is used to convert the bus voltage into a digital form so that it can be read by the microprocessor controller. Interfacing the RS427 ADC to the MPU via the 8255A is illustrated in the Appendix (A). Port B of the PPI is configured as an input port operating in mode 0 to read the output of the ADC. The signal needed for chip-selection is taken from the 74138 Chip Selector/Decoder. The CLK input of the ADC (0.612 MHz) is obtained from a timing circuit (Fig. 3.3). While the Start Conversion pulse (STC) is obtained from a monostable that gives a short pulse at the beginning of every period of the 9.6 kHz signal.

e)

The

8251A

USART:

The

8251A

USART

(Universal

Synchronous/Asynchronous

Receiver/Transmitter) is not an essential part of the system hardware. It is only used during the development phase of the project for down-loading the developed programs from a personal computer (IBM-XT PC) into the microprocessor system. In the operation phase, all the required software is stored in the system EPROM.

The 8251A USART is a programmable chip designed for synchronous and asynchronous serial data communication. The 8251A pin configuration, block diagrams, and description is shown in the Appendix (B). It includes five parts: Read/Write Control Logic, Transmitter, Receiver, Data Bus

Buffer, and Modem Control. The control logic interfaces the 8251A with the MPU, determines the functions of the chip according to a control word in its register, and monitors the data flow. A parallel word received from the MPU is converted into serial bits and transmitted over the TxD (Transmitter Data) line via the transmitter section. On the other hand, the receiver section receives serial bits from a peripheral, converts them into a parallel word, then transfers the word to the MPU. Modem control is used to establish data communication through modems of telephone lines. A summary of the 8251A interfacing and control signals is shown below[20]: 𝑪𝑺

C/𝑫 RD

WR

Function

0

1

1

0

MPU writes instructions in the control register

0

1

0

1

MPU reads status from the status register.

0

0

1

0

MPU outputs data to the data buffer.

0

0

0

1

MPU accepts data from the data buffer.

1

X

X

X

The 8251A is not selected.

The transmitter has two registers; a buffer register to hold eight bits and an output register to convert eight bits into a stream of serial bits. TxC (Transmitter Clock) is an input signal that controls the rate at which bits are transmitted by the 8251A. The clock frequency can be 1,16, and 64 times the baud. The receiver has also two registers; the receiver input register and the buffer register. RxC is a clock signal that controls the rate at which bits are received by the 8251A. In the asynchronous mode, which is the system operation mode, the clock can also be set to 1,16, or 64 times the baud.

As illustrated in the Appendix (A), three RS-232 signals (TxD, RxD, and Ground) being used for serial communication between the PC and the 8085 system through the 8251A USART. The PC transmits data on pin 3 and receives on pin 2; while the 8085 MPU transmits on pin 2 and receives on pin 3 using the 8251A. Data transmitted over the TxD line (pin 19 of the 8251A), are at TTL logic level. So, they are converted by the line driver (MC1488) to RS-232 voltage levels and negative logic. Data received by the 8251A on the RxD line should be at the TTL logic level. Therefore, the line receiver (MC1489) is used to convert the received signals (from the PC) at pin 3 of the connector to the positive TTL logic level. The 8251A operates on the asynchronous mode with 9600 baud. The clock signal ( 9.6 kHz ), which equals to the baud, is obtained from a timing circuit.

3.2.2 PWM Modulator The PWM modulator design is essentially based on the system microprocessor and a simple associated digital circuit as shown in Fig.(3.3). The modulator generates PWM waveform using a fixed carrier frequency of 9.6 kHz. During each modulation period, the MPU reads the bus voltage via an ADC. Consequently, the MPU outputs a certain delay value to the PWM unit which consists of an 8-bit latch, 8-bit counter, and a D-type flip flop. The delay values are stored in the system ROM as a look-up table with addresses indexed to the binary equivalent value of the bus voltage. The delay value is then loaded into the counter which starts counting at the beginning of the modulation period, in other words, at the positive-going edge of the 9.6 kHz clock signal. A monostable multivibrator is used to produce an active low pulse required to load the 8-bit counter at the positive-going edge of the carrier signal. The pulse width (Tmon) produced by the monostable is approximately given by:

Tmon = R .C . ln(2)

(3.1)

Hence, to set Tmon=1/(4.915 MHz) = 0.2 µsec, the values for the capacitor and resistor are chosen to be; C = 68 pF and R = 4.3 kΩ.

Simultaneously, the D-type flip-flop is set by the positive-going edge of the modulating signal. The counter is clocked down by the MPU output clock (2.4575 MHz). The D-type flip-flop remains at its high state until the counter resets, generating a min. pulse to reset the flip-flop. Thus, the pulse width is obtained by setting the D-flip flop into the high state at the start of each modulation period. Then, after a period of time (depending on the content of the counter), the D-flip flop resets into its low state [22].

The modulating signal is obtained from a simple timing circuit which is basically two 4-bit synchronous counters. This circuit is used to generate various timing signals synchronized with the MPU system clock, as illustrated in the Appendix (A). A 614 kHz signal is obtained on QB output pin of counter-1. This signal is used as a clock signal to the ADC. While, a 9.6 kHz signal is obtained on QD output pin of counter-2. This signal is used to set the baud of transmission of the 8251A USART to 9600 and to synchronize the operation of the SASU. The 9.6 kHz signal is also used as a modulating signal.

3.2.3 Solar Array Switching Unit The solar array is divided into 5 sections, one section of which is connected to the bus permanently, it is called the active array section. All other sections are connected through the switches of the SASU, as illustrated in Fig.(3.1). Switching of solar array sections is done by writing an appropriate control word to the 74373 latch through the data bus, as illustrated in the circuit diagram in the Appendix (A). The output lines of the latch are connected to the switching circuits of the solar sections. The switching of array sections is synchronized with a slow clock signal (9.6 kHz). Such synchronization process is very important to allow enough time for the power system to fully respond to fast MPU actions.

3.2.4 Fault Tolerance Hardware To improve the reliability of the proposed shunt regulator system, the previously described hardware of the MPU-based controller is duplicated. Hence, two controllers; Active and Standby are considered. Initially, the active controller acts as the master controller and the standby controller serves as a slave watchdog (i.e. should receive a certain signal from the active controller at regular intervals). The communication between the two controllers is achieved via port A of the 8255A chip incorporated in each controller, as shown in Fig.(3.4). The two controllers communicate with each other using handshake signals provided by the 8255A programmed in mode 1. Port A is used as an output port in the Active controller. While, in the Standby controller, it is used as an input port.

When the standby controller detects an error in the operation of the active regulator (active regulator becomes faulty), it takes action to isolate this regulator and brings control to the standby regulator. Now, the standby controller leaves its watchdog job and begins controlling the bus voltage. The standby controller performs this transition of state by setting PC0 pin of the 8255A using the BSR mode. The PC0 pin in the 8255A of the standby controller is connected to HOLD input of the active MPU controller. When the HOLD pin is activated by setting PC 0 to logic 1, the MPU stops its operations and relinquishes control of its buses.

The PC0 pin is also connected to the enable pin (active low) of the active buffer while, the enable pin (active low) of the standby buffer is connected to PC0 through an inverter. So that the standby buffer is only enabled when PC0 is set to logic 1. In the initial operation, i.e. when the standby controller works as a slave watchdog and no fault is detected, PC0 is always be reset to logic 0, so that the Active buffer still be enabled. Active and standby buffers are used to control the switching

sequence of the solar array sections, PWM output, and the ADC start conversion signals for both the active and standby controllers, as illustrated in the detailed circuit diagram of Appendix (A).

3.3 SOFTWARE DESIGN In this section, the software algorithms required to achieve the desired system performance is presented. The entire software developed in this work can be categorized into three main parts; the downloading program, voltage regulation program, and the fault tolerance program.

3.3.1 Microprocessor System Software The downloading program (DNLOAD) is used to download the object codes of the developed programs from a personal computer (PC) to the 8085 MPU-based controller system. The commonly used format for the Intel family of microprocessors is known as the Intel Hex Format. Using this format, a program or a file is divided into records, and each record has six segments in ASCII characters; the header, record length, load memory address, data, and the check sum. These segments are described below [20].

- Header: The colon is the first byte used to indicate the beginning of the record. - Record Length: The number of data bytes in the record; it can be from 00 to 10H. - Starting Address: This is the memory address where the data in that record are to be stored. If there were additional records, the starting memory address of each record would be automatically calculated. - Record Type: This includes two types of records: 00 means normal data and 01 means end of file record. - Data: These are the Hex bytes of the mnemonics in the program. - Checksum: This is the 2's complement of the sum of all the bytes in the record, excluding the header.

The tasks of the downloading program (DNLOAD) can be summarized as follows [20]: 

Initialize the 8251 USART to receive a file.



Check for the header character.



Read two ASCII characters at a time.



Convert the ASCII characters into binary values, and combine them in a byte.



Extract the information concerning the byte count and the memory address. Add the Hex values in the checksum counter.



Check for the record type. If it is the end of file, display the successful transfer.



If the record type is data, store the bytes in memory, update the memory pointer and the byte counter, and add the Hex values in the checksum counter.



After reading all the data bytes, add the checksum to the value of the checksum received (the last two ASCII characters in the record). If the result is zero, display end of data transfer, if it is other than zero, display error message.

Fig.(3.5) shows a simplified flowchart that summarizes the above steps. The program is divided into five subroutines, which are described briefly as follows:

i) RDASKY- This subroutine enables the 8251 receiver, checks the status, and reads an ASCII character, as shown in Fig.(3.6-a). To initialize the 8251 in the asynchronous mode, a certain sequence of control words must be followed. After a Reset operation (system Reset or through instruction), mode word must be written in the control register followed by a command word. Any control word written into the control register immediately after the mode word is interpreted as a command word. In addition, the MPU must check the readiness of a peripheral by reading the status register. The mode word specifies the general characteristics of operation (such as baud, parity, number of stop bits), the command word enables data transmission and/or reception, and the status word provides the information concerning register status and transmission errors. The definitions of these words are shown in the Appendix (B). The used mode and command words are CDH and 26H, respectively.

ii) HEXBYTE- This subroutine reads two ASCII characters by calling RDASKY, converts the characters into binary by calling ASCBIN, and combines the binary values to form a byte, as shown in Fig.(3.6-b). The binary value of the first ASCII character is saved as high-order four bits and of the second character as low-order four bits.

iii) ASCBIN- This subroutine converts an ASCII character into binary value and adds the checksum counter, as shown in Fig.(3.6-c).

iv) CHKSUM- This subroutine reads the last two ASCII characters by calling the routine HEXBYTE and compares the byte with the check sum counter. If the result is not zero, it calls the error message.

v) ERROR- This subroutine displays an error message.

3.3.2 Voltage Regulation Program This program can be divided into two main parts, a main program (MANPROG) and an interrupt service routine (ISROT). The execution of the voltage regulation program is synchronized with a 9.6 kHz clock signal. This is to give the power circuit enough time to respond to the controller actions. A list of this program in assembly language is documented in the Appendix (C).

a) Main Program (MANPROG): A simplified flowchart of the main program (MANPROG) is shown in Fig.(3.7). It begins with the initialization of the stack pointer and the 8255A PPI. To determine the I/O configuration of the 8255A ports, a control word is loaded to its control register of the 8255. Bit D7 of the control register specifies either the I/O function or BSR function. If bit D7 = 1, bits D6-D0 determine I/O functions in various modes, as illustrated in the Appendix (B). If bit D7 = 0, port C operates in the BSR mode. The BSR mode is concerned only with the eight bits of port C, which can be set or reset by writing an appropriate control word in the control register. This control word, when written in the control register, sets or resets one bit at a time.

In the active controller, the 8255A is configured as follows: port A is programmed as an output port operating in Mode 1, while port B is programmed as an input port operating in Mode 0 for reading the value of the bus voltage from the ADC. Hence, the appropriate control word for the 8255A control register is A2H.

Port A of the 8255A chip of the standby MPU-based controller is configured as an input port operating in Mode 1. Port B is used as an input port operating in Mode 0, as in the active controller. So that, port B can be used to read the bus voltage when the standby regulator comes into action. The remaining bits of port C (other than these used to provide handshake signals with port A) are programmed as an output port. The appropriate control word used to set these configurations is B2H.

As the microprocessor may be considered so fast compared to the power system response, the whole system operation is synchronized with the 9.6 kHz signal by applying it to the RST 7.5 interrupt pin of the 8085 MPU. Hence, to enable the RST 7.5, the used mask interrupt word is 0AH.

During the initialization part, the MPU also generates a look-up table into the system RAM. This table contains delay values which are scaled out according to the received value of the bus voltage. These delay values, which are determined experimentally, are used by the PWM generation unit to define the width of the generated PWM signals. Then, the MPU enters to the background job which is just a dummy do-nothing routine that idles the MPU until an RST 7.5 interrupt signal is received. It should be noted here that the MANPROG of the standby controller includes an additional subroutine (FOLTROT). This will be explained later in section (3.3.3).

b) Interrupt Service Routine (ISROT): The ISROT comprises of two subroutines; a PWM generation routine (PWMROT) and a solar array switching routine (SASROT) as shown in the simplified flowchart of Fig.(3.8). When the MPU detects an interrupt signal from the RST 7.5 (which occurs at a frequency of 9.6 kHz), it starts the execution of the interrupt service routine. At the beginning of this routine, the MPU reads the actual value of the bus voltage (Vbus) and compares it with a digital reference value (Vref). This reference value represents the voltage that the bus is required to be adjusted on. When comparing the voltages, very small differences are allowed for practical reasons. Thus, the two least significant bits of the bus voltage value (8 bits) are neglected to take consideration of the presence of noise in the system. So, the input voltage resolution is approximately 150 mV. If the two values are (equal), the MPU neglects the rest of the ISROT and returns to the background job.

When the two values are not equal, the bus voltage must be either greater or smaller than the reference voltage. In the case of the bus voltage is higher than the reference voltage, the MPU calls a subroutine called HI. Otherwise, when the bus voltage is lower than the reference voltage, the MPU calls a subroutine called LO.

The HI subroutine regulates down the bus voltage when it goes higher than the required value. Such a case occurs when either the load current decreases or the current supplied by the solar array increases. To reduce the bus voltage, the MPU firstly checks the voltage difference (Vdiff)

between the actual bus voltage and the reference voltage. If this difference is bigger than the capability of one solar array section, the MPU calls the solar array switching control routine (SASROT) to switch one solar array section into its OFF state. This process may be repeated as necessary until the voltage difference become within the regulation capability of a single solar array section. This represents the coarse regulation of the bus voltage. now, the PWMROT is called to perform the fine regulation part of the bus voltage. Whenever the PWMROT subroutine is called, the duration (τ/T) of the PWM signal is increased by scaling the delay value provided to the PWM unit by an appropriate factor. This process is also repeated as necessary until the bus voltage satisfies the required value.

On the other hand, the LO subroutine is called to raise the bus voltage when it becomes less than the required operational value. This occurs when the load demands more current from the solar system. In this case, the coarse and fine regulation process described above is repeated but in the reverse direction. The ISROT recognizes whether the actual bus is higher or lower than the desired value depending upon the status of the carry flag of the 8085 microprocessor. Thus, when the SASROT or the PWMROT is called, it initially examines the status of the carry flag. Then, it decides the regulation direction.

3.3.3 Fault Tolerance Program The fault tolerance software in the active controller is based on calling a subroutine called ACMSEG. This routine just sends a binary word to the Standby Controller via port A of the 8255A at each modulation period (1/9.6 kHz). The transmitted binary word represents the value of the bus voltage as read by the Active Controller. In the Standby Controller, this word is used for error detection, according to a certain algorithm.

During the normal operation of the system, the regulation task of the bus voltage is achieved by the active regulator and the standby controller serves as a watchdog. In the standby controller, the fault tolerance software is performed by calling the FOLTROT subroutine, as shown in the flowchart of Fig.(3.9). At each modulation period, the watchdog (standby controller) receives a binary word that represents the value of the bus voltage from the active controller. Hence, when this message does not received from the active controller within the expected time, this is considered as an indication to a fault in the active controller (mainly in the MPU). In this case, the standby controller acts immediately to stop the faulty active regulator system and it takes over to regulate the bus voltage by activating the standby power stage.

It should be explained here that, the implemented fault detection algorithm detects errors (faults) in the operation of the whole active regulator system - not only the controller. This is achieved by further processing of the received message from the active controller. As this message represents the bus voltage, it has to be within a certain defined limits around the desired bus voltage. Thus, when a fault occurs in part(s) other than the controller, the whole system would be faulty. However, the active controller will still send a message to the standby controller at the appropriate times, but this message would represent the bus voltage (unregulated). Consequently, the standby controller can then simply identify the existence of a fault by comparing the received value with pre-defined limits. When the standby controller discovers that the bus voltage is out of range (i.e. unregulated) it waits for a certain period of time (Approximately 1 sec) to make sure that the active regulator cannot resume bus voltage to regulation again. After this period, if the bus voltage still unregulated, the standby regulator acts immediately to stop the faulty active regulator from further functioning and takes over to regulate the bus voltage.

The execution of the FOLTROT routine begins by resetting the 8255A PCo pin to its low state. Hence, the active buffer is enabled while the standby buffer is disabled. Now, the standby controller has to receive messages from the active controller once at each modulation period (1/9.6 kHz). The reception of messages is performed using the status check technique provided by Mode 1. The status word can be checked by reading port C. Hence, checking bit D5 which represents the Input Buffer Full signal of port A (IBFA), the MPU can decide whether there is a message to be received (when IBFA = 1) or not (when IBFA = 0). Simultaneously, the MPU starts comparing the time period between any two successive messages with a maximum time limit equals to 1/9.6 kHz (Approximately 104 µsec). If a message is not received within this period, a decision that active controller has become faulty is taken. Thus, the standby controller leaves the watchdog task, and enters into voltage regulation phase.

When a message is received at the appropriate time, the standby controller checks whether the value of the bus voltage (the message) is within regulation limits or not. If it is, the program control is returned back to receive another message. When the standby controller finds that the bus voltage is not regulated, the whole process explained previously is repeated again several times. This is to give the active regulator enough time to regain control on the bus again - if it is just corrupted and has not a permanent failure. The maximum period allowed for infrequent corruptions in the regulation of the bus voltage is set by loading a counter with a certain number. In the present system, the period is set to one second. If active regulator is not failed, it will regain regulation on

the bus voltage within this time. However, if the bus voltage is still unregulated, the standby controller takes decision to leave the watchdog task and to enter the voltage regulation phase.

Before entering to the voltage regulation phase, a change over process between the active and standby regulators is achieved. The standby controller stops the active regulator from further functioning by setting the 8255A PC0 pin of the standby controller into logic 1 using the BSR mode. This pin is connected to HOLD input of the 8085 MPU in the active controller, and used to enable/disable active and standby buffers as stated previously. Thus, the active MPU-based controller goes into HOLD state, and the active buffer is disabled while the standby buffer is enabled. After the standby controller leaves the FOLTROT routine, the responsibility of bus voltage regulation is taken by the standby regulator.

3.4 PERFORMANCE ASPECTS When the MPU detects a change in the bus voltage from its set value, it will take a suitable action to correct the bus voltage value and keep it regulated at the required level. If it is permitted to return at its maximum speed to check the value of the bus voltage again, the MPU may take another correction action immediately because the power system has not given a time to fully respond to the former correction - even if the initial correction is adequate to compensate for the load change. Hence, the controller would be over correct and the system could be unstable. Thus, controller action is synchronized with the system response capability using clock signal in order of few kilohertz.

The modulation frequency of the PWM signal used to drive the PWM shunt and the speed at which solar array sections can be switched represent the most important design parameters in the proposed regulator system. As the modulation frequency increases, the values required for the output filter components decreases, and consequently, the size and weight of the system can be reduced. Similarly, the amount of the output capacitance needed for energy storage during transient loads, i.e. during switching of solar array sections, is also proportional to the rate at which solar array sections can be switched ON or OFF. The output filter components will in turn influence the transient response characteristics of the shunt regulator. Transients in the response must be given time to decay sufficiently before the processor is permitted to evaluate system status.

In fact, the modulation frequency is an important parameter in both hardware and software design. Its value is also related to the time required for executing the regulation interrupt service routine, the number and nature of the processor background jobs, and the system running clock frequency. In the present system, the background job is just a waiting loop, and with a system clock frequency of 2.4575 MHz, the regulation interrupt service routine needs approximately 60 µsec to be executed. The modulation frequency in the present system is set to 9.6 kHz which is suitable for both of the power circuit switching characteristics and for the MPU-based controller design. Higher modulation frequency can be obtained either by increasing the system clock frequency or by using an external crystal oscillator.

The controller behavior in regulating the bus voltage is simulated in Figures (3.10) and (3.11). The behavior for coarse regulation is simulated in Fig.(3.10). While, the controller behavior for fine regulation is simulated in Fig.(3.11). At the beginning (Fig. 3.10-a), only one solar array section is connected to the bus (switched ON) and the bus voltage is much less than its desired value. Thus, the controller switches a second solar array section ON, as illustrated in (Fig. 3.10-b). Then, the controller checks the difference between the actual bus voltage and the desired voltage. When it finds that the voltage difference is still larger than one solar array section capability, it takes a decision to switch a third section ON, as illustrated in Fig.(3.10-c). Now, when the controller checks the value of the bus voltage, it finds that the difference voltage (Vdiff) is less than one solar array section capability. Thus, the coarse regulation is ended and the controller starts the fine regulation process. This is performed by reducing the duty cycle of the generated PWM signals until the bus voltage reaches its desired value, as illustrated in Fig.(3.11). An opposite situation can be found when the bus voltage goes higher than the required value.

In the implemented fault tolerance algorithm, when a fault is discovered, the time allowed for the active regulator to re-correct its operation before starting the standby regulator, is made programmable. Thus, it can be easily adjusted according to the type of the space system and the maximum period of time which can be allowed for infrequent temporary corruptions in the main bus voltage. Also, the fault tolerance algorithm can be easily modified to consider more number of standby controllers or standby regulators.

Chapter 4: POWER CIRCUIT DESIGN AND PERFORMANCE

4.1 INTRODUCTION Space-based power systems have severe problems related to the weight and size limitations, and to thermal constraints of vehicles design. Hence, the power stage of the proposed shunt regulator system has to be designed carefully to assure the efficiency, flexibility, and reliability of the system.

The philosophy of the regulation procedure proposed in this project reduces effectively the power losses or the heat dissipation in the system. Hence, the number and size of the required heat sinks are reduced. The need for heat sinks might be eliminated if components of ratings higher than that required for operating the system are used in the design of the power circuit. Certainly, this depends on the weight, size, cost, thermal design of the system, and the availability of the required components.

This chapter describes the design and performance of the implemented power circuit that employs the power MOSFET as the main switching device. The behavior of the implemented circuit is analyzed theoretically by a proposed mathematical model. The validity of the proposed model together with the system performance are examined experimentally.

4.2 SOLAR ARRAY SECTION SIMULATORS Because of the unavailability of the actual solar cell arrays, electronic circuit simulators are used instead. For the system under consideration, the simulator circuit does not need to exhibit I-V characteristics identical to that of a real solar cell array; it needs only to be similar. The nearest

simulation with the least complexity is achieved by using a current source circuit similar to that reported in reference [1].

The simulator circuit for one solar array section is shown in Fig.(4.1). The light-emitting diode (LED) is used to indicate visually whether the section is switched on or off. Five units of such simulator have been constructed. The I-V characteristics of the implemented solar cell array section simulators are shown in Fig.(4.2). The approximated P-V characteristic of the array simulator is also illustrated on this figure (the dashed curve). In order to achieve maximum power transfer to the load, the operating voltage is set to be 30 V, which represents approximately 70% of the open circuit voltage. Each simulator is capable of supplying a current of approximately 250 mA at the suggested operating voltage (30 V). Also, it can be seen that the power of the solar array simulator falls below 75% of its maximum value when the voltage becomes less than 20 V or higher than 35 V.

4.3 POWER CIRCUIT ELEMENTS In this section, the design details of the power circuit are described. This includes a MOSFET shunt regulator, and an output filter. The designed power circuit is shown in Fig.(4.3). This circuit is duplicated to improve the reliability of the proposed regulator.

4.3.1 MOSFET Shunt Regulator In the present system, the PWM shunt is based upon using the IRFK2D350 power MOSFET. As illustrated in Fig.(4.3), the resistor Rsh is connected in the shunt path for limiting the current passing through the shunt. The MOSFET shunt regulator (or the PWM shunt) is designed to regulate one solar array section simulator only. Each simulator is capable of supplying 250 mA at a bus voltage of 30 V, as illustrated by the I-V characteristics of Fig.(4.2). Thus, a resistor (Rsh = 100 Ω) is used so that the maximum shunt current is limited to 300 mA at the operating voltage (30 V). The PWM signal is applied to the gate of the power MOSFET via the gate drive circuit so that the power MOSFET is switched ON and OFF according to the width of the PWM control signals.

a) Protection of the Power MOSFET: One of the most important considerations in the design of power electronics equipment is the evolution of economic methods by which reliable operation can be achieved. A contribution to this

can be made by satisfactory protection of the power stages under fault conditions [23]. The thermal and electrical stress that the device undergoes during switching can be quite severe, particularly during turn off with an inductive load at the drain terminal [12]. In order that the power MOSFET not to fail under various operating conditions, it must be protected from unexpected gate-to-source voltage spikes, and drain-to-source voltage spikes induced during switching [24].

(i) Gate-to-Source Spikes: If the impedance of the gate drive circuit is assumed to be high then any positive-going change of voltage applied across the drain-to-source terminals will be reflected as a positive going voltage transient across the gate-to-source terminals in the approximate ratio; 1 / (1 + CGS / CDS) which is typically of about 0.1 to 0.6 [24]. The positive-going gate-to-source voltage transient is undesirable because it may exceed the gate voltage rating of the device, causing a permanent damage. Also, it might turn the device ON unintentionally. This problem can be solved simply by providing the gate-to-source terminals with a voltage clamp (such as a zener diode) to prevent the gate-to-source voltage rating from being exceeded. Another fundamental solution is to make the gate driver circuit of a low impedance such that the voltage transient at the gate is contained to a level at which spurious turn on does not occur.

(ii) Drain-to-Source Voltage Spikes: As a result of the stray inductance in the circuit, a voltage spike is produced when the device is switched off. The faster the power MOSFET is switched, the higher the over voltage will be. One approach to solve this problem is to minimize the stray circuit inductance by means of careful attention to the circuit layout. To protect the power MOSFET from such kind of voltage spikes, a clamping device (a zener diode) may be connected between drain and source to clamp the voltage spike level. Also, a simple RC snubber can be used to limit the peak voltage.

In the present system, a combination of zener diodes and an RC snubber circuit is used for protecting the power MOSFET. A conventional zener diode (type BZY C12) is connected between the gate and the source terminals for protection against gate-to-source spikes. The protection from drain-to-source spikes is achieved by using a zener diode (type 1N5386B) and an RC snubber circuit that are connected between the drain and source terminals, as illustrated in Fig.(4.3). The design values for the snubber circuit are given by [25]:

Rs = Lst . S / Vmax

(4.1)

Cs = 4 . ξ2 . Vmax / Rs . S

(4.2)

and

where, Rs is the snubber resistance, Cs is the snubber capacitance, Lst is the circuit stray inductance, Vmax is the maximum switching voltage (which equals to the solar array open-circuit voltage = 42 V), S is the maximum rate of change of voltage (dv/dt), and ξ is the damping factor (0.5 - 1). Thus, for S = 42 V/µsec, ξ = 0.75, and if it is assumed that Lst = 20 µH, then: Rs = 20 Ω and Cs = 0.1 µF, approximately. According to the above design criteria, the power MOSFET needs approximately one second to be switched on or off completely. Hence, adding the rising and falling times, the minimum pulse width sufficient to switch on the power MOSFET is 2 µsec. The power rating of the snubber resistance is calculated as follows: Ps = Cs Vmax2 f

(4.3)

= 1.7 W.

b) Gate Drive of the Power MOSFET: The power MOSFET is a voltage controlled device, that is a voltage of special limits must be applied between gate and source to produce a current flow in the drain. Only a small leakage current flows from the applied voltage in to the gate because the gate terminal is electrically isolated from the source by a silicon oxide layer. The rate of change of the drain-to-source voltage (VDS) and the drain current (ID) depends on the gate current, which determines how fast the device capacitances are charged and discharged. The advantage of fast switching speed is the reduction in switching power loss. However, fast switching has disadvantages, including higher electromagnetic interference (EMI) and over voltages due to stray inductances. In general, it is preferable to switch

at slower speeds as far as these speeds are sufficient for the required application, and unless the switching losses become significant [27].

In order to turn the device on, a gate-to-source voltage pulse is needed to deliver sufficient current to charge the input capacitor in the desired time. The input capacitance (CISS) of the power MOSFET is the sum of the capacitors formed by the metal-oxide gate structure, from gate to drain (CGD), and gate to source (CGS). Hence, to achieve high switching speeds, it is necessary that the impedance (RG) of the driving voltage source be very low. An approximate values for the driving impedance (RG) and the required driving current (IG) can be estimated using the following equations [24]:

RG = tr (or tf) / (2.2 CISS)

(4.4)

IG = CISS . dv/dt

(4.5)

and,

where; CISS = MOSFET input capacitance (pF), dv/dt = generator voltage rate of change (V / n sec), tr = rise time (n sec), and tf = fall time (n sec). To turn the power MOSFET off, the gate-to-source voltage has to be removed. In this case, the power MOSFET presents a very high impedance between drain and source, thus inhibiting any current flow except leakage currents ( in µA ).

The PWM signal is applied to power MOSFET gate drive stage via an opto-isolater, as shown in Fig.(4.4). The output side of the opto-isolater is powered from an isolated power supply (IPS). The output signal of the opto-isolater is applied to the driving transistor Tr1 type 2N2222A. The transistor Tr1 drives Tr2 and Tr3 that are connected as a totem-pole. Connecting Tr2 (type 2N2222A) and Tr3 (type 2N2907A) in the totem-pole configuration gives a low impedance gate drive signal. This is very important for fast switching operations and to protect the power MOSFET from unexpected gate-to-source voltage spikes. The output of the totem-pole is either 10 V or 0 V which are sufficient to turn the device fully on or off respectively.

4.3.2 Output Filter The filter stage forms a very important part of the PWM shunt regulator. To a large extent, it determines the efficiency, transient response, noise and ripple voltages of the regulator. The selection of a suitable output filter for the shunt regulator is based on the load requirements, as well as the performance characteristics of the filter circuit. The use of LC-filter in a PWM shunt regulator provides the following advantages [10]:

(i) Minimal power loss in the filter. (ii) The magnitude of peak current in the transistor switch is also low. (iii) The size of L to be used can be moderate even for light loads.

In addition, by going over to a high switching frequency, the values of inductance and capacitance to be used in the filter are made relatively low. This reduces the weight and volume of the filter. At the DSR output, a capacitor is needed for energy storage during transit loads. Its value is inversely proportional to the rate at which solar array sections can be added (or removed) to the bus [1]. When there is a step change in the load current, the PWM shunt responds by reducing its shunt current until a minimum value is reached. Now, no more current is available from the solar array and the capacitor must supply the balance of the load current until the microprocessor switches another array section into the bus. The longer the processor takes to do this, the larger the capacitor must be to keep the bus voltage within the required specifications. A similar situation exists when there is a step reduction in load current. In this case, the capacitor must absorbs the excess current until the processor removes a section from the bus.

The values of Lf and Cf required for the filter circuit used in the present PWM shunt regulator (as illustrated in Fig. 4.3) are calculated from the considerations of regulation and ripple voltage as recommended in the references [10,26]; hence:

𝑉𝐿 = 𝐿𝑓

𝑑𝐼 𝐿 𝑑𝑡

where, VL is the voltage across the inductor Lf, and IL is the current passing through Lf ( = load current).

(4.6)

The value of Lf is fixed such that the load current (IL) is reasonably constant during the entire MOSFET switching period (T=1/f), i.e.

𝑉𝑖𝑛 − 𝑉𝑏𝑢𝑠

𝑚𝑎𝑥

= 𝐿𝑓

∆𝐼𝐿 𝑇

(4.7)

where, Vin is the input voltage to the PWM shunt, Vbus is the bus voltage, and ΔIL