Microwave Class-E GaN Power Amplifiers S. Gao1, H. Xu2, S. Heikman2, U. Mishra2 and R.A. York2 1 Active Antenna Group, School of Computing, Engineering and Information Sciences, University of Northumbria, Newcastle Upon Tyne, NE1 8ST, UK Email:
[email protected] 2 Dept. of Electrical and Compute Engineering, University of California, Santa Barbara, CA 93106, USA
Abstract— Two MMIC class-E power amplifiers (PA) in GaN HEMT technology are reported. The single stage class-E MMIC PA operates at 1.9 GHz. At 30V drain bias, a poweradded-efficiency (PAE) of 57% and a maximum output power of over 37 dBm are achieved. At 40V drain bias, an output power of 38.7 dBm is achieved at 50% PAE corresponding to a power density of 7.4 W/mm. The dual-stage class-E MMIC PA operating at 2.0 GHz is also reported. It achieves an output power of 37.5 dBm, a PAE of 50%, and a gain of 18.2 dB. I. INTRODUCTION As the most expensive component in the system, RF/microwave PA is the key part in wireless communication, radar, and sensor systems. High efficiency in PAs is useful for reducing the DC power consumption, relaxing the cooling requirements, lengthening the operating lifetime, reducing the size, and lowering the cost. Extensive research work on high-efficiency RF/microwave PAs has been done worldwide, and different types of high-efficiency PAs have been proposed, including class D, class E, class F, class F-1, class S, etc [1]. Amongst these high-efficiency PAs, the class-E amplifier is attractive due to its simple topology. Also, in the class-E PA, the closed-form expressions of the values of output network components are available, which makes the class-E amplifier designs more convenient compared to other amplifier designs [2]. In recent years several class-E MMIC PAs using GaAs MESFET, InP DHBT, LDMOS and CMOS technologies have been reported [3-6]. This paper presents the first class-E MMIC PA using GaN HEMT technology. Wide bandgap devices, such as AlGaN/GaN HEMTs, have superior power-density compared with other technologies due to an inherently larger breakdown field [7]. Field-plated gate structure can further increase the breakdown voltage [8]. The MMIC amplifiers presented here are fabricated by using a modest 0.7µm AlGaN/GaN process, with a fieldplated gate structure. II. PRINCIPLES OF CLASS-E PA An ideal class-E amplifier configuration is shown in Fig. 1. It consists of a DC supply voltage Vd, an RF choke inductor Ldc, a switch with a parallel capacitor Cp, a resonant circuit L0-C0, and a load R0. The switch is turned on and off periodically at the driving frequency, and hence must have a high impedance in the “off” state and a low impedance in the “on” state. High efficiency is achieved by tailoring the drain voltage and current waveforms to minimize losses at the switching instants. The switches usually use GaAs FETs or other
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transistors. To achieve high efficiency, the conditions include: 1). Voltage returns to zero at switch turnon, and 2). Zero voltage slope at switch turnon [9].
Vd
R0
Fig. 1. Ideal class-E amplifier configuration III. DESIGN of SINGLE-STAGE PA The circuit design in this work is based on the theory described in [9] for an idealized class-E amplifier with a 50% duty cycle and zero voltage and zero derivative at the switching instant. To achieve class-E operation, the load impedance necessary at the output of the transistor switch is given by
Z net =
0.0446 j 49.050 e Cs f
At higher-order harmonic frequencies, the impedance of the output network should be as large as possible, so that the output current at the load could be sinusoidal. Vd Vg W=1 mm
Lg1 3.8 nH
In
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Lg2 4 nH Cg2 0.4 pF
L1 5.6 nH
BIAS TEE
Rs1 125 Ω Rs2 Cs1 500 Ω 5 pF
Cp 0.37 pF
Out
C1 1.6 pF
Fig. 1 Circuit schematic of the class-E PA Because of the narrow range of component values that can be realized in our MMIC process, the usual series LC network at the output is replaced by an L-match network as shown in Fig. 1 (L1, C1). The output L-network transforms a 50 Ω load to the desired optimum load and also provides some harmonic suppression [9]. The drain capacitance Cds of the transistor, together with external capacitance
APMC2005 Proceedings
100 V and Idss=1 A/mm. The measured unity current gain cutoff frequency (ft) of the device is 18 GHz.
Cp, functions as the output capacitance for class-E operation. A second order harmonic trap (Lg2, Cg2) at the gate is employed to improve the input waveforms, so that the transistor can be switched on and off efficiently, as required in class-E mode operation. As the device is potentially unstable, a stability circuit (Rs1, Cs1 and Rs2) is also added at the input. The circuit was simulated using the Agilent Advanced Design System (ADS). A bias-dependent and scalable large-signal EEHEMT1 model was used to simulate output power and efficiency. Passive lumped components and parasitics were simulated using the ADS momentum EM simulator. Fig. 2 shows the simulated waveforms of drain voltage and current, as well as the voltage waveforms at the load. The load voltage waveform is close to sinusoidal indicating good suppression of harmonic components. However, the simulated drain voltage and current waveforms are clearly not the ideal class-E drain voltage/current waveforms. This is partly due to the inherent non-idealities of the device as a switch, but also a consequence of the non-optimal output network that was used because of passive component realization constraints. The low Q-factors of the spiral inductors and loss from the stability circuit also contribute to a degradation in efficiency. These issues are common to MMIC amplifiers and explain why most MMIC class-E amplifiers suffer lower efficiency than hybrid implementations. IDrain
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Fig. 2 Simulated voltage and current wave form of the GaN Class-E PA
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IV. CIRCUIT FABRICATION AND TEST The single-stage class-E power amplifier was fabricated on a SiC substrate. The AlGaN/GaN epitaxial layers were grown by metal organic chemical vapor deposition (MOCVD). The detailed epitaxial structure consisted of a semi-insulating Fedoped GaN base layer, followed by a 290 Å thick Al0.27Ga0.73N barrier layer. The room temperature sheet electron concentration and Hall mobility were ~1.12x1013 cm-2 and ~1430 cm2/Vs, respectively. The device featured a field-plated gate structure, with a 0.7 µm gate length, 8x125 µm gate width and 0.7 µm field-plate length. The field-plated GaN HEMT device has a breakdown voltage greater than
Fig. 3 is a photo of the completed circuit, which occupies an area of 2.4 mm by 2.2 mm, clearly dominated by the spiral inductor areas. There are no vias in our process, so all ground connections are made on the top side with CPW I/O ports. The complete MMIC process begins with a standard HEMT process with the SiN passivation, followed by device isolation and finally the passive lumped components. Lumped component fabrication included NiCr thin film resistors, metal-insulatormetal (MIM) SiN capacitors and spiral inductors with PMGI cross-overs. All input and output matching and turning networks are on chip. Bias feeds for gate and drain are provided through off-wafer bias tees for convenience in testing. The sample was vacuumheld on a 2-inch copper wafer chuck during testing. There was no additional thermal management. Fig. 4(a) shows the measured results of output power and PAE performances. The drain voltage bias is at 30V in this case. A maximum power level of 37.2 dBm is achieved at 1.9 GHz, corresponding to 5.25 W/mm in output power density. In the 500 MHz bandwidth from 1.8 GHz to 2.3 GHz, the PAE is above 52% for an input power of 27 dBm. The highest PAEs are measured as 57% at 1.9 GHz and 2.2 GHz respectively.
Pout (dBm)
1.0
100
-20
Fig. 3. Photo of the amplifier (2.4 mm x 2.2 mm)
power amplifier versus input power levels at 1.9 GHz with 30 V drain bias.
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The measured results of output power and PAE performances versus frequency at a drain voltage bias of 40 V are shown in Fig. 4(b). In this case the power amplifier delivers a maximum output power level of 38.7 dBm at 1.9 GHz, and the power density increases to 7.4 W/mm. A peak PAE of 55% is measured at 2.2 GHz, and the PAE is above 50% within the frequency range from 1.9 GHz to 2.4 GHz for an input power of 28 dBm. Simulated results are also presented as dotted lines in Fig 4 for comparison. A relatively good agreement between simulated and measured output power results is observed. The discrepancy between simulated and measured PAE results may be due to an inaccuracy of the nonlinear device model, EM simulation, process variation and device selfheating. The measured results of output power, gain, and PAE performances of the amplifier at different input power levels at 1.9 GHz and 30 V drain bias are shown in Fig. 5. The power-added efficiency of the transistor reaches 57% with a 10 dB gain. The corresponding drain efficiency is 63%.
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Pin (dBm) Fig. 5 Measured output power, gain and PAE of the
V. DUAL-STAGE CLASS-E AMPLIFIER Using GaN HEMT technology and the same process, a dual-stage class-E power amplifier at 2.0 GHz is also designed and tested. The dual-stage power amplifier consists of a class-F driver stage and a class-E power stage. A class-F amplifier is used as a driver stage, so that a rectangular voltage waveform can be formed at the output of the class-F amplifier, i.e., the input of the class-E power stage [3]. The dual-stage MMIC class-E amplifier is fabricated on a SiC substrate in GaN HEMT technology. Two field-plated AlGaN/GaN HEMT devices, one having 0.7 µm gate length and 2x125 µm gate width, and the other one having 0.7 µm gate length and 8x125 µm gate width, are used for the driver stage and the power stage, respectively. Fig. 6 shows a photo of the amplifier, which has a size of 3.4 mm x 2.2 mm. The input network of the driver stage, the inter-stage network, and output network of the power stage are all on chip. Both the input and the output ports are designed for the standard 50 Ω environments. Off-chip bias tees are used to provide DC bias, for the convenience of testing. The input harmonic tuning is used at both the input and output of the class-E power stage, for achieving better power/efficiency performances.
Fig. 6. Photo of the dual-stage amplifier (3.4 mm x 2.2 mm) Fig. 7 shows the measured results of output power, gain and PAE versus input power. The measurement is performed at 2 GHz with a 35 V drain voltage bias. At an input power level of 19.3 dBm, it achieves a PAE of 50 %, with a gain of 18.2 dB. Higher gain about 20 dB is achievable at lower input power levels. An output power of 37.5 dBm is achieved, corresponding to a power density of 5.6 W/mm.
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Pin(dBm) Fig. 7. Measured output power, gain, and PAE versus input power: f0= 2 GHz, Vds=35 V VI. CONCLUSIONS We have presented two class-E MMIC power amplifiers in GaN HEMT technology, taking advantage of the high-power density of GaN devices and the high-efficiency of the class-E PA topology. The single-stage circuit achieved a maximum power-added-efficiency of 57% and an output power of 37.2 dBm at 1.9 GHz and 30 V drain bias. The power density reaches 5.25 W/mm at 30 V drain bias and 7.4 W/mm at 40 V drain bias. The dual-stage class-E MMIC power amplifier operating at 2.0 GHz is also reported. It achieves an output power of 37.5 dBm, a PAE of 50%, a gain of 18.2 dB, and a power density of 5.6 W/mm. Comparing these two GaN HEMT class-E amplifiers with other technologies [2-6], our power amplifiers exhibit state-of-the-art efficiency performance with significant improvement in output power and power-density. Further work is to combine the GaN HEMT-based class-E PA with the LInear Amplification using Nonlinear Components (LINC) technique, so that the RF/microwave power amplifier can achieve high efficiency, high linearity, and high power [10]. VII. ACKNOWLEDGEMENT S. Gao acknowledges the funding support from High-Education Funding Council of England (HEFCE, UK) under Promising Research Fellowship Scheme, and Engineering and Physical Science Research Council (EPSRC, UK) under the grant GR/S42538/01. This work was also supported in part by the Office of Naval Research under contract #N00014-011-0764. REFERENCES [1] S.C. Cripps, RF power amplifiers for wireless communication, Artech House, 1999 [2] Y. Qin, S. Gao, A. Sambell and E. Korolkiewicz, “Design of low cost broadband class-E power amplifier using low voltage
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