Millimicrosecond Transistor Current Switching Techniques

1957 WESTERN COMPUTER PROCEEDINGS

68

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Millimicrosecond Transistor Current Switching Techniques H.

s.

YOURKEt

AND

E.

J.

SLOBODZINSKlt

INTRODUCTION

HERE ARE five major limitations on the speed of transistor switching circuits. These are: 1) carrier storage delays, where the transistors are operated in saturation, 2) the limitations imposed by transistor and circuit capacitances, 3) a cutoff frequency, 4) diffusion or transit-time delay, 5) storage time in associated diodes. If transistor switching circuits are to have response times limited primarily by the bandwidths of the transistors operating as amplifiers and by diffusion or transit-time delay, it is necessary to avoid operation in saturation. As low collector-to-base voltage generally has a detrimental effect on transistor bandwidth, it is desirable, as well, to avoid operation near saturation. Where nonsaturating circuits are used, and when transistors having cutoff frequenceis of several hundred megacycles are considered, circuit capacitances become the primary limitation on speed. If we assume a current step into a node, where there is capacitance to ground a t the node, the voltage rise time is proportional to the required voltage swing. Therefore, to minimize the effects of circuit and transistor capacitances it is desirable to operate with voltage swings as small as reliability considerations will permit. A new mode of operation has been developed whereby well-specified currents can be switched reliably with small voltage swings. Transistors are operated well out of saturation, and switching speeds approach that of a grounded-base amplifier driven by a current step. The resulting logical circuits reset their own lev~ls. The circuits place no requirement on the upper limit of a and have a dc stability factor of unity. They have complemented outputs and provide an essentially constant load to all dc power supplies. The circuits are simple and relatively noise free.

more negative then the potential at the base of the bottom transistor (in this case, ground), the current, I, will flow in to the emitter of one transistor to the exclusion of the other. A voltage swing of +0.4 to -0.4 volts about the reference voltage has been found sufficient to guarantee switching of up to 10 ma in high-frequency experimental drift transistors. For a positive input voltage whose magnitude is equal to, or greater than, the emitter-to-base voltage drop of the bottom transistor, the bottom transistor will conduct and the top transistor will be off. For a negative input voltage whose magnitude is equal to or greater than the emitter to base voltage drop of the top transistor, the top transistor will conduct and the bottom transistor will be off. The collector current for the nonconducting transistor will be leo, and the collector current for the other will be Ieo+aI. For a voltage step applied at the input, the transient behavior of the circuit approaches that of a groundedbase amplifier driven from a current step. There is simultaneous switching of emitter currents in the two transistors. The outputs of the transistors are complementary. If a complemented output is not desired, the bottom transistor may be replaced by a diode. As noted above, the dc stability factor is unity.

THE MODE OF OPERATION

COUPLING TECHNIQUES

The basic principle of the mode of operation presen ted here is the switching of a constant current in to the emitter of a single transistor, or the emitters of a group of parallel transistors, to the exclusion of other transistors whose emitters are tied to the same node. This mode of operation is best illustrated by an examination of the basic building block shown in Fig. 1. If the vol tage at the base of the top transistor is permitted to assume a value either slightly more positive or slightly

There are several techniques for coupling basic building blocks or the resulting logical circuits. One technique uses alternate p-n-p and n-p-n blocks, directly coupled. Another uses low impedance voltage translating blocks as coupling devices. Two basic building blocks, one a p-n-p block and the other an n-p-n block, are shown in Fig. 2. Both blocks are 6-ma current switches. An unloaded input voltage swing of ± 0.6 volt with respect tothe reference voltage at the base of the bottom transistor is required for reliable switching in either block. The voltage levels at the out-

T

t Research Center, IBM, Poughkeepsie, N. Y.

COLLECTOR CURRENT FOR ON TRANSISTOR:. .1 + lco

COLLECTOR CURRENT FOR OFF TRANSISTOR Ico

=

Fig. 1-Basic transistor block.

From the collection of the Computer History Museum (www.computerhistory.org)

Yourke and Slobodzinski: Millimicrosecond Transistor Current Switching

69

+.•

T~

J-.'

+.61

-.6

-(V+.6)

,-------,---------,----1+.

6

l-(V-.6} L - -_ _----'-_------'--4

-.S

L-(V+.6}

Fig. 2-N-P-N and p-n-p basic transistor blocks with input and output levels shown to illustrate compatibility.

puts are ideal for driving blocks of the opposite kind. The 3 rna current sources in the collector circuits are not essential. Their use, however, permits the collector load resistors to be returned to the reference voltage of the succeeding stages, thereby reducing the effects of noise on the reference voltage lines. The peaking coils provide' a degree of transient overdrive and improve the speed and cascading factor. Since collector voltage swings are small, the transistor may operate at a fairly constant collector voltage whose magnitude is chosen to provide maximum transistor bandwidth. Generally, the ·collector voltage would be as large as breakdown voltage and power dissipation considerations would permit. In Fig. 3, a p-n-p block is shown driving a number of n-p-n blocks located at a relatively large distance. The peaking coil and collector load resistor have been moved from the p-n-p block to the vicinity of the n-p-n blocks being drjven. Since current is being transmitted, rather than voltage, series parasitic elements along the line, such as contact-resistance and inductance, have no effect on the dc levels at the end of the line and have little effect on the transient behavior. The voltage at the inputs to the n-p-n blocks will be either 0.6 volt more positive or 0.6 volt more negative than the reference voltage; and the system is virtually insensitive to noise on the reference voltage. Since impedance levels at all nodes are 200 ohms or less, the system is relatively free of noise due to capacitive coupling. In the example shown, the long line is terminated in a dc impedance of 200 ohms. If larger currents were to be switched the line could be terminated in a proportionally lower impedance, since the required voltage swing would be essentially the same. This technique of placing the load resistor at the end of the long line should lend itself to coupling through low characteristic impedance transmission lines. The use of voltage translating blocks for coupling basic building blocks or the resulting logical circuits is illustrated in Fig. 4. The black box contains a battery, or any device that simulates a battery, and provides an essentially constant voltage drop equal to the desired nominal collector voltage. With the upper transistor cutoff, I rna flows through the black box. The source on the load side of the box provides a current of 1-3 rna,

Fig. 3-A p-n-p block driving a number of remote n-p-n blocks.

I-----,-~----

J

+.6-1

+.6

-.6 2000

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Fig. 4-Application of a voltage translating block as a means of coupling.

and 3 rna flows out of the load resistor, establishing an output potential of -0.6 volt. When the upper transistor is conducting 6 rna, 1-6 rna flows through the box, and since 1-3 rna is provided on the load side of the box, 3 rna flows into the load resistor, establishing an output potential of +0.6 volt. The output of this block may drive either p-n-p or n-p-n blocks. Although this coupling technique requires more components and consumes more power than does the coupling of alternate p-n-p and n-p-n blQcks, the advantages of low impedance levels and relative freedom from noise are retained. TYPICAL LOGICAL CIRCUITS

A nd-Or Circuits Application of the current switching principle described here results in a variety of circuits capable of performing many logical functions. A description of a few such circuits will illustrate the versatility of the system. A typical building block is shown in Fig. 5. Using the notation that the output of a conducting transistor and the input enabling it to conduct are logical ONE's, this circuit may be called an N-way complemented OR circuit. This notation is convenient in dealing with the coupling of alternate p-n-p and n-p-n logical blocks.


70

1957 vVESTERN COMPUTER PROCEEDINGS

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LOGICAL PNP l.NPUT NPN OUTPUT -0.6= "1" +0.6= "0"

NOTATIONPNP OUTPUT NPN :INPUT -y + 0.6 =",i" -Y-0.6:"0"

Fig. 5-N-way complemented OR circuit.

Where any or all of the in pu t signals to this circuit are logical ONE's, the current through the parallel combination of the top transistors is 6 ma, and the current through the bottom transistor is zero. The bottom transistor conducts 6 ma only when all inputs are logical ZERO's. For this case, the combined current through the top transistors is zero. Since all signals have their complements available, the circuit can perform AND or o R operations on N signals. Fig. 6 is a photograph of an input waveform and the output waveforms of a 3-way complemented OR circuit, with two inputs held at logical ZERO. The input waveform, a ten megacycle square wave, is shown at the top. The two output waveforms are shown below. The noninverted waveform is the AND output and the inverted waveform is the OR output. The circuit was operating as a 6-ma current switch, using drift transistors. The oscilloscope was synchronized with the input signal. Fig. 7 shows the response of the same circuit when two complementary inputs are applied while the third is a logical ZERO. Ideally, the two outputs should remain constant. The AND output, shown in the center, is a logical ZERO. The OR output, shown at the bottom, is a logical ONE. Some logical noise does appear at the OR output when the 6-ma current is switching between two of the three parallel transistors. Fig. 8 compares the outputs of a 3-way complemented OR circuit, shown at the top, and a 10-way complemented OR circuit, shown below, when driven from the same signal. Only slight degeneration in both waveshape and delay is observed, indicating that the useful number N for the N-way complemented OR circuit is quite large. To obtain an indication of the cumulative delay through logical stages, a circuit was constructed having four 3-way complemented OR circuits in sequence, each with a cascading factor of three. This circuit is shown in Fig. 9. The blocks were 6-ma current switches using drift transistors, and could be connected through the inverted or the noninverted outputs. The delay through the system is measured between any output on the right and the input to the first three blocks. Fig. 10 is a photograph of the input and output waveforms of the system. At the top are the input and output waveforms when the blocks are connected through

Fig. 6-Three-way complemented OR circuit. Two inputs are logical ZERO's, third input is the top waveform. Lower waveforms are outputs. (Hor.: 20 musec/cm, vert.: 1 volt/em.)

Fig. 7-Three-way complemented OR circuit. One input is a logical ZERO, top waveforms are two complementary inputs. Center waveform is AND output. Lower waveform is OR output. (Hor.: 20 musec/cm, vert.: 1 volt/em.) .

Fig. 8-0utputs of a ten-way complemented OR circuit, lower waveforms, compared with the outputs of a three-way complemented OR circuit, upper waveforms, driven by the same input signal. (Hor.: 20 musec/cm, vert.: 1 volt/em.)

the inverted outputs. Four inversions result in an inphase output. The lower waveforms are the input and output waveforms when the blocks are connected through the noninverted outputs. The total delay through the four blocks in both cases is between 35 and 40 millimicroseconds.

Exclusive OR Another important logical block is the exclusive OR circuit. A six-transistor complemented exclusive OR circuit is shown in Fig. 11. This circuit makes use of the fact that all signals have their complements available. The combined outputs of the bottom transistors will be 6 ma for the exclusive OR statement'and will be zero for the two other possible statements. The combined outputs of the top transistors will be 6 ma for the exclusive OR statement and 12 ma for the two other possible statements.


Yourke and Slobodzinski: Millimicrosecond Transistor Current Switching

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r---~----~----~------~--~-4AB+AB 200~

A

200~

L---------~--------~--~--AB+AB

Fig. l1-Six-transistor, complemented, exclusive OR circuit.

Fig. 9-Block diagram of four complemented OR circuits in sequence, with a cascading factor of three.

Fig. 10-Input and output waveforms of four sequential three-way complemented OR circuits with a cascading factor of three. Top waveforms are input and output of the system with blocks connected through inverted outputs. Lower waveforms are with the blocks connected through noninverted outputs. (Hor.: 20 musec/ cm, vert.: I volt/em.)

Fig. 12-Simple two-transistor trigger or flip-flop.

The 3-ma and 9~ma current sources are arranged so that the currents into the 200-ohm terminating resistors switch between plus and minus 3 rna. The switching speeds and logical noise for this circuit are essentially the same as for the complemented OR circuit.

Triggers This mode of operation, using small voltage swings to switch well defined currents, lends itself readily to the design of triggers or flip-flop circuits, the simplest of which is shown in Fig. 12. The circuit is bistable by virtue of the common-emitter current source and the feedback from one collector to the opposite base. The circuit may be triggered by pulsing the base of the transistor which is tied to the opposite collector. The lack of symmetrical inputs makes it difficult to employ conventional pullover techniques without changes in the collector to base feedback loop and the base circuit of the normally grounded base transistor. Fig. 13 illustrates a typical trigger circuit employing feedback to both bases with p-n-p emitter follower pullovers. The 200-ohm resistors are the loads normally found in the collectors of a 6-ma transistor block as described previously. The base of the ON transistor will be biased at -0.6 volt while the base of the OFF transistor will be biased at +0.6 volt. The pullover transistor bases are normally at +0.6 volt. During a set or reset operation, the appropriate pullover base is brought

Fig. 13-A typical trigger circuit for use in set and reset operation using p-n-p emitter followers for pullover.

to - 0.6 volt. This causes the emitter to follow the input with some level shift. However, the emitter load of the pullover is brought sufficiently past the point where regeneration begins so that the set or reset operation is completed with a minimum of delay. A degree of overdrive is obtained by emitter follower action, and also because the collector of the active pullover transistor is tied to the collector of the transistor whose base is being switched. Hence, a times the emitter current of the pullover transistor appears at the collector of the transistor being turned on, thereby enhancing the output signal at that point. Fig. 14 shows an extension of the technique to the use of n-p-n emitter followers as pullover transistors. Here the pullover bases are normally biased at - 0.6 volt


1957 WESTERN COMPUTER PROCEEDINGS

72

Fig. is-Input and output waveforms of three sequential triggers

II1II using p-n-p emitter followers as pullover transistors. The non-

inverted output signals were:used for coupling. (Hor.: 20 musec/ em, vert.: O.S volt/cm.) Fig. i4-A typical trigger circuit for use in set and reset operation using n-p-n emitter followers for pullover.

and the pullover collectors are tied to the collectors of the transistors being switched. Proper collector bias is obtained for the n-p-n transistors by the use of a translating block in the positive current source. The operation of this circuit is analogous to the circuit of Fig. 13 except that positive swings change the state of the trigger. The delays and rise times of the emitter following pullover triggers are of the same order of magnitude as those for the other logical blocks described. Fig. 15 is a photograph of the input and output waveforms of three sequential triggers using p-n-p emitter followers as pullover transistors. The noninverted trigger outputs were used for coupling, giving a total delay of approximately 15 millimicroseconds. This delay is essentially that of the emitter followers and is caused, in part, by the slope of the input waveform. The inverted output of the trigger will have delays somewhat greater than that of the noninverted output, since in this case the delay is dependent on the pullover transistor and the trigger transistors, as well as on the slope of the input waveform. These delays are of the same order of magnitude as the delay through a simple transistor block. Fig. 16 shows the delay through three

Discussion J. R. Braun (Electro Data) : What is used for the current sources shown? S. Sloan (Norden Ketay): Will you please describe the current sources used? David Zeheb (General Electric): What is the internal impedance of these sources? Mr. Yourke: Transistors can be used as current sources. For the circuit shown. the resistance value is of the order of SOO ohms. John Teska (North American): What is a "voltage translating block"? Mr. Yourke: The voltage translating block is a device which may be biased as to provide an essential, constant voltage drop for a relatively large current swing. This device is a typical type; however, for these

Fig. i6-Input and output waveforms of three sequential triggers using alternate p-n-p and n-p-n emitter followers as pull-over transistors. The inverted output signals were used for coupling. (Hor.: 20 musec/cm, vert.: O.S volt/cm.)

sequential triggers, employing alternate p-n-p and n-p-n emitter followers as pullover transistors, in which the inverted outputs were used for coupling. From Fig. 16, the total delay is approximately 24 millimicroseconds with a delay per trigger of approximately 8 millimicroseconds. ACKNOWLEDGMENT

The authors wish to acknowledge the contributions of other members of the high-speed transistor circuit group, and members of the semiconductor device group. Both groups are at the IBM Research Center, Poughkeepsie, New York.

circuits a very well-specified voltage swing is not essential, but is conceivable on others that are not so specified. J. Foulkes (Bell Telephone Labs.): Would you give us a few details of the transistors used? Mr. Yourke: The transistors used were of IBM manufacture. Their cut-off frequency speck is above 70 megacycles; some go up as high as 300 megacycles. However, for the circuits shown, the speeds are limited primarily by incidental specifications, and very little difference in time is observed where transistors have a cut-off frequency of more than 300 megacycles. J. P. Brosius, Jr. (Autonetics): Is IBM making any specific use of the exclusive "or" circuit, and, if so, what uses?

Mr. Yourke: The exclusive "or" circuit is used exclusively at IBM. A great deal of use is made of the "or" circuit in adding operations. R. C. Spriestersbach (Librascope): Have you worked with silicon transistors in this type of circuit? If so, how fast? Mr. Yourke: No, we have not. David Zeheb (General Electric): Do you safeguard against an open circuit, and if not, what value of voltage will result in case of an open circuit? Mr. Yourke: The only place where any problem could be serious is in the voltage translating block with n-p-n and p-n-p transistors. There is very little danger of excessive voltage from open circuit at any point.
