multiplication can be implemented using a network of binary ... Figure 1. a) Carry-propagation adder symbol and ... The sign can be arbitrarily selected since.
MINIMUM-ADDER INTEGER MULTIPLIERS USING CARRY-SAVE ADDERS Oscar Gustafsson, Henrik Ohlsson, and Lars Wanhammar Department of Electrical Engineering, Linköping University, SE-581 83 Linköping, SWEDEN E-mail: {oscarg, henriko, larsw}@isy.liu.se
ABSTRACT In this paper we investigate graph-based minimum-adder integer multipliers using carry-save adders. The previously proposed approaches use carry-propagation adders with two inputs and one output and are not suitable for carry-save adder implementation when we have a single input and a carry-save output of the multiplier. Using carry-save adders avoids carry propagation and will result in a higher throughput. We find that mapping from carry-propagation adders to carry-save adders is suboptimal and the multipliers should be designed for carry-save adders directly. Multiplier graphs up to five adders are presented. Exhaustive search finds that for carry-save adders savings are possible for coefficients with wordlength larger than nine bits. For 19 bits an average saving of over 10% is obtained.
1. INTRODUCTION Multiplication with a constant fixed-point number is a basic operation in many digital signal processing applications. A multiplication can be implemented using a network of binary shifts and adders (or subtractors). For bit-parallel arithmetic the shifts (multiplication by a power of two) can be hardwired and therefore do not require any gates. The hardware cost can thus be approximated with the required number of adders and subtractors. For two’s complement numbers, the hardware cost of a subtraction is approximately equal to that of an adder. For convenience both adders and subtractors will therefore be referred to as adders. Since a fixed-point number can be converted to an integer number by multiplication by 2 N for some N, only integer numbers will be considered. An N-bit integer number can be expressed as N–1
c =
∑ bi 2 i
(1)
i=0
where b i ∈ { 0, 1 } for a binary number. The number of ones is on average half of the coefficient wordlength. Using canonic signed-digit code (CSDC) [1] we have b i ∈ { – 1, 0, 1 } and b i b i + 1 = 0 , i.e., no two consecutive bits are nonzero. For a CSDC number approximately only one third of the bits are nonzero. The number of adders required for a multiplication is proportional to the number of nonzero bits. Thus, CSDC representation is advantageous compared with binary representation and will here be used as a reference.
Methods to further decrease the number of adders needed has been proposed by a number of authors [2]–[5]. The most competitive algorithms are those proposed by Dempster and Macleod in [4] where the suboptimal algorithm in [3] were improved and a new optimal algorithm was proposed. In [6] and [7] the same authors show that their algorithms are superior to those proposed in [2] and [5], respectively. However, these algorithms are based on carry-propagation adders with two inputs and one output, but for many highspeed applications carry-save arithmetic is preferred [8]. By using carry-save adders the need for carry propagation in the adder is avoided and the latency of one addition is equal to the gate delay of a full adder. The carry-save adder has three inputs and two outputs, where the two outputs together form the result. One of the outputs is the sum output, while the other is the carry output. In Fig. 1 a) a carry-propagation adder is shown while a carry-save adder is shown in Fig. 1 b).
X Y a)
xNyN
x2 y2
x1 y1
x0 y0
sN
s2
s1
s0
cN+1
S X Y Z
xN yN z N
y2 z2 x1 y1 z1 x0 y0 z0
b) C S
cN+1 sN
c3 s2
c2 s1
c1 s 0
Figure 1. a) Carry-propagation adder symbol and structure. b) Carry-save adder symbol and structure. The length of the carry output increases with one bit after each addition, but by using the carry overflow detection proposed in [8] the length can be kept constant. If the input to the multiplier is in carry-save format the previously proposed multipliers can be used by replacing each adder with two carry-save adders. However, if the input is only one binary word the mapping to carry-save adders will be suboptimal. This is the case in for example transposed direct form FIR filters as shown in Fig. 2 or in direct form FIR filters when not considering any possible symmetry in the multiplier coefficients. The bold lines denotes carry-save representation of the data. Carry propagation is performed in the final vector merging adder (VMA). To demonstrate that the previously proposed approaches are not suitable for carry-save adders consider a multiplication
in
a)
T
T
T
VMA
out
Figure 2. FIR filter using carry-save arithmetic. with 425. According to [4] the minimum adder realization is obtained using three adders as shown in Fig. 3 a). If this is mapped to carry-save adders we will have the realization shown in Fig. 3 b), requiring four carry-save adders. However, the CSDC multiplier based on carry-save adders shown in Fig. 3 c) realizes the same multiplication using only three carry-save adders as 425 = (1010101001)CSDC, where the inverted input denotes subtraction. This is also a minimum-adder multiplier using carry-save adders. Of the seven possible multipliers using three carry-propagation adders described in [4], two uses two carry-save adders, three uses three carry-save adders, and two uses four carry-save adders. For the 32 multipliers using four carry-propagation adders in [4] the number of carry-save adders for the corresponding implementations ranges from three to six. It is clear from the previous discussion that the optimal solution using carry-propagation adders will in general not be the same when using carry-save adders. In this paper we investigates multipliers structures using a single binary input and carry-save adders. In the next section the proposed multipliers are described. Then, in section 3, the results are presented, and finally some conclusions are drawn.
2. GRAPH-BASED MULTIPLIERS The graph representation of multipliers were introduced in [3]. Here we utilize this technique to represent the different topologies for the possible multipliers. The graphs are directed acyclic graphs (DAGs), i.e., there is no feedback and the edges have a direction. Each edge in the graph represents a multiplication with ± 2 n , i.e., a binary shift. The sign can be arbitrarily selected since subtraction is as expensive as addition. The edge can either be a single binary word or in carry-save representation. Each vertex in the graph, except for the initial, represents an addition. Each vertex can have two or three inputs and an arbitrary number of outputs. If the vertex has three inputs all have to be single binary words. The corresponding hardware is then one carry-save adder. One carry-save adder is also obtained for one single word and one carry-save input. If both inputs are in carry-save format, two carry-save adders are required in the corresponding implementation. Other combinations are also possible, such as two single binary words and one input in carry-save format, but those described are sufficient for all graphs in Fig. 4. The output of a vertex is always in carry-save representation. All possible combinations of edge values for the given graphs can be searched and the minimum-adder solution can easily be found. Figure 4 shows all possible graphs generating different sets of coefficients using up to five carry-save
b)
c)
