Mixed Loopback BiST for RF Digital Transceivers Jerzy Dąbrowski Javier Gonzalez Bayon Linköping University, Dept.of Electrical Engineering SE-581 83 Linköping, SWEDEN e-mail:
[email protected] Abstract In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generator and response analyzer. The test is oriented at spot defects in a transceiver front-end. Estimates for noise, signal power and nonlinear distortions such as EVM (or SER), gain and IP3, respectively, are considered the test responses. Limitations of these tests are investigated with respect to the test path properties, the strength of defects and circuit tolerances. The IP3 test complements the EVM (SER) and gain tests for some spot defects. The analysis is verified by simulation of a functional-level RF transceiver model implemented in Matlab¥.
1. Introduction At present a common trend in personal communication ICs design is to reduce the RF circuitry in a front-end, and to implement most of the transceiver functionality in software. Nevertheless, a high enough quality of the RF part is essential to achieve the intended performance of the transceiver chip. The problem of verifying correctness of the RF circuitry is not diminished, and to perform test, expensive RF equipment (ATE) has still to be employed [1]. On the other hand, the advancing complexity and performance of present RF transceivers are pushing the ATE to the edge of its limits. In this context an alternative approach based on the built-in self-test (BiST) is appealing and can alleviate the problem. In this paper a BiST for a RF transceiver front-end is discussed in a context of noise- power gain- and nonlinear distortions analysis. The loopback technique is used having the advantage that all the functional front-end blocks are under test, and their sensitive nodes are not affected by external equipment, neither much extra test circuitry is put on a chip [2-6]. Using an RF front-end model we are specific about signal path sensitization for enhanced fault detection. With this approach we aim at CMOS RF ICs that are frequently subjected to spot defects that can severely degrade the performance or result in chip malfunction [7-9]. The spot defects are layout dependant and result in electrical opens and shorts or can take softer form of resistive breaks or bridges. In a test plan it is important to detect those faults early in order to cut the total test costs. Using a hierarchy abstraction from layout up-to system level we arrive at impairments in RF specifications such as gain, noise figure (NF) or IP3. Those impairments can be considered faults at the system-level, where the RF-test issues are becoming more tractable [4,11]. A kind of mapping from circuit to chip level in a spot-fault perspective is exemplified in Fig.1, where shown is an impact of spot defects (breaks and shorts) on gain and NF for a typical CMOS Gilbert mixer [10]. With this mapping we aim at noise analysis supporting a loopback BiST for an IC transceiver front-end. In this case a baseband processor serves both as a digital test pattern generator and a response analyzer (Fig.2). The test loop is closed by an on-chip test attenuator (TA), disabled in a normal operation mode. Besides, Tx and Rx have to operate with the same carrier frequency, like CDMA systems, and otherwise an extra mixer is needed in the test loop [3]. A symbol error rate (SER) or error vector magnitude (EVM) measured by the baseband (BB) processor are test responses, which in fact, are equivalent
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(a) (b) Figure 1. Impairments in NF and conv. gain of CMOS Gilbert mixer vs strength of spot defects: breaks - (a), and shorts - (b). The fault-free NF = 10.6 dB and G = 7.5 dB.
to a signal to noise ratio (SNR) at the receiver Sout Sin output. Using this architecture also other Rx test out complementary tests such as for gain or nonlinear distortions can be implemented. A f0 possible advantage of the IP3 test is shown in BB LO Fig.3 where the responses were obtained for the same faults as in Fig.1. In some cases, TA f0 such as for the short F7, the IP3 response is even more pronounced than the respective test in Tx impairments in NF or gain. This observation, S0 although promising, cannot be overestimated, and as we show in the paper, the IP3 test can be considered complementary to EVM- and Figure 2. Loopback BiST set-up for RF IC the power gain tests. digital transceiver. The paper is arranged as follows. In Section 2 we develop a behavioral model for noise-, power- and nonlinear distortion analysis for an RF transceiver front-end under test, and point to the main mechanisms of the proposed BiST. Section 3 provides a detailed discussion on spot fault modeling with respect to three different tests applied. In Section 4 we present some simulation results obtained with a functional model for the proposed BiST. In Section 5 discussed is an impact of tolerances, where the detectability thresholds for two different tests are derived and their performance is analyzed. Final conclusions are given in the last section.
2. Behavioral BiST Model 2.1. Noise performance To charecterize the BiST in terms of noise performance the SNR can be used. First, we focus on the receiver path where the input and output are related by the formula: SNRout
SNRin SNRin 1 ( NFRx 1) S in N ref
where Sin, NFRx, Nref are the input power, noise figure and reference noise, respectively.
Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’04) 1550-5774/04 $ 20.00 IEEE
(1)
(a) (b) Figure 3. Impairments in output IP3 of CMOS Gilbert mixer vs strength of spot defects, breaks - (a) and shorts – (b). The fault-free IP3 = 7.8 dBm
Figure 4. Probability of error in QPSK demodulator vs receiver NF for Sin/Nref = 17dB ÷ 20dB.
Figure 5. Sensitivity dpe/dNFRx vs Sin/Nref of receiver for NF = 6dB ÷ 9dB.
Obviously, SNRout is an ascending function of Sin for constant SNRin, and the impact of NFRx on SNRout (due to some defect) would only be visible for low enough signal level Sin. In a digital receiver SNRout is directly related to the probability of an error, pe, in a demodulator [13, ch.7] that is frequently measured as SER. A relation between pe and the involved parameters for a QPSK system (as an example) is depicted in Fig.4 [11]. Apparently, impairments in NFRx raise pe, and larger increments 'pe are obtained for reduced SNRin (mind the log scale). The corresponding sensitivity w pe w NFRx versus S in N ref is given in Fig.5. On the other hand, the measurement resolution of pe is limited by the test sequence length. To reduce the test time one is interested to use shorter test sequences, but as a consequence the test sensitivity is sacrificed due to quantization of pe. This effect is shown in Fig.6 for a sequence of 2000 symbols (resolution = 0.5*10-3 which is equivalent to one error). It can be shown that in some cases even a significant NF increment is hardly detected unless the resolution is increased. An alternative to SER is the EVM test, which is based on a concept of the signal constellation measured at the receiver output [12]. An EVM response can be defined as EVM
¦ z k sk k
2
¦ sk
2
(2)
k
where sk stands for the reference constellation point and zk for the actual constellation point, usually affected by test path noise or additionally by some defect in the circuit (Fig. 7). In contrary to SER it does not require an error to occur in the received symbol sequence. EVM
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response tends to display any disturbances in the received signal, so even small constellation variations according to impairments in the receiver or transmitter NF would be visible during the test. Apparently, EVM can be related to SNRout by: EVM
1 SNRout
(3)
Combining (3) and (1) EVM can be depicted versus the involved parameters (Fig.8). For high sensitivity of the test both low Sin and low Nin should be used. Obvious limitations in this case are the noise floor and the receiver sensitivity. On the other hand, the test resolution depends here on the number of ADC bits and the numerical precision of DSP.
Figure 6. pe and SER vs receiver NF for 2000 symbols and SNRin = 10 dB.
2.2. Gain and nonlinear distortion performance The baseband signal sampled at the receiver output can be used to estimate the actual signal power and thereby reveal impairments in the loop gain. Specifically, all blocks contribute to this test response in the same way, so if a gain is locally degraded no matter where the spot fault is located: S out GTxGTAGRx S0 (4) This is unlike EVM test for which faults located closer to the receiver output are more difficult to detect that one can infer from Friis formula. Since signal power is measured here, to minimize the impact of noise we would aim at a high enough SNR, and NF of TA should be kept low as well so GTA should be adjusted high. This is in contrast to the noise-oriented test setup where low signal power was needed to sensitize the test response. The gain test can be combined with the measurement of nonlinear distortions when a harmonic baseband signal is applied. With a two-tone or single-tone stimulus, and FFT applied to the received signal, we arrive directly at IM3 or HD3, which may serve as the test responses. On the other hand, IP3 is more suitable to discuss the test performance ( IP3 2 P1 IM 3 and P1 is a power of the fundamental component). Based on IP3 consider a fragment of the test loop composed of two RF blocks in series: (5) 1 IP3eq # 1 IP31 G1 IP32 where G1 is a power gain of the first stage. From (5) we can see that an impairment in IP3 (of “strength” n-times) in either block would be visible in the equivalent IP3eq, provided the contribution of each component is similar. Also, one can sensitize the path for IP31 or IP32 impairment by decreasing or increasing G1, respectively (the issue is the relative sensitivity). This observation holds for the IM3 and HD3 estimates as well, since they are proportional to 1/IP3.
3. Spot fault analysis From Fig.1 one can see that the spot faults tend to fall into 3 classes. For a given RF block faults of class #1 would satisfy the condition 'G = -'NF where the increments are expressed in [dB]. On the other extreme faults of class #2 satisfy 'NF | 0 but are still visible for nonzero gain impairments 'G that they evoke. Faults resulting in gain impairments larger than the impairments in NF would belong to class #3. With respect to the above classification we can be more specific about pe and EVM as test
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D2 00
01 sk
11
zk
D1
10
Figure 7. Constellation in QPSK system
Figure 8. EVM vs receiver NF for Sin/Nref = 17dB ÷ 20dB
responses for spot defects located in different blocks. Here, we concentrate on the receiver (for a broader discussion refer to [11]). Using the Friis formula: NFRx
NFLNA
NFMixer 1 NFother 1 GLNA GLNAGMixer
(6)
while SNRin at the receiver input would be provided by: SNRin
SNR0 SNR0 1 ( NFTx TA 1) S 0 N ref
(7)
where S0, SNR0 are power and SNR at the Tx baseband, and NFTx+TA denotes a combined NF of Tx and TA. Based on (6) we can “inject” spot defects into different blocks. At this abstraction level they are represented by impairments in gain and NF, respectively. Here, we can also observe that faults of class #1 would affect NFRx much more than those of class #2 (unless located in the last stage). Combining (6), (7) with (1) and (3) one arrives at test responses to different defects. In Fig.9 shown are pe and EVM test responses to fault #1 located in LNA. The faultfree LNA is assumed to have a gain GLNA = 16dB and NFLNA = 6dB. The fault strength varies here by 3dB. Tuning the TA gain within 6dB range provides pe larger by at least one order of magnitude. In practice however, pe is subjected to quantization according to the test sequence length, and the test detectability is locally lost (Fig.6). Observe also that much longer test sequences (about 100x) are required for SER test with SNRin = 13dB compared to SNRin = 10dB since the respective values of pe differ by 2-3 orders of magnitude. The EVM test does not suffer from this effect, and in practice, the measurement resolution (ADC, DSP) would not be a limitation. As compared to LNA, faults located closer to the Rx output are more difficult to detect that one can infer from (6). However, this effect can be mitigated to some extent by reducing the power level Sin applied. On the other hand, defects located in Tx exhibit similar detectability to those in LNA [11]. In the power gain test the spot defects are subject to eqn.(4). Upon gain impairment in i-th block, the loop gain simply drops by 'Gi. dB. Using this test one can expect to easier detect defects located closer the Rx output as compared to EVM. On the other hand, there is no special way to provide more sensitivity to this test response. Finally, consider the spot defects under the nonlinear distortion test, For this purpose refer to (5) and assume a defect in the first stage. If degraded is both IP3 and gain, the fault tends to be masked. Specifically, if both components of (5) are equal and 'G1 = 'IP31 (in dB) then the equivalent IP3 remains unchanged. Such a defect would be detected rather with the noise
Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’04) 1550-5774/04 $ 20.00 IEEE
(a)
(b)
Figure 9. Test responses vs TA gain for faults #1 located in LNA, (a) pe, (b) EVM.
oriented EVM test or gain test. If 1/IP31 is much smaller than G1/IP32, then upon this defect IP3eq would be raised by -'G1 dB, so the defect would be detectable due to the gain impairment. On the other extreme, there are also spot faults that only affect IP3. These are in particular breaks in MOST drains that result in imbalance in a circuit, such as in a Gilbert mixer (not shown in Fig.3).In this case, the fault will be detected unless the respective component 1/IP3 is negligible compared to others in the fault-free loop. Also here, gain tuning would be helpful to sensitize the loop for IP3 impairments, and thereby to enhance detectability. During the test for nonlinear distortions, TA only contributes with its gain. Usually, its 1/IP3 can be neglected, but by tuning its gain one can sensitize the RF path for defects located in the receiver or transmitter as explained before.
4. Fault Simulation Table 1. Transceiver model specifications To verify the BiST mechanisms discussed above a functional Block NF [dB] G [dB] IP3 [dBm] model of WLAN transceiver such as 802.11b Std. has been LNA 4 18 0 implemented in Matlab¥. The Rx Mixer 10 -3 10 model is arranged as a direct Filter 13 27 15 conversion Tx and zero-IF Rx, and Mixer 10 0 10 Tx when in the test mode it operates Filter/buffer 8 0 15 as a QPSK system. The test response is measured by DSP analyzer at baseband. The basic specifications for the transceiver components are given in Tab.1. The NF parameters have been adjusted using additive white Gaussian noise (AWGN) sources. To limit the simulation time of SER test a pseudo-random sequence of 2000 symbols has been chosen with a corresponding resolution 5e-4. With a power of -79 dBm at the Rx input and SNR = 10dB at baseband, the fault-free TRx under test provided SER = 2.5e-3. This value was considered a reference during SER fault simulation, which we performed at that power level. For lower power levels higher values of reference SER were obtained (Tab.2). To sensitize the RF path for weaker defects useful is lowering of signal power (while keeping SNR unchanged). For example, the defect (0dB; 1dB) in LNA is only barely visible with SER = 3e-3 compared to the reference equal 2.5e-3 at -79dBm. By reducing the power by 2dB this defect becomes evident in the test response for SER = 6e-3 versus 4e-6 as reference (the resolution of the test is still 5e-4).
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Table 2. Results of SER test simulation Faults located in the transmitter prove to be well detectable, almost SER 'NF 'G like those in LNA. Unlike this, @ -81 dBm @ -79 dBm Block [dB] [dB] SER0 = 2.5e-3 SER0 = 4e-3 faults located closer to the receiver 0.6 0.6 3e-3 4.5e-3 output are more difficult to detect. Mixer 0 1 3.5e-3 5e-3 Tx They require even lower signal Filter 0.8 0.8 3.5e-3 5e-3 power that might be hard to /buffer 0 1 3.5e-3 5.5e-3 achieve in practice. 0.8 0.8 3e-3 5e-3 LNA 0 1 3e-3 6e-3 To cope with this problem the 0 2 4e-3 9e-3 EVM test has been introduced. The 0 2 3e-3 4.5e-3 first observation was that a test Rx Mixer 1 2 3e-3 4.5e-3 sequence limited to only 100 4 4.5 3.5e-3 5.5e-3 symbols provides EVM responses 1 1 2.5e-3 4e-3 Filter 2 3 2.5e-3 4e-3 with 5% accuracy as compared to 3 3 3e-3 4.5e-3 2000 symbols applied. The time savings obtained in this way were up to 20 minutes per one Table 3. EVM vs SER test simulation. Table 3 shows some of the simulation results for faults in EVM SER 'NF 'G Block LNA and Rx mixer in comparison SER0 = 2.5e-3 EVM0 = 0.3296 [dB] [dB] to SER test performed for the same 0 1 3.0e-3 0.3562 LNA 1 1 3.5e-3 0.4133 conditions. Apparently, the 1 1 3.0e-3 0.3727 quantization problem typical of Mixer 0 2 3.0e-3 0.4219 SER is avoided with EVM. 2 2 3.0e-3 0.4608 Nonlinear distortion simulation results are presented in Tab.4 for TA gain tuned to 0, -20 and -30 dB, respectively. The faultfree response is denoted as IP30. Two types of faults were used throughout this test, one with 'IP3 = 'G, and the other with 'G = 0. For TA gain of 0dB well visible in the test response are faults of the first type, located in Tx. This is because of impairment in gain that they evoke, and the IP3 response is raised by them. Faults of the second type with the same location are not detectable. To make them visible we have to reduce gain to -20 or -30dB. At the same time we can see that the fault in Tx mixer is more pronounced than that one in Tx filter. To understand this one has to compare their IP3 specs that differ by 5 dB. Faults of the first type located in Rx tend to be masked (e.g. in Rx mixer at 0 dB, or in LNA at -30 dB). On the other hand, faults of Table 4. Results of IP3 test simulation the second type in Rx are best visible at the highest IP3 [dBm] 'IP3 'G gain, when Rx prevails @ -20 dB @ -30 dB @ 0 dB Block [dB] [dB] IP30 = 5.88 IP30=8.09 IP30 = -10.58 with its 1/IP3 comp3 3 -7.51 5.09 6.08 onents. Again, the best Mixer 3 0 -10.63 4.22 5.73 Tx detectability achieves a Filter 3 3 -7.50 6.08 7.26 block with largest G/IP3, /buffer 3 0 -10.60 5.19 7.20 i.e. the Tx mixer. In 3 3 -8.17 6.23 8.12 LNA contrast to the first type, 3 0 -11.23 5.48 8.06 Rx 3 3 -10.80 4.84 7.86 faults of the second type Mixer 3 0 -11.92 4.81 7.90 only cause the IP3 3 3 -11.19 5.58 8.08 response to drop, and do Filter 3 0 -11.19 5.58 8.08 not exhibit self-masking behavior.
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5. Fault Masking PDF(w)
Parameter tolerances tend to mask faults in analog circuits. Using simulation it is good w0 faulty wf possible to capture this effect and try to estimate detectability thresholds for different types of faults including their different locations. To cope with this problem one can apply the “worst-case” analysis or the P0 Pf Monte-Carlo technique. Neither approach w however, is efficient. In the first case usually decision over-pessimistic estimates are obtained, Escapes border False (fault masking) while the other one suffers from an rejects excessive simulation time. To overcome those drawbacks, here, we Figure 10. Test response PDF refer to the behavioral model introduced in Section 2, and discuss the problem in terms of statistical parameters supported by sensitivity analysis. For this purpose consider a test response denoted by w (such as EVM, power gain or IP3). Its variance referred to parameters xi of the involved RF blocks (NF, gain or IP3, respectively) would be 2 (8) V w2 ¦ ww wx V xi2 i
Calculated from (8) variances for the fault-free circuit and a faulty one would be V 02 and V 2f , respectively. As shown in Fig.10, a fault drives the test response from w0 to wf , and to make it detectable the distance between the corresponding mean values µ0 and µf should be large enough. Otherwise, a lower confidence level would be achieved, and a significant number of“false rejects” or “escapes” during the test might occur. Here, we assume: P f P 0 t 3 V 0 V f
(9)
Solution of (9) with respect to (3), (1) and the Friis formula (where the loop blocks are specified) provides the “weakest” detectable fault i.e. the detectability threshold for EVM test. Figure 11a shows the results obtained for the transceiver parameters specified in Tab.1 when EVM test is applied. All the parameter tolerances were assumed the same, and to be of 3V, i.e. txi = t = 3(Vxi/xi)100%. In practice, those tolerances might be kept below 5% provided the blocks are designed as differential circuits, so that the corresponding detectability
(a) (b) Figure 11. Detectability thresholds 'G ( 'NF), (a) for EVM test, (b) for gain test
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thresholds (DTs) would be relatively low. Faults of type #1 located in LNA display the lowest DTs, which correspond well to the highest sensitivity of EVM response to this type of fault and its location [11]. Besides, we found that increasing the signal power and SNR only slightly affects those estimates. In Fig.11b shown are DTs for the power gain test. In this case, DT values neither depend on location nor the type of fault. The advantage of the power gain test is evident in case of defects located in blocks following LNA. The corresponding DTs are lower than those of EVM test, which only appears superior for faults #1 located in LNA as shown.
6. Discussion and Conclusions The loopback BiST architecture applied to an RF front-end has both strengths and weaknesses. Basically, one prevents the internal RF nodes from extra noise or external disturbances. On the other hand, more subtle fault detection without providing more controllability and observability of the RF blocks is difficult to achieve. The BiST shares the on-chip resources, and only the test attenuator (TA) is added on chip so the chip area is not much larger. The loopback architecture enables different tests so that mixed test can be run to enhance fault detectability. EVM test has been shown superior to the SER test. With EVM as the test response we can detect spot faults that degrade gain and/or NF of the involved RF blocks including phase noise impairments in LO. Faults located closer to the Rx output are more difficult to detect. In this case the fault strength plays very much role. To enhance detectability for those defects one can sensitize the RF loop by reducing the TA gain or run a complementary test for gain, which is insensitive to fault location. With the IP3 test we have primarily addressed faults that are not susceptible to EVM or the gain test. An obvious drawback is parameter tolerances, which impose limitations on detectability for the masking effect that they evoke. Using a simple statistical analysis we have derived estimates of the detectability thresholds for the tests applied. In this way also an extra criterion to compare the performance of those tests was obtained.
7. References [1]. A.Grochowski, et al, “Integrated Circuits Testing for Quality Assurance in Manufacturing: History”, IEEE Trans.CAS-II: Analog and Digital Signal Proc., Vol.44, No.8, Aug.1997, pp. 610-633 [2]. M.Soma, “Challenges and Approaches in Mixed Signal RF Testing”, Proc. ASIC Conf, 1997, pp.33-37 [3]. M.Heutmaker, D.Le, “An Architecture for Self-Test of a Wireless Communication System Using Sampled IQ Modulation and Boundary Scan”, IEEE Communication Mag., June, 1999, pp.98-102 [4]. J.Dabrowski, “BiST Model for IC RF-Transceiver Front-End”, Proc. of DFT’03, pp. 295-302 [5]. S.Ozev, C.Olgaard, “Wafer-level RF Test and DfT for VCO Modulating Architectures”, Proc. VTS’ 04, 6 pp. [6]. G. Srinivasan et al, “Loopback Test of RF Transceivers Using Periodic Bit Sequences”, IMSTW’04, 6 pp. [7]. M.Sachdev, B.Atzema, “ Industrial Relevance of Analog IFA: A Fact or a Fiction”, Proc.ITC’95, pp.61-70 [8]. M.J.Ohletz, “Realistic Fault Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits”, Proc. ITC’96, pp.776-785 [9]. Y.Xing, “Defect-Oriented Testing of Mixed-Signal ICs”, Proc.ITC’98, pp.678-687 [10].J.Dabrowski, “Fault Modeling of RF Blocks Based on Noise Analysis”, Proc. of ISCAS’04, 4 pp. [11].J.Dabrowski, L.Li, “Signal Path Sensitization for Built-in-Self-Test in Integrated RF Transceivers”, Proc. DDECS’04, pp.59-66. [12].(----) “Using Error Vector Magnitude Measurements ”, Agilent PN 89400-14 [13].S.Haykin, “Digital Communications”, Wiley, 1988
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