mm-Waves design trends in BiCMOS technology

mm-Waves design trends in BiCMOS technology T. Taris, R. Severino, Y. Deval, J.B. Begueret IMS laboratory 351 cours de la libération 33405 Talence Cedex, France [email protected] Abstract—mm-Waves building block design is the meeting point of distributed and RF analog techniques. After reviewing the skills of a 130nm mm-Wave dedicated back-end BiCMOS technology, this paper investigates these two design methodologies in an 80GHz cascode differential LNA implementation. A third version of the circuit taking advantage of both approaches is finally proposed. Operating under 2.5V and consuming 17mA it exhibits a 20dB maximum gain at 79GHz, and performs 5.4dB Noise Figure.

Characterization step is not a technology dependent process thus allowing distributed design flow to be easily reused. It is so an accurate tool for technology performance probing and application matching potentiality. It is also the single alternative when operating frequency is too high for RF analog techniques. lumped and / or

I.

INTRODUCTION

Imaging, sensing and data transmission domains initiate a high interest for research and product developments in the frequency range around 80 GHz. Among them we can find long range and short range automotive radar from 76 GHz to 77 GHz and 77 GHz to 81 GHz [1], respectively, data communication in the frequency bands 58-64GHz and 71–76 GHz, concealed weapons detection at 77GHz and above. Up to now these frequency ranges have been dominated by III–V compound whose expensive cost and sensitive set up cannot afford the aforementioned applications to match high volume production. Over the past years, improvements in silicongermanium led to transition frequencies (fT) and maximum oscillation frequencies fmax beyond 200 GHz, making this technology an alternative choice [2],[3]. The state-of-the-art demonstrates silicon circuits in W-band such as LNA, PA and mixer at 77GHz [4]-[7], and 94GHz [8]-[10], and 77GHz receivers and transmitters [11][15]. Concerning building block implementation, two kinds of design are reported: distributed [2] [4] [5] [11]-[14] and lumped [6] [10] [15]. This first based on electromagnetic (EM) field analysis occurs when signal wavelength is in order of circuit path size. It is the original high frequency design approach that can be merely described as it follows: active devices, characterized by S parameters, are tuned by distributed passive structures such as Transmission Lines (TL) and/or CoPlanar Wave guides (CPW) as depicted in Fig. 1. Characterized Active Device

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lumped maximum Gain input/output impedance Noise Figure …

Figure 2. Lumped design approach

RF analog approach presented in Fig. 2 combines lumped passive devices with transistor model to perform the functionality. Because lumped passive components, and by means inductors, exhibit a definitely lower silicon footprint than distributed structures, RF blocks herein designed are more compact. As well EM effects are less considered in such case. The so derived design flows are specific to a technology thus taking better advantage of transistor intrinsic performances than distributed approach. However active device modelling is a costly, time expensive and critical step of technology development compared to S-parameter characterization. After reviewing performances of a 130nm BiCMOS technology, this paper gives a brief description of a two stage differential cascode LNA design. Section III proposes post layout simulation results and design investigations of a fully T-Lines implementation, first, and then a lumped version of the LNA. Taking advantage of each approach a last circuit proposes a trade-off implementation for improved mmWaves design flow.

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II. A.

130NM BICMOS TECHNOLOGY AND DEVICES

Active device 130nm BiCMOS9MW technology of ST Microelectronics offers a high speed self aligned SiGe:C HBT with

Figure 1. Distributed design approach

978-1-4244-2332-3/08/$25.00 © 2008 IEEE

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250/280GHz fT/fmax and 1.6V BVCE0. Dual VT, high speed and low leakage, and dual gate oxide, 1.2V and 2.5V, 120nm MOS transistors are also available. As reported in Fig. 3, a 10µm*0.27µm npn transistor achieves 2.8dB NFmin and 250GHz fTmax for a 0.8mA/µm² and a 3.2mA/µm² current density respectively.

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Figure 3. fTmax and NFmin versus current density in a 10µm transistor

B. Passive devices 130nm BiCMOS9MW is a dedicated millimeter waves back-end based on BiCMOS9 process. As depicted in fig. 4(a), they differ from the 3 last Cu metal level, and oxide, which are set seeker in BiCMOS9MW. As reported in Fig.4 (b) this improves the quality of passive devices since the attenuation constant of a 50Ω microstrip transmission line becomes close to above IC BCB realizations. MIM capacitors implemented with the two last metal levels perform a 2fF/mm².

The TL and lumped inductor reported in Fig. 5 are assumed to be equivalent since they exhibit the same impedance behavior over the frequency band of interest – i.e. 77-81GHz-. In the TL, the center conductor is performed with Alucap and metal 6 via connected, ground plane uses all stacked metal levels. The 75pH inductor is set up stacking the two last metal levels and Alucap via connected, underneath, a pattern ground shield is made up combining active, polysilicon and metal 1&2 geometries. We can notice that the inductor needs a six time lower silicon area than TL to be implemented making lumped device well suited to low cost system development. Considering the quality factor reported in Fig. 6, both structures exhibit good performances between 21 and 27 depending on the value and the geometry of the device. Quality Factor 30 25 20 15 Ind50p Ind75p TLine200u TLine300u

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Figure 6. simulations of T-Line and Lumped inductor quality factor in 130nm mm-Waves BiCMOS9MW

(a) (b) Figure 4. Metal level backend comparison between BiCMOS9 and BiCMOS9MW technologies (a) attenuation constant comparison of a 50Ω microstrip transmission line (b)

In high-frequency circuits passive devices introduce extra loss and deteriorate the noise performance. Inductors and transmission lines are especially critical, since their Q-factor is rather low due to the lossy substrate and the metal resistance. Aforementioned TL and lumped inductors have been simulated with 3D ElectroMagnetic (EM) software to be compared. The back-end of the devices is depicted in Fig. 5.

These investigations on passive device implementations in 130nm mm-Waves BiCMOS technology seem to indicate that lumped inductors would be a better alternative than TL since they exhibit almost the same performances for a significant smaller silicon footprint. We are going now to test this assumption by implementing a Low Noise Amplifier (LNA). III.

TWO STAGE CASCODE DIFFERENTIAL LNA DESIGN

Fig. 8 depicts the schematic of an 80GHz differential LNA that has been implemented in the aforementioned 130nm BiCMOS9MW technology and dedicated to 77-81GHz radar applications. Cascode stages have been here selected to increase reverse isolation, by means stability and design flow trade-off. The first stage, (Q1,Q2), performs both 50Ω input matching and NF. The second stage, (Q3,Q4), improves voltage gain and provides 50Ω output matching.

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Figure 7. Layout excluding ground plan of TL LNA (a) Lumped LNA (b) TL-Lumped LNA (c)

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(a) (b) Figure 9. Sparameters (a) NF & NFmin (b) of full T Lines LNA

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Figure 8. Schematic of a two stage cascode differential LNA

In Fig. 8, (Q1,Q2) are sized to lower NF, because of cascode topology a roughly twice larger current density is required compared to common emitter skills reported in Fig. 3. The number of emitter in Q1 is set to achieve noise matching where as (Lb,Le) achieve 50Ω input matching by inductive degeneration. Lpck1 is tuned to optimize available gain (Ga) at 80GHz when Cm1 and Q3 are connected. Current density in (Q3,Q4) is close to fTmax in order to provide maximum gain. Lpck2 in combination with output network complete 50Ω output matching. The output network consists of a 300pH series T-Line and a 45fF shunt capacitor. IV.

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B. Lumped inductor LNA Mass market applications likewise Automotive Radar, the chip area remains a major of importance since it is in the straight-line with system development cost. So a lumped version of the LNA has been also investigated as shown in Fig. 7(b) leading to a significant reduction of the silicon area since the circuit now takes place within a 0.5 mm². Unfortunately, post layout simulations, reported in Fig. 10, do not complete with expected results, especially input matching and NF that is ill mannered in a LNA. NF & NFmin 20 15 S 21 (d B )

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CIRCUIT IMPLEMENTATIONS

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A. TL lines LNA A first version of this LNA was realized exclusively using T-Lines for inductor implementation as depicted in Fig. 7(a). We can observe that a more than 75% of the 1.5mm² silicon area is dedicated to T-Line implementation. Post layout simulations, reported in Fig. 9, exhibit a 23 dB maximum gain and -24 dB input return loss at 80GHz. In the frequency band of interest –i.e. 77 to 81GHz- the Noise Figure (NF) close to NFmin does not exceed 5.3dB.

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(a) (b) Figure 10. Sparameter (a) NF & NFmin (b) of full lumped LNA

Lumped inductors are designed and simulated with a 3D-ElectroMagnetic software –i.e. HFSS- as detailed in section II. They are then reported in the final circuit layout as stand alone cells and connected to devices. In inductive degeneration topology, LNA characteristics are very sensitive to input inductor values, (Lb,Le) here, since they perform both impedance and noise matching. Focusing on (Lb,Le,M1) routing area, Fig. 11, figures out that connection length

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between Lb and PAD, 40µm, Lb and M1, 80µm, are in the range of the inductor length itself, 104µm. As a result these terminations add unexpected impedances tuning out input matching, and by means, lowering LNA performances as reported in Fig. 10. Resizing of Lb in combination with these terminations, based on EM simulations, is mandated to retune the circuit. These recursive design steps make design flow esoteric and so less attractive.

lumped and T-Lines devices remains the best trade-off between performances and silicon bulk. TABLE I.

LNA VDD Iconso S21

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Figure 11. Zoom in input matching network of lumped LNA

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