Model Predictive Control of Neutral-Point Clamped Inverter with Harmonic Spectrum Shaping J. Rubinic, V. Yaramasu, B. Wu
N. Zargari
Dep. of Elec. and Comp. Eng. Ryerson University Toronto, ON, M5B 2K3, CANADA Email:
[email protected]
MV R&D Department Rockwell Automation Cambridge, ON, N1R 5X1, CANADA Email:
[email protected] (DFT) in the cost function to solve this issue. The authors in [5] presented a frequency weighted cost function to shape the harmonic spectrum. The addition of secondary control objectives to cost function reduces the relative importance of primary control objective, i.e., load current control. As a result, the quality (total harmonic distortion) of the load current deteriorates. The variable switching frequency nature with these two works is still unanswered.
Abstract—This paper proposes a variable sampling frequency model predictive control (VSF-MPC) to achieve fixed-switching frequency operation for a neutral-point clamped (NPC) inverter. The proposed control technique simultaneously considers load current control, balancing of DC-link capacitor voltages, mitigation of common-mode voltage, and elimination of evenorder and inter-harmonics in the load current harmonic spectrum, while maintaining fixed-switching frequency operation. The challenges associated with weighting factor design are also addressed. Through the simulation and experimental tests on an NPC inverter, it has been demonstrated that the proposed method preserves high dynamic response nature of MPC, and predefined harmonic spectrum characteristic of classical space vector modulation.
This work aims to solve the challenges associated with FCS-MPC such as spread spectrum and variable switching frequency by introducing variable sampling frequency (VSF) concept. This method uses an auxiliary algorithm to calculate the number sampling points to be used in the main predictive control algorithm. This approach combines the working principles of FCS-MPC and space vector modulation (SVM) to achieve high dynamic performances as in FCS-MPC and fixed switching frequency operation as in SVM, for a given set of operating conditions. The proposed control strategy is yet simple and intuitive similar to FCS-MPC. In addition to obtaining predefined spectrum shape, this work proposes evenorder harmonic elimination and common-mode voltage (CMV) mitigation. To verify the feasibility of the proposed control scheme, a neutral-point clamped (NPC) inverter is considered as a case study, and this approach can be easily extended to other power converter configurations. The NPC inverter presents more challenges compared to a standard two-level voltage source inverter. The NPC inverter needs to maintain constant DC-link capacitor voltages in addition to excellent load current regulation [6]. In order to validate the proposed method, simulation and preliminary experimental results are presented using resistive-inductive (RL) load case.
Keywords—Common-mode voltage, current control, DC-AC power conversion, DC-link voltage balancing, digital control, finite control-set model predictive control (FCS-MPC), neutralpoint clamped (NPC) inverter, variable sampling frequency (VSF), spectrum shaping.
I.
I NTRODUCTION
The finite control-set model predictive control (FCS-MPC) emerged as a new and promising approach to control the power converters with good steady-state and dynamic performance [1]. The FCS-MPC uses the model of converter, parameters of the system, and feedback variables, and selects an optimal switching state (signals) based on the minimization of the cost function during each sampling period [2]. Due to unsynchronized sampling between the measurements and output reference fundamental frequency (f ∗ ), the chosen switching states for predicted cost function values within the period of one fundamental cycle vary compared to the selected switching states in the preceding cycle. Thus this control strategy leads to variable switching frequency operation and wide harmonic spectrum [3]. These two characteristics cause difficulty in the design and operation of power converters and harmonic filters, and also cause harmonic oscillations in particular power converter configurations. The deadbeat predictive control provides fixed switching frequency operation, however its dynamic performance is inferior compared to the FCSMPC.
II.
To facilitate the design of MPC for NPC inverter with RL load, it is important to obtain the discrete-time model of the overall power conversion system. The variables to be controlled with the NPC inverter are load current, DC-link capacitor voltages, and CMV. In this section, the model of these three variables is presented with respect to the previously published works on NPC inverters [7]–[9].
The concept of achieving fixed-switching frequency with FCS-MPC, while maintaining good dynamic performance is a well-known challenge in this field. The work in [4] proposed preliminary study on using discrete Fourier transform
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M ODEL OF NPC I NVERTER
The NPC inverter is most popularly used in medium voltage (MV) power conversion applications. A three-phase NPC inverter is composed of 12 active switches and 6 clamping diodes [7]. The DC-link consists of two capacitors, C1 and C2 , and ideally they share equal voltages (vC1 = vC2 = vdc /2). The
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vdc represents the total (net) DC-bus voltage. The continuoustime model of load currents is given as [2]:
switching signals for the NPC inverter during each sampling interval leads to accurate control of load currents, zero CMV and DC-link capacitor voltages simultaneously. The following section describes the control strategy which performs such control actions during each sampling interval.
d i(t) 1 = [v(t) − R i(t)] (1) dt L where, R and L represent the load resistance and inductance, respectively. Furthermore, i and v represent the load currents and inverter voltage vectors, respectively as demonstrated below: i = [ia
ib
T
ic ] ,
v = [van
vbn
T
vcn ] .
III.
P ROPOSED C ONTROL S TRATEGY
The classical FCS-MPC does not comply to any predefined patterns as it has been conceived with the idea of freedom for the controller to select the best switching state that minimizes the cost function. When the fixed harmonic profile term is added to the cost function [4], [5], the overall performance of power converter deteriorates due to the assigned relative importance of sub-cost functions. In order to solve this issue, a novel VSF-MPC scheme is proposed in this paper, and its generic block diagram is shown in Fig. 1.
(2)
With respect to the load neutral n, the NPC inverter voltages are represented in terms of DC-link capacitor voltages and switching signals as [8]: ⎤ ⎡ 2 1 1
sa1 sa2 van 3 −3 −3 ⎢ 1 2 1⎥ vbn = ⎣ − 3 3 − 3 ⎦ vC1 sb1 + vC2 sb2 (3) vcn sc1 sc2 − 31 − 31 23 where, sa1 , sb1 , sc1 , sa2 , sb2 and sc2 are the switching signals applied to the NPC inverter. By using forward-Euler approximation method, the continuous-time load current model in (1) can be converted to discrete-time domain as [2],
Ts R Ts p i (k + 1) = 1 − (4) i(k) + vp (k) L L
Figure 1: Proposed variable-sampling frequency MPC algorithm.
where Ts is control sampling-time, and the superscript “p” represents the predicted variable. The prediction of inverter voltages, vp (k) with the help of (3) leads to the prediction of future values of the load currents.
The proposed method achieves fixed harmonic profile using auxiliary control methods, and not by the cost function. The backbone of presented idea is to sample the data and perform actions at the specific rate in synchronization with the required output frequency, which makes sampling frequency an integer multiple of the fundamental frequency. Also, the reference current is generated at the same sampling rate. Furthermore, the specific number of samples (Ns ) has to be found which secures required harmonic spectrum [10]. The optimal Ns combined with imposed restrictions on the availability of voltage vectors (depending on the position of the reference voltage vector) based on space vector modulation (SVM), limits the options for MPC scheme. As a result, the complete control over the switching pattern has been established so as to achieve high quality harmonic spectrum. Moreover, elimination of unwanted even-order and inter harmonics is easily obtained by an auxiliary algorithm.
The NPC inverter CMV is calculated as, p (k) = vcm
van (k) + vbn (k) + vcn (k) . 3
(5)
Similarly, the discrete-time model of DC-link capacitor voltages is given as [7], ⎫ Ts p p ⎪ i (k + 1) = vC1 (k) + C (k) vC1 ⎪ ⎬ C1 1 (6) ⎪ ⎪ Ts p p ⎭ vC2 (k + 1) = vC2 (k) + C2 iC2 (k) p p where, C1 and C2 are DC-link capacitors. iC1 and iC2 are predicted DC-link currents flowing through C1 and C2 , respectively. The DC-link currents are related to the load currents and NPC inverter switching signals as [9], ⎫ p iC1 (k) = ka1 ia (k) + kb1 ib (k) + kc1 ic (k) ⎬ (7) p (k) = ka2 ia (k) + kb2 ib (k) + kc2 ic (k) ⎭ iC2
The MPC main control block in Fig. 1 contains standard FCS-MPC algorithm which is the converter controlling block. The proposed control approach incorporates a new block called virtual system simulator (VSS). The main function of this block is to simulate the inverter and its load configuration to determine the appropriate sampling frequency based on the simulated waveforms and their harmonic spectra. The simulator uses MPC internally to develop the data based on the harmonics to be eliminated. It is enough to develop the data for one fundamental cycle. The simulator is implemented as a complex C function in the control loop for the FSCMPC. The internal structure of the proposed VSS algorithm is presented in Fig. 2. VSS consist of two sections: an auxiliary model predictive control (AMPC) running at the specific sampling rate, controlled by the sampling frequency shifter
where, ka1 , kb1 , kc1 , ka2 , kb2 and kc2 are the variables which are computed online according to the voltage level (or switching signals) of the NPC inverter [9]. The prediction of DC-link currents in (7) through the switching signals leads to the prediction of future values of DC-link capacitor voltages in (6). The models in (3)–(7) depict that the future values of the predicted load currents, CMV, and DC-link capacitor voltages are related to the switching signals. The proper selection of the
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The expressions in (9) to (11) need angle θ which is obtained from αβ-frame coordinates and it is calculated during each sample period Ts . The above expressions are used to calculate the distance from the origin to any point on the sides (lines) of triangle 3. The length of the reference vector is then compared with the calculated distance to determine its position. For instance, if the intensity (length) of the vector is less than the distance from the origin to the point on x3a -side for the given θ , V ∗ is located in region 1. If the intensity is higher than x3a and if θ is less than 30◦ , then expression (10) is used to calculate the dot on x3b -side line to determine whether the vector is located in region 3 or 2. If the length of V ∗ is higher than the calculated distance, V ∗ is located in region 2. If it is less, it is positioned in region 3. The same principle is used for determining the position in regions 3 and 4.
Figure 2: Proposed architecture of virtual system simulator.
and a waveform plotter running at much higher frequency, Tsp . To provide a satisfying resolution for the waveforms, a higher frequency is required for the plotter in comparison to the frequency of AMPC. A standard discretized model of the system is used in the AMPC, whereas the plotter uses time domain differential equations of the system.
Only selected adjacent vectors will further be allowed and used by the AMPC. The sampling frequency shifter starts from previously used sampling frequency and sets the new value for AMPC. For different sets of reference current and output frequency values, the same Ns value cannot ensure fixed-switching frequency operation. Therefore, Ns should be recalculated according to changes in the operating conditions. The correct synchronization requires Ns to be the same integer value in each of the 6 sectors. Therefore, the sampling frequency can be obtained through the following equation:
Upon giving new reference values to the control scheme, the VSS block determines the appropriate sampling frequency. The algorithm starts by determining the position of the reference vector in order to calculate the nearest three vectors, according to SVM principle, as presented in Fig. 3. The intensity of the vector, in other words, the location of the peak is calculated based on the following expression: vdc √ (8) V ∗ = I∗ IB 6
fsam = ffun ∗ 6 ∗ Ns .
where, I ∗ is the rms reference current, and IB is the rms base current. Based on the intensity of the reference vector and angular distance from the x-axis, it is possible to find out its exact position, i.e. the region that the reference vector is located in. All the lengths in Fig. 3 are assumed to be multiplied by vdc , but for the sake of simplicity the multiplication is not pictured in the figure. By using trigonometry expressions, the following dynamic models are derived:
In the next step the AMPC algorithm is executed to minimize the cost function and determine the states of the switches. The obtained optimum switching states are subsequently delivered to the waveform plotter for the simulation of current waveforms. The plotter uses load equations in time domain to form load currents ia , ib and ic , according to
R Tsp v(k) v(k) − − i(k) e− L (13) iv (k) = R R
√
x3a
vdc 63 = sin 2π 3 −θ
x3b
vdc 63 = sin π3 − θ
(9)
where i(k) is the initial condition that has to be known and calculated with respect to voltage vectors change, and v(k) is calculated according to (3).
(10)
This part of the algorithm repeats itself until enough data points are obtained for the execution of pattern and harmonics verification. First stage is to run the pattern verification on the obtained switching vectors. If the test passed, the Discrete Fast Fourier Transform (DFFT) will be done to extract the harmonics of interest. If the switching pattern exists but was formed in such a way that certain unwanted harmonics appear in the spectrum or if the spectrum does not exist at all for the given sampling rate, the computation continues while sampling frequency is either shifted up or down, depending on the configuration of VSS. The process repeats until the correct sampling frequency is obtained and the desired harmonics are removed from the spectrum. Once the value of fsam is known, the algorithm will automatically change the sampling frequency of main MPC to the calculated value. It is assumed that the entire calculation time for VSS will be less than one sampling period Ts . That way, the converter will always operate with a presumed switching pattern and the dynamics of the system are preserved.
√
√
x3c
vdc 63 = sin (θ)
(a) Division of sectors and regions
(12)
(11)
(b) Regions 1 to 4 in Sector I
Figure 3: SVM diagram
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Once the switching pattern was established and since Ts is constant for a certain operating conditions, the switching frequency can be controlled by sorting P/N/O states of the small vectors. This method provides an option to differently utilize the redundant states, which will only result in magnitude change of the capacitor voltage ripple. The effect on current waveform in terms of THD is marginal, since redundant states are controlled outside of cost function. In other words, the DClink voltages control becomes decoupled from the load current control.
Figure 4: Algorithm for P/N/O states sorting Figure 5: Switching frequency reduction from 1050 Hz to 700 Hz by switching from auto λ balancing to given P/O/N states: 0.4 pu inverter current (upper), DC-link voltages (middle), and NPC output voltage with respect to DC-bus mid-point, vaZ (lower).
The algorithm for P/N/O states sorting consists of five stages. Once the pattern is defined by the VSS it can undergo redundant state arrangement to obtain the desired switching frequency versus DC-link voltage ripple. The operating principle is presented in Fig. 4. In a first stage it is required to detect Ns that was decided by the control. The next stage is to choose how many identical states, P or N, can appear in a row before breaking the series. At least 2 same states have to stand next to each other in order to minimize the switching frequency. In the next step the sequence inverses in order to be applied in the forthcoming sector. The average switching frequency is calculated to check if the pattern with newly sorted stages satisfies the switching frequency criterion. In addition to obtaining predefined spectrum shape, this work proposes even-order harmonic elimination and CMV mitigation. Finally, the cost function considers the load current tracking, balancing of capacitor voltages and CMV mitigation through the weighting factors λdc and λcm as defined below: g(k) = |i∗ (k + 1) − ip (k + 1)|+ (14) p p p + λdc |vC1 (k + 1) − vC2 (k + 1)| + λcm |vcm (k)| IV.
Figure 6: Common-mode voltage elimination through cost function minimization with switch frequency reduction from 1050 Hz to 600 Hz: 0.4 pu inverter current (upper), DC-link voltages (middle), and common-mode voltage (lower).
S IMULATION R ESULTS
To validate the proposed control scheme, a MATLAB/Simulink model of three-phase NPC inverter with the following parameters has been developed: vdc = 10784 V, C1 = C2 = 1000 μF, R = 10.4 Ω, L = 16 mH, f = 50 Hz. In order to verify the fixed-switching frequency operation of NPC inverter, the weighting factor λdc was changed from 0.01 to 0 at t = 0.03 s as illustrated in Fig. 5. The auxiliary algorithm chooses P/O/N states such that the capacitor voltages are balanced even though the cost function omits this task. Due to the transfer of capacitor voltages balancing to the auxiliary controller, the switching frequency, fsw changed from 1050 Hz to 700 Hz, and this can be noticed by looking into the inverter output voltage waveform with respect to the mid-point of DC-bus (vaZ ). The ripple in the capacitor voltages is also increased; however their mean value is equal to half the total DC-bus voltage. The ripple in the load current waveform is not affected by this phenomenon, because the overall control scheme forces the load current to follow predefined harmonic profile. This test verifies the fixed switching frequency operation for the NPC inverter.
rithm in NPC inverter CMV mitigation and also simultaneous elimination of even-order harmonics. The inverter is initially running with a switching frequency of 1050 Hz, and the cost function considers the load current control and balancing of capacitor voltages. At t = 0.035 s, the weighting factor λcm was changed from 0 to 0.1, making the CMV zero by choosing only medium and zero voltage vectors. As a consequence, the switching frequency of the inverter decreases to 600 Hz. Due to the use of medium and zero vectors only, the load current THD has increased slightly. However, the current ripple shape is still symmetrical to eliminate the even-order harmonics and inter-harmonics. The harmonic spectrum of load current waveforms before and after the introduction of λcm into the cost function are shown in Figs. 7 and 8, respectively. The load current follows the predefined harmonic profile and thus the evenorder and inter-harmonics are eliminated completely despite the changes to λcm value. This test verifies the effectiveness of the proposed scheme in eliminating even-order harmonics and CMV simultaneously.
Fig. 6 shows the effectiveness of the proposed control algo-
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Figure 7: Harmonic spectrum of load current with λcm = 0.
Figure 10: Ns versus inverter switching frequency targeting Ns = 14.
VSF-MPC forcing constant sampling rate, where Ns was targeted for 14. The cost function in this case includes load regulation term and capacitor voltage balancing through λdc . At certain operating points, the requested sampling frequency cannot provide either even-order harmonic elimination or fixed switching frequency operation. Thus, the sampling rate is changed by the VSS to first nearby sampling frequency at which primary control objective can be achieved. Ns could either increase (dashed line) or decrease (dotted line) depending on the VSS settings. The increase in Ns would naturally raise the inverter switching frequency while lowering Ns will decrease fsw .
Figure 8: Harmonic spectrum of load current with λcm = 0.1.
Fig. 9 verifies the dynamic response of the control and its ability to precisely follow the current reference while dynamically recalculating and assigning the new sampling frequency. The cost function in this case considers load current control and balancing of capacitor voltages. To simulate the control behavior, the reference current was changed from 0.4 pu to 0.8 pu at t = 0.035 s . A fast dynamic response for load current is observed. The fixed switching frequency operation with new operating conditions was established 10.6 ms after current step change with even-order harmonic elimination from load current. The capacitor voltages are properly balanced after transient conditions. This test verifies the dynamic capabilities and fixed switching frequency of the proposed control scheme.
Figure 11: Ns versus inverter switching frequency targeting fsw = 1000 Hz. Figure 9: Simulation waveforms for load current and DC-link voltages during a step-change in reference current.
On the other hand, Fig. 11 presents the control behavior when the inverter switching frequency was targeted for 1000 Hz within the allowed range of ± 10 % of fluctuation around the targeted value. The VSS is configured to automatically adjust the sampling rate to meet the requested criterion while maintaining fixed switching frequency with even-order har-
It is known that the inverter switching frequency changes with load current ranging from low to high values. In classical fixed sampling frequency FSC-MPC, the inverter switching frequency varies with load current. Fig. 10 shows the proposed
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monic elimination. Figs. 10 and 11 show the flexibility of the proposed control scheme to fulfill various objectives and simultaneously shape the harmonic spectrum. V.
VI.
C ONCLUSION
This paper proposes a variable sampling frequency model predictive control to achieve fixed-switching frequency operation for the NPC inverter. The complete elimination of even-order harmonics and inter-harmonics in the load current spectrum has been achieved. Another important feature of the proposed control strategy is to arrange small vectors automatically through an auxiliary algorithm such that DClink capacitor voltages and inverter switching frequency can be controlled independently without defining these objectives in the cost function. This leads to a cost function with less control terms involved, and thus the problems associated with the weighting factor design are mitigated. Moreover, inclusions of only current tracking in cost function produces less error in reference tracking and lower load current THD. The commonmode voltage elimination in NPC inverter was also verified, and this has been achieved without altering the predefined harmonic profile. The proposed scheme has been verified by simulation and preliminary experimental tests.
E XPERIMENTAL R ESULTS
The proposed control scheme has been experimentally verified preliminarily with the laboratory NPC inverter prototype with the following parameters: vdc = 150 V, C1 = C2 = 1000 μF, R = 9.8 Ω, L = 7.5 mH, f = 60 Hz. The prototype is controlled by a dSPACE DS1103 board. The experimental waveforms for NPC inverter line-to-line voltage and phase current are illustrated in Figs. 12 and 13, respectively with Ns = 14. It has been verified that the switching frequency is constant for the given operating condition, and the current waveform is half-way symmetrical proving even-order harmonic elimination.
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Figure 12: Experimental waveform for NPC inverter line-to-line voltage.
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Figure 13: Experimental waveform for NPC inverter phase current.
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