Modeling and Simulation of Single Electron Systems ...

Minia University Faculty of Engineering Electrical Engineering Dept.

Modeling and Simulation of Single Electron Systems for Nanoelectronic Applications

A Thesis Submitted in Partial Fulfillment of the Requirement for the Degree of Master of Science In Electrical Engineering

By

Eng. Mohamed Gamal Ahmed Mohamed B.Sc. in Electrical Engineering (Communication and Electronics) Demonstrator in Electrical Engineering Department Faculty of Engineering, Minia University

Under the Supervision of Prof. Dr. Mohamed Ahamed Abdel Wahab Dr. ElSayed Abd ElHameed Mahmoud Hasaneen Electrical Engineering Department Faculty of Engineering, Minia University El‐Minia, Egypt

2009

Acknowledgments

Acknowledgements By the name of Allah most merciful, most gracious All prayers of gratefulness and acknowledgement to the messenger of Allah I would to express my sincere appreciation and gratitude to my supervisors Prof. Dr. Mohamed A. A. Wahab Dr. ElSayed A. M. Hasaneen for their academic and moral support and encouragement during the preparation of this thesis. Their unlimited wise advice guided me all the way. Special thanks to my parents. Without their encouragement, I could not continue through my life and studies. At last, I dedicated this piece of work to my parents wishing they feel satisfaction toward me.

Eng. Mohamed Gamal Ahmed

I

2009

Abstract

Abstract Motivated by the merits of low power dissipation, ultra small size and high speed, many nanoelectronic devices have been demonstrated to ensure future progress. Single electron devices become one of the most important nanoelectronic devices due to their interesting electrical characteristics and behavior. Many research efforts moved to describe their electrical characteristics to use them with conventional electronic devices. Therefore, this thesis deals with modeling and simulation of such new electronic devices. This thesis starts with describing single electron phenomena and discussing the most important theory (orthodox theory of single electronics) used in explanation of single electron devices behavior. With the aid of orthodox theory and the basic idea of electron transport through tunnel junctions, we present an equivalent circuit model for single electron tunneling junction (SETJ) taking into consideration the effect of temperature, tunneling resistance and junction capacitance. This model is validated by comparing its results with well known single electron simulator SIMON in two simple standard circuits (electron box and current biased tunnel junction). This thesis also presents a study about different modeling techniques (Master equation and Monte Carlo algorithm) for single electron systems and the usage of these techniques to develop models for most widespread single electron devices. By applying these techniques in order to model the most used single electron device (single electron transistor (SET)), one can find that master equation gives better accuracy

II

Abstract

than Monte Carlo algorithm and takes less simulation time. Thereafter, many research efforts have been done to develop accurate models for SET using these techniques. These models take limited conditions in SET modeling to avoid numerical solution which cannot be implemented in SPICE simulators. A new developed model for SET is also presented. This model is accurate for large range of bias voltage with any type of biasing. It takes the effect of background charges. It is implemented on SPICE to enable simulation with other electronic components like MOS devices. It is validated with comparing the results of symmetric and asymmetric SET device characteristics with SIMON simulator. Finally, some single electron circuits are studied and simulated using our proposed model. These circuits are single electron inverter, NAND and OR gates.

III

Table of Contents

Table of Contents Acknowledgements ............................................................................................................. I Abstract .................................................................................................................................. II Table of Contents ............................................................................................................... IV List of Figures .................................................................................................................... VII List of Symbols ...................................................................................................................... X Chapter 1 Introduction ..................................................................................................... 1 1.1 Scope of the present thesis .................................................................................. 2 Chapter 2 Single‐Electronics Overview ..................................................................... 5 2.1 Introduction ............................................................................................................... 5 2.2 Basic physics and scaling ...................................................................................... 5 2.3 Observation of Coulomb blockade oscillation ............................................. 7 2.3.1 Electron box circuit .......................................................................................... 8 2.3.2 Current biased tunnel junction ................................................................... 9 2.4 Orthodox theory .................................................................................................... 10 2.5 Single electron devices ....................................................................................... 13 2.5.1 Single electron transistor ........................................................................... 13 2.5.2 Single electron turnstile ............................................................................. 14 2.5.3 Single electron pump ................................................................................... 14 2.5.4 Single electron array .................................................................................... 15 2.6 Applications of single electron devices ....................................................... 15 2.6.1 Electrometer .................................................................................................... 15 IV

Table of Contents

2.6.2 Single electron memory .............................................................................. 16 2.7 Design issues ........................................................................................................... 17 2.7.1 Top‐down design issues ............................................................................. 17 2.7.2 Bottom‐up design issues ............................................................................ 17 2.8 Summary ................................................................................................................... 18 Chapter 3 Literature Review ....................................................................................... 19 3.1 Introduction ............................................................................................................ 19 3.2 Basics of single‐electronics ............................................................................... 19 3.3 Modeling and simulation techniques ........................................................... 21 3.4 Modeling of single electron tunnel junction .............................................. 22 3.5 Modeling of single electron transistor ......................................................... 23 3.6 Summary ................................................................................................................... 27 Chapter 4 Equivalent Circuit Model for Single Electron Tunneling Junction ................................................................................................................................. 28 4.1 Introduction ............................................................................................................ 28 4.2 Single electron tunneling junction model ................................................... 29 4.3 Proposed SETJ circuit simulation model ..................................................... 31 4.4 Simulation results ................................................................................................. 33 4.5 Summary ................................................................................................................... 37 Chapter 5 Single Electron Circuit Simulation Methods .................................... 38 5.1 Introduction ............................................................................................................ 38 5.2 Free energy of an arbitrary circuit ................................................................ 39 5.2.1 Notation ............................................................................................................. 39

V

Table of Contents

5.2.2 Electrostatic energy ...................................................................................... 41 5.3 Master equation method .................................................................................... 43 5.4 Monte Carlo Method ............................................................................................ 47 5.5 Summary ................................................................................................................... 48 Chapter 6 Modeling and Simulation of Single Electron Transistor ............. 50 6.1 Single electron structure and operation ..................................................... 50 6.2 Single electron transistor modeling .............................................................. 58 6.2.1 Master equation ............................................................................................. 58 6.2.2 Monte Carlo Algorithm ................................................................................ 64 6.3 Developed model ................................................................................................... 68 6.3.1 Simulation Results ........................................................................................ 76 6.4 Summary ................................................................................................................... 81 Chapter 7 Single electron Circuits Simulations ................................................... 82 7.1 Introduction ............................................................................................................ 82 7.2 Logic Inverter ......................................................................................................... 82 7.3 Logic NAND Gate ................................................................................................... 85 7.4 Logic OR Gate .......................................................................................................... 87 Chapter 8 Conclusions .................................................................................................... 90 8.1 Conclusions .............................................................................................................. 90 8.2 Recommendations for future work ............................................................... 92 References ........................................................................................................................... 93 VI

List of Figures

List of Figures Figure (2.1)

Page

a) An electron approaching a small uncharged metallic sphere will feel a small attractive force caused by its own image charge in the sphere. b) Once the sphere is charged by a single electron, following electrons will feel a strong repelling Coulomb force.

6

Single electron tunnel junction. a) A structure. b) A schematic diagram.

7

(2.3)

Two tunnel junctions. a) A structure. b) A schematic diagram.

8

(2.4)

An electron box can be filled with a precise number of excess electrons by raising the bias voltage V above the threshold voltage V . a) Electron box construction. b) Electron box circuit. c) Coulomb staircase.

9

Current biased tunnel junction showing Coulomb fluctuations. a) Circuit diagram. b) Current as a function of time.

10

(2.6)

Single electron transistor. a) A structure. b) A schematic diagram.

13

(2.7)

Schematic diagram of single electron turnstile.

14

(2.8)

Schematic of the simplest single electron pump.

15

(4.1)

The junction impulse model.

31

(4.2)

Impulse current passing through the junction within tunneling event.

31

(4.3)

The SPICE SETJ model.

32

(4.4)

Current‐biased SETJ.

33

(4.5)

Simulation results for current biased SETJ compared with single electron simulator SIMON, where IS = 1 µA, Cj = 1 aF.

34

The voltage over SETJ as a function of time at different junction capacitances, where IS = 1 µA, RT = 1 M.

34

The voltage over SETJ as a function of time at current biased SETJ with different tunneling resistances, where IS = 1 µA, Cj = 4 aF.

35

Electron box circuit.

36

(2.2)

(2.5)

(4.6) (4.7) (4.8)

VII

List of Figures

(4.9)

Simulation results for electron box circuit compared with single electron simulator SIMON, where Cj = 1 aF, Ccap = 9 aF, RT =1 MΩ.

36

The voltage over SETJ as a function of time at electron box circuit with different tunneling resistances, where Cj = 1 aF, Ccap = 9 aF.

37

Single electron circuit consisting of tunnel junctions, capacitors, and voltage sources and showing different types of nodes.

40

A macro‐node is formed by a set of voltage sources which are not connected to ground.

42

State transition diagram for a jump process with discrete states ( 5).

44

(5.4)

State transition diagram of a birth‐death process.

46

(5.5)

State transition diagram of a Poisson process.

46

(6.1)

A schematic diagram of single electron transistor.

50

(6.2)

Diagram of tunneling rates for the movement of an electron through single electron transistor.

51

(6.3)

Stability plot diagram for single electron transistor.

55

(6.4)

Symmetric SET characteristics. a) characteristics. b) characteristics. The SET device parameters are ( = = 1 aF, = 2 aF, = = 1 MΩ, T =1 K) biased under symmetric bias voltage condition.

56

Asymmetric SET characteristics. a) characteristics. b) characteristics. The SET device parameters are ( = = 1 aF, = 2 aF, = 3 MΩ, = 100 kΩ, T = 1 K) biased under symmetric bias voltage condition.

57

(6.6)

Flow diagram for master equation algorithm.

62

(6.7)

Simulation results from applying master equation method on symmetric SET for a) 5 states. b) 9 states. The SET device parameters are ( = = = 1 aF, = = 100 kΩ, T = 1 K) biased under symmetric bias voltage condition.

63

Simulation results from applying Monte Carlo algorithm on symmetric SET for a) 50 random values. b) 500 random values. The SET device parameters are (CD = CS = CG = 1 aF, RD = RS = 100 kΩ, T = 1 K) biased under symmetric bias voltage condition.

66

(4.10) (5.1) (5.2) (5.3)

(6.5)

(6.8)

VIII

List of Figures

(6.9)

Simulation results from applying Monte Carlo algorithm on symmetric SET for a) 5000 random values. b) 20000 random values. The SET device parameters are (CD = CS = CG = 1 aF, RD = RS = 100 kΩ, T = 1 K) biased under symmetric bias voltage condition.

67

a) 3D pattern for drain current characteristics with VDS and VGS under steady state conditions and asymmetric bias voltage. b) Probabilities of the most probable states under asymmetric bias voltage.

69

a) 3D pattern for drain current characteristics with VDS and VGS under steady state conditions and symmetric bias voltage. b) Probabilities of the most probable states under symmetric bias voltage.

71

(6.12)

Simplified flow chart for our developed model for SET.

75

(6.13)

Verification of our model on IDVDS characteristics at certain voltage of VGS for symmetric device (CD = CS = 1 aF, CG = 1 aF, RD = RS = 1 MΩ) (line: SIMON, + symbol: our model). a) With symmetric bias voltage. b) With asymmetric bias voltage.

77

Verification of our model on IDVGS characteristics at certain voltage of VDS for symmetric device (CD = CS = 1 aF, CG = 1 aF, RD = RS = 1 MΩ) (line: SIMON, + symbol: our model). a) With symmetric bias voltage. b) With asymmetric bias voltage.

78

Verification of our model on IDVDS characteristics at certain voltage of VGS for asymmetric device (CD = 1 aF, CS = 3 aF, CG = 2 aF, RD = 1 MΩ, RS = 2 MΩ) (line: SIMON, + symbol: our model). a) With symmetric bias voltage. b) With asymmetric bias voltage.

79

Verification of our model on IDVGS characteristics at certain voltage of VDS for asymmetric device (CD = 1 aF, CS = 3 aF, CG = 2 aF, RD = 1 MΩ, RS = 2 MΩ) (line: SIMON, + symbol: our model). (a) With symmetric bias voltage. (b) With asymmetric bias voltage.

80

(7.1)

A schematic diagram of a single electron inverter.

83

(7.2)

The input‐output characteristics of the inverter calculated at 4.2K, 27K, and 77K. The simulations performed with SPICE (symbols) are compared with the ones performed with a conventional Monte Carlo simulation program SIMON (lines).

84

(7.3)

SET NAND schematic diagram.

86

(7.4)

Voltage transfer characteristics for a NAND SET.

87

(7.5)

SET OR schematic diagram.

88

(7.6)

Voltage transfer characteristics for OR SET.

89

(6.10)

(6.11)

(6.14)

(6.15)

(6.16)

IX

List of Symbols

List of Symbols Symbol Description Unit that denotes to atto‐farad which equal 10‐18 farad

Γ

Tunnel rate through tunnel junction

Γ

Rate matrix

Γ

The transition rate for drain/source tunnel junction in forward/backward direction

,

The transition rate from state to state

Γ Γ |

The transition rate from state to state Capacitance

Capacitance matrix

Capacitance of the adjacent capacitor to tunnel junction in electron box circuit

Drain tunnel junction capacitance

The replacement capacitance that equals the equivalent circuit capacitance

The total capacitance of the conductor

Element of the capacitance matrix which denotes to the capacitance between conductor and

The junction capacitance

Source tunnel junction capacitance

The summation of all capacitances

Time delay

Very small period of time representing the pulse width Impulse function shifted to

Electron Charge

Electrostatic Energy Frequency

X

List of Symbols

Free energy

A function that rounds the number to the nearest integer less than or

equal

Planck’s constant

Current

Boltzmann’s constant

Number of states

Number of electrons in the island (state)

Number conductors

Number of charge‐nodes

Number of floating‐nodes

Number of floating nodes in a macro‐node

Number of macro‐nodes

Number of all nodes except ground node

The optimum number of electrons in the island

Number of potential‐nodes

State probability vector

State probability vector at

0

,

Probability of state 0 at time

0 0

Probability coefficient

The time dependent occupation probability of state

Probability density function in state space The vector of node charges

The transpose of the vector of node charges

Average charge on the junction capacitance

Background charge

Charge vector of charge nodes

The transpose of charge vector of charge nodes

The charge of the floating node in the macro‐node

The total charge of the macro‐node XI

List of Symbols

The charge on any conductor

,

Charge vector of potential and floating nodes

,

The transpose of charge vector of potential and floating nodes Random numbers

r

Drain tunnel resistance

Source tunnel resistance

Tunneling Resistance Time of the tunnel event

τ

Absolute temperature

Electrostatic energy

the vector on node voltages

Voltage of the island

Voltage difference between nodes 1,2

Critical voltage

Drain voltage

Drain – Source voltage

Gate voltage

Gate – Source voltage Potential of node after change

́

Potential of node

Tunnel junction voltage

Source voltage

Threshold Voltage

The work done by the voltage sources

Potential vector of charge nodes

,

Potential vector of potential and floating nodes

,

The transpose of potential vector of potential and floating nodes Potential of a potential node or floating node from which an electron

,

tunnels

,

Potential of a potential node or floating node to which an electron tunnels

XII

List of Symbols

Change in electrostatic energy

Δ ∆

The reduction of the free energy of drain tunnel junction in forward/backward direction

∆

The reduction of the free energy of source tunnel junction in forward/backward direction

∆

Change in free energy

∆

Change in electrostatic energy

XIII

Chapter 1 – Introduction

Chapter 1 Introduction MOSFET device has been the predominant technology during the past three decades for semiconductor industry. The advancement of IC industry is largely driven by technology of MOS transistor minimization which is called MOSFET scaling down. Going to high speed devices and low power consumption makes the scaling down of circuit dimensions of very new technology is one of the most important topics of the semiconductor industry. Nowadays, MOSFET scaling down nearly reaches its limit of miniaturization because of some non ideal effects that change the well known characteristics of MOSFET. Single‐electronics comes to replace the predominant CMOS technology. This technology has many benefits and great figure of merits such as very small size, low power consumption, and high speed. Single‐ electronics reveals new physical effects of charge transport. It implies the possibility to control the movement and position of electron or a small number of electrons. However, it has several open challenges waiting for elegant solutions. Single electron tunneling devices have the problems of high output impedance, high sensitive to background charges and low voltage gain. There is a solution for these problems by using hybrid technology (single electron technology with CMOS technology). Thus, there is a growing need for models of single electron tunneling devices to precisely determine its performance. From the beginning of the last decade to nowadays, there was a steady rise in published work in this area. Several sophisticated numerical 1


simulators (i.e. SIMON [1], KOSEC [2], SECS [3], and MOSES [4]) were developed to precise model single electron systems. These simulators are accurate but they cannot be used in circuit simulators with other electronic components and usually extremely time consuming when the simulation involves high temperature operation, current biased single electron device, or any single electron circuit including a resistance [5]. Therefore, SPICE models for single electron devices are needed to enable simulation with other electronic components. The smallest element in single electron devices is the tunnel junction. All single electron devices consist of tunnel junctions connected to capacitors or resistors. So many researchers tried to model these tunnel junctions thinking that they might describe the operation of all single electron devices. Contrarily, modeling of tunnel junctions cannot describe the operation of single electron devices because of charge sharing between different nodes. Thus, they moved to model the most used single electron devices. Single electron transistor can be considered the most common single electron device because SET is conceptually simple and shows several interesting features in its electrical characteristics. Therefore, many research efforts on developing SPICE models for SET have been proposed [5‐16]. These models enable the integration between CMOS technology and single electron technology.

1.1 Scope of the present thesis This thesis presents simulation techniques used in single‐electronics. It contains a new developed SPICE model for single electron tunnel junction. This model is able to describe the motion of electrons through

2


the tunnel junction. The effect of temperature, tunneling resistance and junction capacitance is included in this model. This thesis also contains a new analytical model for single electron transistor. This model can be implemented in SPICE. It was proved to work with a good accuracy within a large voltage range with any type of biasing. This thesis is divided into eight chapters and list of references. Its organization is as follows: Chapter 2: In this chapter, there is an overview about physics of single‐electronics and its basic operating principles. It also contains an overview about orthodox theory of single‐electronics, different single electron devices, and applications of single electron devices. Design issues for single electron technology are also included. Chapter 3: This chapter gives a literature review about the physics of single‐electronics and the different techniques used in simulation. It also contains a literature review about modeling of single electron tunnel junction and single electron transistor. Chapter 4: This chapter presents the proposed equivalent circuit model for single electron tunnel junction taking into consideration the effect of temperature, tunneling resistance, and junction capacitance. It also presents the validation of the proposed model with well known simulator SIMON. Chapter 5: Different modeling techniques used in simulating single electron devices are presented in this chapter. These techniques are master equation and Monte Carlo algorithm. Chapter 6: In this chapter, SET device construction and characteristics are discussed. Different modeling techniques like Monte Carlo algorithm 3


and master equation are applied to model SET device. A new developed analytical model for SET device is presented in this chapter which can be implemented in SPICE. Finally, the validation of proposed model with SIMON simulator for different SET parameters and different types of biasing are presented in this chapter. Chapter 7: In this chapter, the proposed SET model is used to simulate SET circuits. These circuits are SET inverter, NAND and OR gates. Chapter 8: This chapter presents the main conclusions which have been extracted from the present thesis and also the recommendations for future work.

4

Chapter 2 – Single‐Electronics Overview

Chapter 2 SingleElectronics Overview 2.1 Introduction Single‐electronics implies the possibility to control the movement and position of a single electron or a small number of electrons. Therefore, the current through the device is quantized. Actually, single electron transport appears from investigations on a device known as the tunnel junction, formed by two metal electrodes separated by a thin insulator. According to quantum mechanics, a single electron has a small probability of passing through the thin insulator. This phenomenon is called tunneling. Therefore, in this chapter, there is an overview about physics of single‐ electronics and its basic operating principles. It also contains an overview about orthodox theory of single‐electronics, different single electron devices, and applications of single electron devices. Design issues and different fabrication techniques for single electron technology are also included.

2.2 Basic physics and scaling The fundamental concept behind single electron devices can be explained by considering an uncharged small metallic sphere with a radius 1 nm. Let such a small sphere be initially electro‐neutral “i.e. it has exactly as many electrons as it has protons in its crystal lattice”. If it is charged with a single electron as shown in Fig. (2.1), the electric field on the surface of the sphere in vacuum will become very large because it is 5


Fig. (2.1): a) An electron approaching a small uncharged metallic sphere will feel a small attractive force caused by its own image charge in the sphere. b) Once the sphere is charged by a single electron, following electrons will feel a strong repelling Coulomb force.

inversely proportional to the square of the island size [17]. This electric field results in a remarkably large repelling force for any other electron which wants to approach the sphere. This phenomenon makes it possible to separate a single electron in a solid state structure. To be more precise, a single electron is not isolated, because there are many other electrons in the electron cloud around the metallic sphere. But one single electron has been precisely added to the electrically neutral sphere. Meaning there are a control over single electrons and a manipulation of them with single electron precision. The theory behind single electron phenomenon shows that the associated charging energy

⁄2 for a single electron with charge

e is the adequate measure to describe single electron transfer and related effects. Thus, if the involved capacitances are small enough, charging energies will be dominating.

6


Fig. (2.2): Single electron tunnel junction. a) A structure. b) A schematic diagram.

2.3 Observation of Coulomb blockade oscillation Coulomb blockade oscillations can be observed in charging tunnel junction which is the smallest unit cell in single electron devices. It consists of two electrodes separated by a thin insulator as shown in Fig. (2.2). The only way for electrons to move across the tunnel junction is to tunnel through it. Although tunneling is a probability distribution function, electrons tunnel across the tunnel junction in a discrete manner [18]. Another example to observe Coulomb blockade oscillations is in a Coulomb island which is formed by connecting two tunnel junctions together as shown in Fig. (2.3). No electron can reside on the island unless its kinetic energy exceeds the Coulomb energy of the island which is known as the Coulomb blockade. The conditions which control the movement of electric charge through a conductor are required to be well known to understand single electron transfer. There are free electrons at the atomic nuclei which are free to move through the system. The current through the conductor can be represented by the charge transferred per time. This transferred charge can take any value, in particular, a fraction of the charge of a single electron. Hence, it is not quantized.

7

tio n ul a

metal

ins

ula

island

ins

metal

tio n


(b)

(a)

Fig. (2.3): Two tunnel junctions. a) A structure. b) A schematic diagram.

Placing a tunnel junction in an ordinary conductor restricts the current flow which results in a quantized current. Thus, electric charge will move through the system by both a continuous and a discrete process. Since only discrete electrons can tunnel through junctions, charge will accumulate at the surface of the electrode against the isolating layer, until a high enough bias has built up across the tunnel junction. Then one electron will be transferred by tunneling. Electron box circuit and current biased tunnel junction are the simplest circuits which demonstrate Coulomb blockade oscillation. 2.3.1 Electron box circuit A single electron box [17] can be considered the simplest circuit which exhibits single electron charging effects. The single electron box is not just easy to understand but it is also relatively simple to manufacture and measure in the laboratory. It consists of a metal granule placed in an oxide between two conductors as shown in Fig. (2.4a). The granule is closer to one of the conductors than the other conductor. Thus, this structure can be described as a tunnel junction connected with a capacitor in series as shown in Fig. (2.4b). The top oxide layer is thin enough for electrons to tunnel through because it works as a large 8


q(e)

q

6 5 4

Island

Vb

Vb

3 2

oxide

1 Vb

Vth

(a)

(b)

(c)

Fig. (2.4): An electron box can be filled with a precise number of excess electrons by raising the bias voltage V above the threshold voltage V . a) Electron box construction. b) Electron box circuit. c) Coulomb staircase.

capacitance. To transfer one electron onto the granule, the Coulomb energy

⁄2 has to be taken into account. We must observe that

the only energy source available is the bias voltage and neglecting thermal and other forms of energy. As long as the bias voltage is smaller than a threshold

⁄ , no electron can tunnel because not enough

energy is available to charge the island. This behavior is called the Coulomb blockade. Raising the bias voltage will increase electron population in the granule in a discrete manner, leading to a staircase like characteristics shown in Fig. (2.4c). 2.3.2 Current biased tunnel junction Coulomb blockade oscillation can be observed by biasing a tunnel junction with a constant current source I as in current biased tunnel junction circuit shown in Fig. (2.5a) [19]. The so‐called single electron tunneling oscillations will appear with frequency

⁄ as shown in

Fig. (2.5b). Charges continuously accumulate on the tunnel junction like on a capacitor until it is energetically favorable for an electron to tunnel. This 9


Fig. (2.5): Current biased tunnel junction showing Coulomb fluctuations. a) Circuit diagram. b) Current as a function of time.

discharges the tunnel junction by an elementary charge e. Similar effects are observed in superconductors where charge carriers are copper pairs. ⁄2 , related to the so‐called

The characteristics frequency becomes Bloch oscillations.

2.4 Orthodox theory The orthodox theory [17] describes charge transport under the influence of Coulomb blockade. In order to observe single electron phenomena such as single electron tunneling oscillations and Coulomb blockade, there are two conditions that have to be fulfilled. The first condition confines that the Coulomb energy is higher than thermal energy. Otherwise thermal fluctuations will disturb the motion of electrons and will change the quantization effects in a random fashion. The necessary condition is /2 where

(2.1)

is the Boltzmann’s constant and is the absolute temperature.

From the previous condition, it can be observed that the capacitance C has to be smaller than 3 aF to observe charging effects at room 10


temperature (300 K), which requires a grain with diameter smaller than 1 nm. To use charging effects for deterministic logic, this will require granules below 1 nm diameter for room temperature operation in order to raise the

⁄

ratio to suppress the thermal tail of electrons

overcoming the Coulomb blockade and causing errors [17]. A second condition for the observation of charging effects is that quantum fluctuations of the number of electrons on an island must be negligible in order to make electrons well localized on the islands. This leads to the requirement that all tunnel junctions must be opaque enough for electrons in order to confine them on islands. The opacity of a tunnel which must fulfill the

junction is given by its tunnel resistance

following condition for observing discrete charge effects: ⁄

25813 Ω

(2.2)

where is Planck’s constant. This should be measured as an order of magnitude, rather than an exact threshold. The main result of the theory can be formulated as follows: the tunneling of a single electron through a particular tunnel barrier is always a random event, with a certain rate Γ (i.e. probability per unit time) which depends solely on the reduction of the free electrostatic energy Δ of the system as a result of this tunneling event [20]. The tunnel rate is given by Γ

⁄

(2.3)

The reduction in free energy can be calculated by taking a closer look to the electrostatic energy of a single electron circuit. Consider a system with conductors which has a capacitance matrix . The charge on any conductor can be expressed as [17] 11


∑ where the

1 , 2 , … … ,

(2.4)

denote the elements of the capacitance matrix and the

potential of node . In capacitance matrix, the diagonal elements

are

the total capacitance of the conductor , and the off‐diagonal elements

are the negative capacitances between conductor and . Thus, the electrostatic energy can then be expressed as [17] ∑ where

∑

∑

(2.5)

is the transpose of the vector of node charges, v is the vector of is element of the inverse of the

node voltages, and

capacitance matrix. If the charge configuration changes, node voltages and electrostatic energy will change. The system tunnels from a state of a higher electrostatic energy to a state of lower electrostatic energy. The difference in energy is dissipated as heat. The energy needed to move an electron to node is given by [17]

∆

(2.6)

Consider the case where an electron tunnels from node to node , where the initial voltage on node is and the initial voltage on node is . The change in the energy can be calculated in two stages. The first stage is to remove an electron from node , and the second stage is to add an electron to node . The total change in electrostatic energy [17] will be ∆

∆

∆

⁄2 (2.7)

2

and the change in node voltages can be given by ́

, ́

12

(2.8)


Drain Drain

Gate

Gate

island

Source Source (a)

(b)

Fig. (2.6): Single electron transistor. a) A structure. b) A schematic diagram.

Note that the change in electrostatic energy depends only on the difference in voltage between the initial and final nodes plus a term that is independent of the charge state of the system.

2.5 Single electron devices Single electron box, transistor, turnstile, pump, one and two dimensional array are small devices on their own. They can be considered the fundamental building blocks for more elaborate nanoelectronic circuits. 2.5.1 Single electron transistor Single electron transistor consists of a small island coupled to three electrodes as shown in Fig. (2.6). Source and drain leads are coupled to the island by a high resistance tunnel junction and the gate is capacitively coupled to the island. The SET can be viewed as a single electron box that has two junctions for entry and exit of electrons. This is analogous to a conventional MOSFET which has channels replaced by tunnel junctions (i.e. source and drain regions are connected to island by tunnel 13


Fig. (2.7): Schematic diagram of single electron turnstile.

junctions.). Gate electrode can be used to control number of electrons on the island. 2.5.2 Single electron turnstile Geerligs et al. [21] are the first who suggested the single electron turnstile. The simplest turnstile is similar to SET in its construction except it has four tunnel junctions as shown in Fig. (2.7). At zero bias, an electron can be drawn to the central island by increasing the gate voltage. This electron can enter from left or right according to the gate voltage. But with a bias voltage, the symmetry in its operation can be broken. It makes electrons enter from one side and exit from the other, which means one can realize controlled electron transfer. 2.5.3 Single electron pump Fig. (2.8) shows the schematic diagram of the simplest single electron pump. It resembles single electron turnstile except that it has a gate between each adjacent tunnel junctions, whereas the turnstile usually has a gate after each block of two junctions. Single electron pumps are widely used as a highly accurate current standard and they are used also for logic and memory applications. 14


Fig. (2.8): Schematic of the simplest single electron pump.

2.5.4 Single electron array Linear or one‐dimensional arrays of tunnel junctions resemble single electron transistor and double junction circuit in their characteristics. The resistance of the array is the sum of the tunnel junction resistances. Thus, the assumption of breaking one tunnel junction make the array could not be able to conduct. So, two‐dimensional arrays are more stable because it is composed of a parallel combination of several linear arrays which give more paths for electrons if a tunnel junction is broken.

2.6 Applications of single electron devices Single electron devices have been used in many applications. They are used as charge sensing devices in electrometers or memories. 2.6.1 Electrometer Single electron devices are charge sensing devices. Its operation is strongly affected by random background charge. When a SET is operated above Coulomb blockade threshold it forms an electrometer. Even small amount of background charge can change the Coulomb blockade and thus alter working of the SET device. The advantage of the problem of background charge is that we can build high sensitive electrometers. This 15


change in charge is detected by an island of SET. The SET electrometer can be operated by capacitively coupling external charge source to the gate of SET. For very small changes in the gate voltage there is a large change in source and drain current. This happens due to large amplification coefficient. Schoelkopf et al. [22] have predicted the achievable sensitivity value of 10

⁄√Hz. This sensitivity is much better

than many common electrometers made by MOSFET. With such good sensitivity we can measure very small amounts of charge. High sensitivity can be achieved by increasing gate capacitance but this can reduce Coulomb energy [17]. 2.6.2 Single electron memory It is perhaps one of the interesting applications of SET. It stores information by predicting presence and absence of an electron on an island. Tiwari and Lingjie [23, 24] independently demonstrated single electron memory which stores information in the form of one electron in two different publications. They used gate electrode to inject single electron to island and this can modulate drain‐source current. They fabricated memory element by having one or several nano‐particles embedded in thin layer of silicon dioxide insulator. Finally, source, drain and gate electrodes are fabricated around nano‐particles. Tiwari’s structure demonstrated read/write time of 20ns with a lifetime of more than 109 cycles and can retain information ranging from few days to several weeks. Another way to construct a memory element is by considering 1 bit = 1 electron, then an array of 4‐7 single electron transistors can be used and positions of single electrons in an array will define different memory

16


states [25]. The practical limitation of such a memory is fabrication. If this type of memory is realized, it will be very much advantageous over CMOS. This can be proved to be advantages when time comes for integration of SET to form logic gates.

2.7 Design issues The fundamental design aspect in single‐electronics is that individual electrons will be manipulated instead of currents. This will lead to design complexity. The complexity arises if we realize that we have to cope with, or even to exploit, the typical properties like inaccuracies and stochastic behavior, that inherently go hand in hand with decreasing dimensions. The design complexity has to be tackled from two approaches: a top‐ down structured design and a bottom‐up structured design [26]. 2.7.1 Topdown design issues The top‐down design focuses on the interdependencies of the design choices made at different functional levels. Especially, the application of appropriate signal definition, the choice of what functions at which level to implement and the use of redundancy, adaptively or neural networks are most important nanoelectronic issues. The necessity of a top‐down approach comes from a number of reasons. First there are the uncertainties and inaccuracies caused by quantum effects or just by the imperfection due to the nanofabrication technology. In general, these uncertainties and inaccuracies have to be tackled at different levels in the design. We have the choice to try to avoid them or to cope with them. 2.7.2 Bottomup design issues A design methodology only followed the top‐down approach will result in functional blocks that have to be implemented with nano‐ 17


devices not necessarily exploiting the specific properties of the devices. The choice of functional blocks is based on existing circuit design paradigms that often do not fully take into account the new possibilities of the nanoelectronic devices. Complementary, a bottom‐up approach can exploit from the lowest level capabilities of the nano‐devices. Such an approach can try to use the discrete character of the single electron tunneling process and its stochastic behavior. As it is usually done in a bottom‐up design strategy, we start with the basic physics describing the device. From this level, we are able to propose circuit elements, or equivalent sub‐circuits that approach physical equations in certain domains of signal processing. Those circuit elements and sub‐circuits form the basis for circuit analysis, circuit synthesis and SPICE‐like transient simulation.

2.8 Summary In this chapter, an overview on the basic phenomena of single electron tunneling has been discussed. Orthodox theory of single‐electronics described the charge transport under the influence of Coulomb blockade and gave the conditions needed for observing single electron phenomena such as single electron tunneling oscillations and Coulomb blockade. After taking an overview on orthodox theory, one can conclude that the tunneling phenomena strongly depend on the energy argument in the circuit. Most used single electron devices have been presented showing its simple construction. One can see that the basic element for single electron devices is the single electron tunnel junction. Then, important applications and design issues have also been discussed in this chapter.

18

Chapter 3 – Literature Review

Chapter 3 Literature Review 3.1 Introduction Nowadays, Modeling of single electron devices is one of the important topics that researchers are interested with. Numerical methods were applied to model single electron devices then they were implemented in single electron simulators. These simulators are used to simulate single electron devices only. Thus, many researchers moved toward developing SPICE models to enable simulation with other electronic components. Most of these models were developed from master equation or Monte Carlo algorithm. In this chapter, a literature review of different single electron simulation techniques, modeling of SETJ, and modeling of SET has been illustrated.

3.2 Basics of singleelectronics The shrinking of electronic devices dimensions to the nanometer size accelerated semiconductor roadmap towards nanotechnology [27] and thus, quantum mechanical effects ought to be considered in transistor operation [28, 29]. Single electron technology is not so different to CMOS technology [30]. It can be used to design similar system like those designed with CMOS technology, but it is based on different phenomena. As a result of working in nanometer size, orthodox theory of single‐ electronics [31] was mentioned to describe the charge transport under the influence of Coulomb blockade. A year after, Fulton and Dolan [32] 19


had observed unusual structure and large electric field induced oscillations in the current voltage curves of small‐area tunnel junctions arranged in a low capacitance multiple tunnel junction configuration. This behavior arises from the tunneling of individual electrons charging and discharging the capacitor. This leaded them to discover single electron transistor device. After the discovery of single electron transistor, there are many research efforts in energy quantization were developed. Geerligs et al. [21] had studied the conductance of linear arrays of two and three normal metal small tunnel junctions for bias voltage below the Coulomb blockade threshold. Wan et al. [33] derived a simple analytical formula for the differential conductance of a double junction containing a small grain under the conditions of Coulomb blockade. Hanna et al. [34] reported a measurement of the Coulomb staircase in a two‐junction system where the fractional residual charge on the central electrode is varied without an external electrode. They presented a simple analytical equation for the current passing through these junctions. Within that progress, Scott‐Thomas et al. [35] discovered accidentally the first semiconductor single electron transistor as reported by Kastner [36]. After describing the behavior of single electron devices, researchers move toward making a review about single electron devices and its application and modeling [18, 20, 37]. Thereafter, Wasshuber came to give overall view on single‐electronics in his book [17]. He presented an

20


overview about the theory of single‐electronics, the simulation methods and numerical algorithms, single electron devices and its applications, random background charges, manufacturing methods and material systems. After this huge progress in this field, more papers [26, 38‐40] were published to discuss circuit design techniques and the challenges in this technology.

3.3 Modeling and simulation techniques Wasshuber [17] presents the most used two numerical solutions for single electron systems (Monte Carlo algorithm and Master Equation) in his book. He discussed in his Ph.D. thesis [41] the developing of a new single electron simulator SIMON [1]. SIMON simulator is based on a Monte Carlo algorithm. It allows transient and stationary simulation of arbitrary circuits consisting of tunnel junctions, capacitors, and voltage sources of three kinds: constant, piecewise linearly time dependent, and voltage controlled. Co‐tunneling can be simulated either with a plain Monte Carlo algorithm or with a combination of the Monte Carlo and master equation approach. Fonseca et al. [42] described a new and efficient method for the numerical study of the dynamics and statistics of single electron systems presenting arbitrary combinations of small tunnel junctions, capacitances and voltage sources. This method is based on numerical solution of a linear matrix equation for the vector of probabilities of various electric charge states of the system, with iterative refining of the operational set of states. This method is able to describe very small deviations from the “classical” behavior of a system, due to the finite speed of applied signals,

21


thermal activation, and macroscopic quantum tunneling of charge (co‐ tunneling). Then, they used it to develop a new program (SENECA) [43] for simulation of single electron systems. The most recent single electron simulator (SECS) [3] is developed by Zardalidis et al. The stochastic nature due to tunneling is incorporated in the simulation of single electron circuits using the Monte Carlo method. The novelty of the SECS system is that it provides the behavior of single electron circuits in an actual time scale. This facilitates the study of the phenomena that take place at an arbitrary single electron circuit.

3.4 Modeling of single electron tunnel junction Many research efforts have been moved toward developing SPICE models for SETJ to enable simulation of single electron devices with other electronic elements. Hoekstra [44] discussed the impulse circuit model for the SETJ. Then, van de Haar et al. [45, 46] improved the impulse model. They expressed the condition for tunneling as a form of a critical voltage instead of free electrostatic energy dependence. Klunder and Hoekstra [19, 47] gave a general derivation of the critical voltage based on local voltage conditions. They described the electrical behavior of the tunnel junctions. They presented two possible ways to excite a junction or a combination of junctions, namely excited by a current or voltage source. Then, Hoekstra and van de Haar [48] developed a semi‐classical physical hot electron model for metallic single electron tunneling circuits. Hänggi et al. [49] verified by physics‐based Monte Carlo simulations that the tunneling junction can in fact be modeled by a piecewise linear

22


voltage‐charge relation, which, from the circuit‐theoretic perspective, is a nonlinear capacitor. van de Haar and Hoekstra [50‐52] used their SETJ model in simulating different single electron circuits like single electron pump and SET and compared their results with measured data.

3.5 Modeling of single electron transistor SET is considered to be the most used single electron device. It has very interesting electrical behavior. Thus, SET becomes the most studied single electron device. Some researchers moved toward making models for it to design large applications making use of its advantages of low power dissipation, small size and high speed. Mahaptera et al. [7‐9, 53] proposed a quasi‐analytical model for SETs named MIB which was validated by comparison with Monte Carlo simulations in terms of drain current and transconductance. Their new approach is based on the separate modeling of the tunneling and thermal components of the drain current, and verified over two decades of temperature. Then, they improved the model to include temperature dependence, device asymmetry and background charge effects. They presented a CAD framework for co‐simulation of hybrid circuits containing CMOS and single electron tunneling devices. They used an improved version of MIB model to extend it to work for single/multi‐gate symmetric/asymmetric device for a wide range of drain to source voltage. They cooperated with Wasshuber and Vaish [5] to develop MIB model to work for a larger range of bias voltage and extend it to explain the background charges. This model showed a good agreement with Monte Carlo simulator SIMON under symmetric bias conditions only.

23


Lee et al. [54] and Yu et al. [55] developed a SPICE compatible transient model for SET. Then, Yu et al. also developed SPICE macro‐ modeling techniques [56‐58] for the compact simulation of single electron circuits. The macro‐model of the SET, which is much more efficient than the corresponding Monte Carlo calculations, was developed and can be considered a reasonably accurate tool for the simulation of complicated single electron circuits. They also proposed a new compact DC/transient SET model [10] for circuit simulation. In this model, a developed equivalent circuit approach had been adopted to build up the circuit admittance matrix. The steady state and time dependent master equation solutions for DC and transient analysis, respectively, had been implemented for exact calculation of the electron population in the Coulomb island. The derivatives of the probability of electron population are explicitly included in the admittance matrix. After three years, they developed the model and implemented it in SmartSpice [14]. Uchida et al. [59] proposed a compact, physically based, analytical SET model suitable for the design and analysis of realistic single electron tunneling circuits. The model was derived on the basis of the orthodox theory of correlated single electron tunneling and the steady‐state master equation method. The SET inverter characteristics were successfully calculated using the model implemented in the simulation program with integrated circuit emphasis (SPICE). The hybrid circuit of SETs with metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) was also successfully simulated. A practical model for SET device was developed by Lee et al. [6] which is based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET 24


current calculated by the analytic model was combined with the parasitic MOSFET characteristics. Analytical model for asymmetric SETs, in which resistance and capacitance parameters of source/drain junctions are not equal, had been developed by Inokawa et al. [11]. The model was based on the steady state master equation, taking only the two most‐probable charging states into account. Therefore, it is very simple. Even so, it could accurately reproduce the peculiar behaviors of an asymmetric SET, such as the skew in the drain current‐gate voltage characteristics and the Coulomb staircase in the drain current‐drain voltage characteristic. Analytical expressions for the charge in the Coulomb island and the capacitance components of the SET are also derived according to the same scheme. They demonstrated that the model can precisely describe the various aspects of the SET behavior. An exact model for a SET was developed within the circuit simulation package SPICE by Lientschnig [12] based on the recursion relation. This model uses the orthodox theory of single electron tunneling and determines the average current through the transistor as a function of the bias voltage, the gate voltage, and the temperature. Circuits including SETs, field‐effect transistors (FETs), and operational amplifiers were simulated. In these circuits, the SETs provide the charge sensitivity while the FETs tune the background charges and provide gain and low output impedance. Zhang et al. [60] presented a simulation and design method for complementary SET based nano‐circuits. An HSPICE behavioral implementation of modified Lientschnig’s single electron transistor model based on the orthodox theory and the Birth‐Death Markov chain is 25


demonstrated and verified with Coulomb characteristics. It showed a reduced CPU time and more compatibility with other SPICE softwares on both Windows and Unix. Jia et al. [13] and Chaohong et al. [61] presented an analytic current model for capacitively coupled SETs that is based on a modified M‐state steady‐state master equation. Based on this current model, they also derive a current noise model for SETs. A compact and analytical model for silicon SETs considering the discrete quantum energy levels and the parabolic tunneling barriers was proposed by Miyaji et al. [15]. The model was based on a steady state master equation that considers only the three most probable states derived from ground level and the first excited level for each number of electrons in the dot to reduce the complexity while accounting for the quantum‐level spacing and multiple peaks in Coulomb oscillation. Negative differential conductance characteristics and aperiodic Coulomb oscillations due to nonuniform quantum level spacings can be reproduced in this model. A simplified model for SET was proposed by Abu El‐Seoud et al. [16] to account for unnecessary lengthy calculation processes, resulting from the large number of states assumed for simulation. The proposed PSPICE simplified model was confirmed by comparing its results to the results of the available models, and it showed a good agreement with them. This model takes much less runtime than the available models and can easily be used to simulate SET‐based integrated circuits on SPICE. Boubaker et al. [62] and Troudi et al. [63] presented simulations of SET output characteristic using Maple [64]. Typical SET I–V characteristics and charge energies curves were presented by developing 26


Maple programs. They developed a new model without considering quantum effects using the superposition theorem, transfer function and Laplace transformer. They proposed a new block using SIMPLORER 7.0 simulator [65] to modulate quantum effects in the SET island. This model is based on a parallel analog‐digital converter.

3.6 Summary In this chapter, a literature review of different single electron simulation techniques, modeling of SETJ, and modeling of SET has been illustrated. After this review, we can make use of these research efforts in describing the basics of single‐electronics to find theories and equations that describe the movement of electrons through tunnel junctions. Also, we can conclude that equivalent circuit models for SETJ are based on impulse circuit model. Thus, a new equivalent circuit model for SETJ is required to describe the electron transport taking into consideration the effect of junction capacitance, tunneling resistance and temperature. On the contrary, SET modeling uses different techniques (master equation or Monte Carlo algorithm). All these models were developed from solving master equation or applying Monte Carlo algorithm for limited value of biasing voltage. All these models work with a good accuracy under symmetric bias conditions only. Thus, modeling and simulation of single electron devices with other electronic components requires a new developed model for SET that works with good accuracy within large range of biasing voltage under symmetric or asymmetric bias conditions. This model should be implemented on SPICE to enable simulation with other conventional circuit elements.

27

Chapter 4 – Equivalent Circuit Model for Single Electron Tunneling Junction

Chapter 4 Equivalent Circuit Model for Single Electron Tunneling Junction 4.1 Introduction Today, there are a couple of different definitions of nanoelectronics. From the physics point of view, nanoelectronics often deal with circuits including nanoelectronic devices whose dimensions have reached such a small length. The wave nature of the electrical carriers cannot be neglected and that device and circuit simulations for essentially classical device structures are confronted with a real quantum mechanical description rather than with classical models. From the electrical engineering point of view, nanoelectronics is understood merely as the electronics based on nanoelectronic devices which utilize quantum mechanical phenomena. They have to be described with semi‐classical models to make circuit synthesis possible. The main quantum property in single electron devices is the tunneling which deals with electron penetration of a potential barrier having a higher energy level than the kinetic energy of the electron approaching the barrier. Quantum mechanics introduces a finite possibility for finding the electron at the other side of the barrier. Any single electron circuit can be described by discrete charge transfer through the tunnel junctions (barriers) and by continuous charge transport along the rest of the circuit. Tunnel junction modeling is based on electronic concept rather

28


than the orthodox theory of single‐electronics which is basically a physical description of the circuit. Single electron tunneling junction is the basic element in single electron devices. It consists of two conductors separated by a tiny gap, typically a few nanometers. Recently few research efforts on the SPICE model of SETJ have been proposed [45, 46, 48]. In this chapter, we present a SPICE model based on the realistic physical phenomena of single electron tunneling. It is able to explicitly describe the effect of the tunneling resistance, junction capacitance and temperature variation. Single electron circuits are simulated using the proposed SPICE model and verified with the results from published data which were simulated by Monte Carlo Simulator SIMON

4.2 Single electron tunneling junction model Orthodox theory of single‐electronics is used to describe the tunneling of an electron in the single electron devices based on the free electrostatic energy. If a single electron is injected by tunneling through the energy barrier of the insulating layer, it may prevent the tunneling of additional electrons and the system is said to be in Coulomb blockade. The charge of the junction changes from /2 to

/2 within tunneling

event (where e is the electron charge). The tunneling of a single electron is always a random event, with a certain rate Γ that depends on the change in free electrostatic energy Δ of the system. The tunneling rate as in Eq. (2.3) is a function of the junction capacitance , tunneling resistance Γ

, and temperature and is given by ⁄

29

(4.1)


The tunneling event is a strong function in the energy argument that occurs when the change of junction energy between the time immediately before and the time immediately after the tunnel event is positive. The change in free energy can be calculated by the method of critical voltage described by Geerligs et al. [21]. The change of the junction free energy [66] can be expressed as

∆

(4.2)

(4.3)

⁄

where Q is the average charge on the junction capacitance and is the junction capacitance. The general relation for the critical voltage of the tunneling junction [47] is given by where

(4.4)

is the replacement capacitance that equals the equivalent

circuit capacitance. Single electron tunneling devices, included in a circuit, can be described by a discrete charge transfer through the tunnel barriers coexisting with a continuous charge transfer along the rest of the circuit. Therefore, the SETJ can be modeled by the impulse model as shown in Fig. (4.1). The current source used in the impulse model is used to feed the junction with one electron when the tunnel condition occurs. An electron tunnels from source to drain when the voltage over the junction exceeds the critical voltage

that is given by 30


e  it  t  t 0 

Cj

Fig. (4.1): The junction impulse model.

(4.5)

4.3 Proposed SETJ circuit simulation model In our circuit simulation model [66], the effect of the tunneling resistance and temperature is included. The SETJ is modeled by a capacitance connected in parallel with a large resistance to eliminate the error generated due to SPICE connection rules. When the voltage over the junction reaches the value of the critical voltage

, an electron

tunnels through the junction. The tunneling event of an electron is modeled by an impulse current passing through the junction for a very small period of time

, where

as illustrated in Fig. (4.2).

Fig. (4.3) shows a complete circuit simulation model for SETJ. It consists of a resistor, capacitor, voltage controlled current source, two hard limiters, time control circuit, and delay element [66]. The detection

i t 

dtt

t

Fig. (4.2): Impulse current passing through the junction within tunneling event.

31


Cj

R

+

+

Limiter 1

Limiter 2

-

I +

+

Vcr

delay

-

C R

+ _

0.37 V

IT

Fig. (4.3): The SPICE SETJ model.

for tunneling is implemented with a hard limiter function. If the junction , the output from the first hard limiter will be

voltage is higher than

high. The width of the pulse is set by a time control circuit. When the voltage across the resistor decreases to 0.37 V, the passed time equals . The output of the second hard‐limiter is high when the first the output is low again. The

hard‐limiter is high, and after a time

second hard limiter output pulse is fed into the delay element to avoid convergence problem in SPICE. The pulse is delayed with a factor

.

where

In order to take the effect of tunneling resistance and temperature, we must not ignore the current calculation at any instant of time. It can be calculated by Γ

Γ

(4.6)

where Γ is the tunneling rate in the forward direction and Γ is the tunneling rate in the backward direction. This value of current can be implemented by connecting a current source in parallel with junction capacitance. One can see in Eq. (4.1) that the tunneling rate depends on the value of tunneling resistance and temperature. Thus, this model gives an overall

32


description of the tunnel junction taking into consideration all junction parameters.

4.4 Simulation results In order to validate our proposed SPICE model, the current biased SETJ shown in Fig. (4.4) has been simulated and compared with single electron simulator SIMON as shown in Fig. (4.5). The results show a good agreement. The output voltage increases until it reaches the critical voltage

and, at this instant, it decreases to

. This event represents

the tunneling of an electron. By using a tunnel junction with junction capacitance equal to 1 aF, the critical voltage will be 80 mV. The tunneling resistance and junction capacitance has a significant effect on the output voltage. As the junction capacitance changed from 1 aF to 2 aF the critical voltage changes from 80 mV to 40 mV as shown in Fig. (4.6). While the tunneling resistance changes from 100 k to 1 M, the output voltage takes less time to reach the critical value

as shown

in Fig. (4.7).

Fig. (4.4): Current‐biased SETJ.

33


0.08

Output Voltage (V)

0.04

0

-0.04

-0.08 -0.1 0

SIMON 0.2

developed model

0.4

0.6

0.8

Time (s)

1 x 10

-12

Fig. (4.5): Simulation results for current biased SETJ compared with single electron simulator SIMON, where IS = 1 µA, Cj = 1 aF.

0.1 0.08

Output Voltage (V)

0.04

0

-0.04

-0.08 -0.1 0

C = 1 aF

C = 2 aF

j

0.2

j

0.4

0.6 Time (s)

C = 4 aF j

0.8

1 x 10

-12

Fig. (4.6): The voltage over SETJ as a function of time at different junction capacitances, where IS = 1 µA, RT = 1 M.

34


0.025 0.02

Output Voltage (V)

0.01

0

-0.01

-0.02 -0.025 0

R = 1 M  T

1

2

R = 100 k 

R = 200 k 

T

3 Time (s)

T

4

5

6 x 10

-13

Fig. (4.7): The voltage over SETJ as a function of time at current biased SETJ with different tunneling resistances, where IS = 1 µA, Cj = 4 aF.

Fig. (4.8) shows another standard example (electron box circuit) to test our proposed model. In this circuit, the input voltage applied to the circuit is a ramp function which varies from 0 V to 30 mV within a time period of 0.6 ps. The developed model has been used to simulate this circuit and then compare the results with single electron simulator SIMON as shown in Fig. (4.9). The results show a good agreement. Fig. (4.10) shows the effect of tunneling resistance on the output voltage. One can observe that the tunneling resistance has a great effect on circuit response.

35


Fig. (4.8): Electron box circuit.

0.01 0.008

Output Voltage (V)

0.004

0

-0.004

-0.008 SIMON -0.01 0

0.2

developed model

0.4

0.6

0.8

Time (s)

1 x 10

-12

Fig. (4.9): Simulation results for electron box circuit compared with single electron simulator SIMON, where Cj = 1 aF, Ccap = 9 aF, RT =1 MΩ.

36


0.01 0.008

Output Voltage (V)

0.004

0

-0.004

-0.008 -0.01 0

R = 1 M 

R = 100 k 

T

0.2

T

0.4

R = 200 k  T

0.6 Time (s)

0.8

1 x 10

-12

Fig. (4.10): The voltage over SETJ as a function of time at electron box circuit with different tunneling resistances, where Cj = 1 aF, Ccap = 9 aF.

4.5 Summary In this chapter, the operation of single electron tunnel junction has been discussed. Then, an equivalent circuit model for SETJ has been introduced. This model gives an exact description of the SETJ behavior. It utilizes the concept of taking the critical voltage as the condition for tunneling. This model is validated with single electron simulator SIMON upon current biased SETJ and electron box circuits.

37

Chapter 5 – Single Electron Circuit Simulation Methods

Chapter 5 Single Electron Circuit Simulation Methods 5.1 Introduction Single electron effects are significant in ultra small dimension devices. They are the central physical fact for numerous novel types of logic and memory circuitry. Most single electron device models are based on the orthodox theory of the single‐electronics. As mentioned before, the theory assumes that the resistance of the tunnel barriers in the system is much greater than the quantum resistance, thereby insuring that the electron is localized within a particular conducting island at any instant of time. The orthodox theory also ignores electron tunneling time through the barrier. Furthermore, it neglects quantization of electron energy within the small conductive island formed by the tunnel junctions. Much of the quantum mechanics are disregarded in most of the commonly used models which are based on the orthodox theory, and thus these models are considered semi‐classical. Some models focus on the statistical nature of the tunneling process of an electron through a barrier which is influenced by the electrostatic energy in the system. The tunneling process occurs at a rate that depends on the resulting change in the free energy of the system. Once the tunneling rates for all junctions are known, Monte Carlo simulation method is used to determine the actual tunneling events that take place, and thus the random dynamics of single electron systems can be simulated. Monte Carlo simulation method was implemented in various programs such as MOSES [4] and SIMON [1]. It models the underlying 38


physics of the system giving average quantities needed to determine DC device characteristics and it also provides the tunneling dynamics needed for the study of circuit operation. The master equation is another different single electron circuit simulation method. It was built into simulation programs such as SIMON. Its approach is only useful in simulating systems having only few tunnel junctions. Also, it is not useful in investigating the dynamics of the microscopic tunneling events in single electron circuits since it deals only with averages. In other words, Monte Carlo technique is poor in including such effects as co‐tunneling, whereas the master equation method is useful in such cases. The tunneling rates and the change in free energy of all relevant tunnel events are required to be evaluated in both master equation and Monte Carlo simulation methods. Thus, the steps used in calculating these values before and after all possible tunneling events are implemented in both simulation methods.

5.2 Free energy of an arbitrary circuit Before using master equation or Monte Carlo methods, input tunnel rates of relevant states must be calculated. The tunnel rate formulas depend on the change in the free energy of each tunnel event causes. Thus, the first part of a simulation is the calculation of the free energy before and after all possible tunnel events in an arbitrary circuit. 5.2.1 Notation A single electron arbitrary circuit consists of capacitors, tunnel junctions, voltage sources and current sources that constitute the circuit branches as shown in Fig. (5.1). Each branch starts and ends at a node.

39


Fig. (5.1): Single electron circuit consisting of tunnel junctions, capacitors, and voltage sources and showing different types of nodes.

Node potentials, node charges and branch currents describe the circuit characteristics. Kirchhoff’s laws are usually used to calculate the unknown parts (voltages, charges and currents) in the circuit by using the known parts. A potential node (node 1) is named after a node whose potential is known, such as the case of a node connected to a grounded voltage source. A node with known charge is defined as a charge node. That charge is known to be either a constant charge or a charge which can change by an integer of elementary charge. A charge node has a constant charge if it is connected to capacitors only, taking into consideration that no charge can enter or exit, such as node 6. If a charge‐ node is connected to at least one tunnel junction it can change its charge by an integer number of the elementary charge due to electrons tunneling onto and off the node, such as nodes 2 and 4. Ungrounded voltage sources that are not connected to other grounded voltage sources produce floating nodes where neither the charge nor the potential is known of such nodes. However, the potential differences of all floating‐ nodes in a macro‐node are known. For example the potential difference 40


between nodes 3 and 5 is determined by a voltage source. In addition to the known potential differences of floating nodes comprising a macro‐ node, the charge of the macro‐node is known. The charge of the macro‐ node is the sum of the charges of its floating nodes. 5.2.2 Electrostatic energy 1 nodes

A single electronic network consists of , where

nodes are charge nodes,

nodes are potential nodes,

nodes are floating nodes, and one node is the ground node. Subscripts , , and denote potential node, floating node and charge node quantities respectively. Using the capacitance matrix

, charge vector and

potential vector [41] are related by ,

,

The sub‐matrices

,

,

,

and

(5.1)

have dimensions

, and

respectively.

matrix is a symmetric matrix. Consequently

The capacitance

and are symmetric. The

unknown quantities of charges on potential nodes and floating nodes and potentials of charge nodes

,

,  can be written in terms of the known

quantities that are the potentials on potential nodes and floating nodes and the charges on charge nodes. So it can be reformulated as ,

,

41

(5.2)


Fig. (5.2): A macro‐node is formed by a set of voltage sources which are not connected to ground.

The potentials of the floating nodes are derived from the equations of the macro‐nodes, which are the known sum of charge of each macro‐ node and the individual potential differences given by the voltage sources comprising a macro‐node shown in Fig. (5.2). The voltage sources give a set of

1 equations, where

node (

4). 1 0 0

1 0 0 1 1 0 1 0 1

is the number of nodes in a macro‐

(5.3)

With the additional equation for the charge of the macro‐node, ∑

,

4

(5.4)

the electrostatic energy of a circuit can be expressed using the relation which links known charges and potentials with the unknown quantities, and is given by ,

,

The work done by the voltage sources is 42

(5.5)


,

∑

,

min

,

,

(5.6)

where the sum over Nm macro‐nodes considers the fact that voltage sources in a macro‐node can only shift charge relative from the node of lowest potential in the macro‐node and not from ground level as grounded voltage sources do. The last term in the above equation considers the work to replace a tunneled electron, since if it tunnels from or to a potential node or floating node its charge has to be replaced by a voltage source. With the expression for the electrostatic energy stored in the circuit, Eq. (5.5), and the work done by the voltage sources, Eq. (5.6), the free energy [41] is given by the difference of these two quantities.

(5.7)

The difference of free energy before and after a tunnel event is then given by ∆

(5.8)

5.3 Master equation method The orthodox theory solves the tunnel rates through tunnel junctions in single electron circuits, but it does not resolve the statistics of electron transport. The master equation is developed based on two assumptions. The first assumption is for the transport process in which electrons are assumed unable to probe their past, and thus their tunneling rates depend only on the momentary state of the system. This is exactly the case of a Markov process which is a stochastic process having the Markov property (a random process whose future probabilities are determined by its most recent values). The second assumption presumes that the

43


system evolves at random times in a jump like fashion [16]. The master equation can be expressed as ,

where Γ |

Γ | ,

,

|

Γ

,

(5.9)

is the probability density function in state space, and

denotes the transition rate from state to state . In the case of

discrete states, the master equation is reformulated as follows ∑

Γ

Γ

(5.10)

where Γ denotes the transition rate from state to state and

is

the time dependent occupation probability of state . A state is a specific charge distribution (i.e. each node or quantum dot is occupied by a certain number of electrons). Fig. (5.3) is a typical state transition diagram for such a process. The important aspect of this method is to obtain the set of relevant states that the circuit under investigation can occupy in order to set up the rate matrix  . The states and their transition rates of the circuit is described by a set of differential equations which may be written in matrix form for m states [17] as follows Γ

(5.11)

Fig. (5.3): State transition diagram for a jump process with discrete states (

44

5).


∑ Γ

Γ

Γ

Γ ∑ Γ

… …

Γ

…

Γ Γ ∑

(5.12)

Γ

Single electron circuits with at least one island have a discrete but infinite number of states because the number of excess electrons is unbound. Clearly, higher numbers of excess carriers are due to the Coulomb blockade and are exponentially suppressed and are more unlikely to exist. It is impossible to filter out the most likely states from an arbitrary circuit, an adaptive scheme is utilized which starts with the initial state and calculates the tunnel rates for all possible transitions. These rates are used as a zero order estimate for the state probability of other states reached with these rates as transitions. High transition rates leads in general to states with high probabilities and vice versa. If the rate falls under certain threshold, the state will not be considered. Then, the master equation is solved with all states that passed the threshold test. In the next iteration, new states are joined to the set of relevant states and the circuit is better described. This is called a journey in state space, starting at the set of states already found and making steps into other states in state space. The master equation method for the simulation of single electron circuits is the general stochastic description of a single electron circuit. By simplification, the state can only change to a neighboring state since only one electron is assumed to tunnel at a time. Processes with this property are called birth‐death processes and are illustrated in Fig. (5.4). The stationary case, where

/

0, is a system of linear equations

which may be solved by a multitude of numerical algorithms. The 45


Fig. (5.4): State transition diagram of a birth‐death process.

Fig. (5.5): State transition diagram of a Poisson process.

transient case which is a system of ordinary linear first order homogeneous differential equations may be solved either by integrating Eq. (5.12) and calculating the exponential of a matrix or by solving the system of differential equations without explicitly forming the exponential of the transition rate matrix. It can be expressed as where

(5.13)

is the state probability vector and Γ is the tunneling rate

matrix. Hence, the electron transport can be identified. Assuming further that states can evolve in one direction, this is the case if only tunneling in one direction is considered, and that all states have an equal transition rate to the next state, which is the case when charging effects are neglected. This leads to the Poisson process which

46


starts at

0 and evolves to higher states as shown in Fig. (5.5). Master

equation for that process is given by Γ

Γ

,

0

1

(5.14)

(5.15)

Solving this differential equation gives

!

5.4 Monte Carlo Method The direct discrete stochastic modeling of electron transport is possible between quantum mechanics and classical physics. This is done by treating purely quantum mechanics, analyzing wave functions and classical physics macro‐model. In macroscopic scale, electrons appear to transport in continuum fashion. This makes the Monte Carlo simulation method prevalent. Tunnel events can be accurately modeled as discrete events. For the Poisson distribution given in Eq. (5.15), the probability of tunnel event for state 0 takes place at  is

(5.16)

(5.17)

The Monte Carlo procedure for calculating τ depends on

where r is a random number that is constructed in the interval 0,1 . Starting from a list of all possible tunnel events with their particular tunneling rates, random tunnel times are computed for all events. The event with the smallest will happen first and thus is taken as the winner. Node charges are updated according to the computed tunnel event, which updates node potentials. The current is a charge per time interval and is directly computed from the winning tunnel events. Each 47


tunnel event transports an electron along a certain path. All charges transported in each circuit branch are summed and averaged over time. New tunnel rates are calculated and a new winner is determined through stochastic sampling. Doing this many times gives the macroscopic behavior of the single electron circuit. Another possibility is to calculate first an exit tunnel time out of the current state ,

ln r ⁄∑ Γ , and selecting afterwards with a

second independent random process, which event actually happened. To do that one generates an evenly distributed random number in the interval 0, ∑ Γ

. If the random number is larger than ∑

smaller than ∑

Γ , the winner is event .

Γ but

It is important to simulate more events to guarantee that the circuit is long enough in equilibrium for the averaging to give meaningful events. Monte Carlo method has problems with rare events (co‐tunneling). If the co‐tunnel rate is 10‐6/s and the normal tunneling is 1/s, it is essential to simulate in average one million events to have one co‐tunnel event among the simulated ones.

5.5 Summary Single electron circuits cannot be simulated using equivalent circuit models for tunnel junctions because of neglecting quantum effects in these models. SETJ model ignores the effect of charge sharing between tunnel junctions through islands. Therefore, there are two methods used for simulation of single electron circuits (master equation and Monte Carlo algorithm). Master equation describes the system as a state space where each state has its probability which can be computed after setting up the 48


transition rate matrix. Master equation deals with averages rather than certain state. Monte Carlo algorithm tends to compute the tunneling duration for each tunnel event to choose the winning tunnel event that has the smallest tunnel event.

49

Chapter 6 – Modeling and Simulation of Single Electron Transistor

Chapter 6 Modeling and Simulation of Single Electron Transistor 6.1 Single electron structure and operation Single electron transistor can be considered the most important single electron device. It shows several interesting features in its electrical characteristics and behavior so it is the most studied device in single electron devices. Fig. (6.1) shows the basic schematic of a SET device. It consists of two single electron tunnel junctions which sandwich a single conductive island between them. Each one of these tunnel junction can be considered to be like a capacitor but with thinner layer of insulating material. To control SET conductance, a gate attached to the island through a thicker layer of insulating material to prevent tunneling through it. An electron can only enter the island by the tunneling through one of the two tunnel junctions. The tunneling event of an electron is described

Fig. (6.1): A schematic diagram of single electron transistor.

50


by orthodox theory of single‐electronics. If a single electron is injected by tunneling through the energy barrier of the insulating layer, it may prevent the tunneling of additional electrons and the system is said to be in Coulomb blockade. Fig (6.2) shows the available electron transitions for SET device. As mentioned before, the tunneling of a single electron is always a random event with a certain rate Γ that depends on the change of the free electrostatic energy of the system ∆ . The tunneling rate is a ,

function of the junction tunneling capacitances ,

tunneling resistances Γ

∆ ,

,

,

∆

,

/

, the junction

, and temperature T and is given by

(6.1)

The single electron transistor can be considered two electron box circuits connected to each other. Thus, the reduction of the free energy during tunneling event in forward direction (superscript +) and backward direction (superscript ‐) in the two single electron tunnel junctions are given by [41]

Fig. (6.2): Diagram of tunneling rates for the movement of an electron through single electron transistor.

51


∆

⁄

(6.2)

∆

⁄

(6.3)

the voltage across these two tunnel junctions are

(6.4)

(6.5)

where is the voltage of the conductive island, is the background charge on the island, and is the number of electrons in the island. According to orthodox theory of single‐electronics, a proper operation of a SET device requires two conditions. The first is that the tunnel ,

junction resistances

should be greater than the quantum

resistance (~26kΩ) in order to confine the electrons in the island. The second is that the charging energy of the island capacitance should be to avoid electron

larger than the available thermal energy tunneling due to the thermionic emission.

The total capacitance of the island to ground is equal to the summation of all gate, source, and drain capacitances which can be expressed as

(6.6)

By setting the free electrostatic energy of two tunnel junctions equal to zero in Eqs. (6.2) and (6.3), one can drive the equations for boundary of stable regions. Each region is bounded by four lines like a diamond‐ shaped area as shown in Fig. (6.3). This shape is precisely determined by junction capacitances, background charges and type of biasing (symmetric,

⁄2 and

⁄2 ; asymmetric,

0). The general formulas for these boundaries are [17] 52

and


e n

q

VD

VG CG

VD

VS CS

(6.7)

e n

q

VG

VD CG

VS

VD CS

(6.8)

e n

q

VG

VS CG

VD

VS CD

(6.9)

(6.10)

e n

q

VG CG

VS

VS

VD CD

The current in the stable regions is constant because the number of electrons in a stable region is constant. Therefore, the stable regions are correspondent to the Coulomb blockade. These stable regions are located for small

. On the contrary, the current in the unstable regions is not

constant. It increases with moving faraway the stable regions boundaries. and

Thus, one can get the well known characteristics

as shown on Fig. (6.4) by cutting the stability plot diagram vertically and horizontally respectively. A vertical cut parallel to the

axis runs only

through one stable region. This stable region can be recognized by the value of

at the cutting edge (i.e. for

will be

0 where the number of electrons in the island is zero). A

horizontal cut parallel to the

, the stable region

axis for small

runs through all stable

regions resulting in periodic Coulomb oscillations with a period of ⁄ The

characteristics becomes linear for large bias voltage, but it is

displaced from /2

.

/

with small offset voltage of

. The slope obtained just after the Coulomb blockade

occurrence is equal to 1/2

1/2

for

. This is caused by

the large biasing overshadowing of any Coulomb interaction and so the electrons deal with junctions as two resistors in series. For small biasing exceeding the Coulomb condition, electrons can either enter the island

53


via junction one or exit via junction two and this is considered as two parallel conduction channels, causing the 1/2

1/2

relation.

For asymmetric single electron transistor with unequal tunnel junctions, the

characteristic is a staircase like shape as shown in

Fig. (6.5). Unequal tunnel resistances will directly affect the tunnel rate and unequal tunnel capacitances will change the distribution of the bias voltage across tunnel junctions, indirectly affecting the tunnel rate. For , the tunneling speed in source tunnel junction is larger than in drain tunnel junction. Thus, once the bias voltage is above the Coulomb blockade threshold, an electron will quickly tunnel through source tunnel junction to the island. However, it will take much longer time to escape through drain tunnel junction due to its higher resistance, resulting in a local saturation in

characteristic. So we can observe the

difference between symmetric and asymmetric SET where an electron exit the island immediately after entering it in symmetric device. However, an electron can’t escape as quickly as it enters the island in asymmetric device.

54

Unstable region

55 e 2C G

e 2C D  C G 

Unstable region

Fig. (6.3): Stability plot diagram for single electron transistor.

e 2C S  C G

e 2CG

Unstable region

Unstable region

Stable region n=1

Vertical cut

Unstable region



Stable region n=0

2C S  C G

e 2C D  C G

Unstable region e

Unstable region

Stable region n = -1

Unstable region

Horizontal cut

VDS

VGS



25

VDS = 82 mV VDS = 69 mV VDS = 61 mV

D

Drain Current I (nA)

20

15 VDS = 39 mV

VDS = 48 mV

10 VDS = 26 mV

VDS = 4 mV VDS = 17 mV

5

0

0

0.05

0.1

Gate - Source Voltage V

(V)

GS

0.15

(a) 30 V 20

V

10

V

GS GS GS

= 4 mV = 16 mV = 24 mV = 36 mV

D


V

GS

0

-10

-20

-30 -0.1

-0.08

-0.06

-0.04 -0.02 0 0.02 0.04 Drain - Source Voltage V (V)

0.06

0.08

0.1

DS

(b) Fig. (6.4): Symmetric SET characteristics. a) characteristics. The SET device parameters are (

characteristics. b) = = 1 aF,

= 2 aF,

=

= 1

MΩ, T =1 K) biased under symmetric bias voltage condition.

56


25 VDS = 69 mV

D


20

VDS = 82 mV

VDS = 61 mV

15 VDS = 48 mV

10 VDS = 4 mV

VDS = 39 mV

5

VDS = 26 mV

VDS = 17 mV

0 0

0.05 Gate - Source Voltage V

GS

0.1 (V)

0.15

(a) 25 20

D


15 10

V V V V

GS GS GS GS

= 4 mV = 16 mV = 24 mV = 36 mV

5 0 -5 -10 -15 -20 -25 -0.1

-0.08

-0.06

-0.04 -0.02 0 0.02 0.04 Drain - Source Voltage V (V)

0.06

0.08

0.1

DS

(b) Fig. (6.5): Asymmetric SET characteristics. a) characteristics. The SET device parameters are (

characteristics. b) = = 1 aF,

= 2 aF,

= 3 MΩ,

= 100 kΩ, T = 1 K) biased under symmetric bias voltage condition.

57


6.2 Single electron transistor modeling Modeling of SET utilizes master equation or Monte Carlo algorithm. Master equation is used in simulating single electron circuits based on the orthodox theory. It computes the occupation probability of each state. Monte Carlo algorithm computes the time duration for all available tunnel events. Then it determines the success tunnel event which has smallest tunnel duration. 6.2.1 Master equation Master equation describes the system as a Markov process which is a stochastic process having the Markov property whose future probabilities are determined by its most recent values [17]. In ME algorithm, the change in free energy of both junctions during tunnel event is calculated for state n using Eqs. (6.2) and (6.3). Then the tunneling rates are evaluated using Eq. (6.1). ME solves the system with all the state probabilities according to the tunneling rates between those states, and is given by ∑ where

Γ

Γ

(6.11)

is the time dependent occupation probability of state , and

Γ denotes the tunneling rate from state to state . It also can be expressed in a matrix form Γ

(6.12)

The important aspect of this method is to obtain the set of relevant states that the circuit under investigation can occupy in order to set up the rate matrix  . The states and their transition rates of the circuit are

58


described by a set of differential equations which may be written in matrix form for m states as follows ∑ Γ Γ

Γ

Γ ∑ Γ

Γ

… … …

Γ Γ ∑

(6.13)

Γ

Single electron transistor has a single island that have a discrete but infinite number of states, because the number of excess electrons is unbound. Clearly higher numbers of excess carriers are due to the Coulomb blockade and are exponentially suppressed and are more unlikely to exist. It is impossible to filter out the most likely states from an arbitrary circuit. An adaptive scheme utilized in master equation is to start with the initial state and to calculate the tunnel rates for all possible transitions. These rates are used as zero order estimation for the state probability of other states reached with these rates as transitions. In general, high transition rates leads to the states with high probabilities and vice versa. If the rate falls under a certain threshold, the state will not be considered. Then the master equation is solved with all states that passed the threshold test. In the next iteration, new states are joined to the set of relevant states and the circuit is better described. This is called a journey in state space, starting at the set of states already found and making steps into other states in state space. The number of states to be included in the rate matrix Γ is infinite because the number of excess electrons is unbound. A typical state transition diagram for a tunneling process is shown in Fig. (4.3). It shows all transitions that are available between a limited number of states. It can be observed that there are a large number of transitions between 59


these 5 states. The state can only be changed to a neighboring state since only one electron is assumed to tunnel at a time. Processes with this property are called birth‐death processes and can be illustrated with a simple state diagram as shown in Fig. (4.4). In this case the rate matrix Γ is found to be Γ Γ 0

Γ

Γ Γ

0 Γ

Γ Γ

Γ

0

… … …

Γ

0

0

…

0 0 0 Γ

(6.14)

,

The most probable states are found around the state representing the optimum number of electrons in the island which can be calculated by where

(6.15)

is a function that rounds the number to the nearest

integer less than or equal . The solution of master equation gives where and

(6.16)

is the state probability vector, Γ is the tunneling rate matrix is the initial probability vector where

1

0

0

…

0 .

The value of the initial probability vector is determined by having a look to the stability plot diagram where the number of electrons in the island 0. So the state of

is zero for

0 has the unity probability

and the other states has zero probability. Afterwards, the electron transport can be identified and the current is defined by ∑

Γ

60

(6.17)


ΓD where Γ

Γ

Γ

(6.18)

denotes the tunneling rate through the drain junction to the

right side at state , while Γ

denotes the tunneling rate through the

drain junction to the left side at state as shown in Fig. (6.2). SET simulation using master equation method is accomplished in the steps listed by the flow diagram shown in Fig. (6.6). In master equation solution, a truncation method is implemented in the algorithm to include only the most probable states, and this is done by adopting a threshold value to cut off low probability states. The threshold value for tunneling rate determines the number of states taken into simulation which affects the simulation accuracy. Fig. (6.7) shows 3D simulation of the drain current of SET with gate‐ source voltage and drain‐source voltage. This simulation utilized master equation with a limited number of states (5 and 9 states) without using the truncation algorithm. One can observe that increasing the drain‐ source voltage requires more states to be included in order to get acceptable accuracy.

61


Start

Calculate nopt Calculate ∆F & Γ Add more states No

Check truncation

Construct Γ matrix

∑

Γ

Γ

End

Fig. (6.6): Flow diagram for master equation algorithm.

62


-7

x 10

D


8 6 4 2 0 0.3 0.2 0.1 Gate - Source Voltage V

GS

0.2

0.15

(V)

0

0.1 0.05 Drain - Source Voltage V

0

DS

(V)

(a)

-7

D


x 10 8 6 4 2 0 0.3

0.2 0.1 Gate - Source Voltage V

GS

0.2

0.15

(V)

0


0

DS

(V)

(b) Fig. (6.7): Simulation results from applying master equation method on symmetric SET for a) 5 states. b) 9 states. The SET device parameters are ( =

= =

= 1 aF,

= 100 kΩ, T = 1 K) biased under symmetric bias voltage condition.

63


6.2.2 Monte Carlo Algorithm Monte Carlo algorithm as described in Sec. (5.4) is a stochastic modeling of electron transport in electron devices. Using Monte Carlo algorithm in SET simulation requires tunnel rates calculation. The tunnel rates are evaluated in the same manner discussed before. Electrons tunneling are considered as events that will occur in multiple durations depending on the tunneling rates just computed. The winning event is chosen depending on the minimum duration needed for an electron to tunnel a junction and is given by Eq. (5.17). As the island state raised or lowered by one electron charge depending on the winning event, the tunneling rates are re‐evaluated and other winning events are considered. In the case of steady state, an electron will first tunnel through one of the two junctions; this will increase the probability of an electron to tunnel through the other junction in order to restore the system to the steady state case. The drain‐source current is equal to the electron charge divided by the time for electron transport from source to drain. Thus the current can be expressed as

(6.15)

where is the duration for an electron to tunnel through drain tunnel junction and is the duration for an electron to tunnel through source tunnel junction. While considering that electron tunneling process is very fast to be considered, co‐tunneling process is not considered in our case. The simulation was run and the results are shown in Figs. (6.8) and (6.9). The Coulomb blockade triangular region is equal to that of master equation method but with fluctuations of the readings. For the conduction region, the estimated output drain current swings and seems

64


somewhat random. The randomness in the output shape is due to the low amount of random numbers utilized in simulation. This amount was raised in multiples from 50 to 20000 till finding an acceptable output with reasonable runtime duration. The runtime duration is linearly proportional to the amount of random values utilized.

65


-7

D


x 10 15

10

5

0.3 0.2 0.1 Gate - Source Voltage V

0.2

0.15

GS

(V)

0


0

DS

(V)

(a)

-7

D


x 10 10 8 6 4 2 0.3

0.2


0.2

0.15

0.1 GS

(V)

0


0

DS

(V)

(b) Fig. (6.8): Simulation results from applying Monte Carlo algorithm on symmetric SET for a) 50 random values. b) 500 random values. The SET device parameters are (CD = CS = CG = 1 aF, RD = RS = 100 kΩ, T = 1 K) biased under symmetric bias voltage condition.

66


-7

D


x 10 8 6 4 2

0.3 0.2 0.1 Gate - Source Voltage V

GS

0.2

0.15

(V)

0


0

DS

(V)

(a)

D


x 10

-7

8 6 4 2

0.3 0.2


GS

0.2

0.15

0.1 (V)

0


0

DS

(V)

(b) Fig. (6.9): Simulation results from applying Monte Carlo algorithm on symmetric SET for a) 5000 random values. b) 20000 random values. The SET device parameters are (CD = CS = CG = 1 aF, RD = RS = 100 kΩ, T = 1 K) biased under symmetric bias voltage condition.

67


6.3 Developed model Our developed model solves steady state master equation taking into consideration the most probable states in the region where ( 4 /

). After solving master equation for SET with symmetric

(

/2 ,

/2 ) and asymmetric (

,

0 ) bias

voltage and plotting the probability distribution function as shown in Fig. (6.10) and Fig. (6.11), we found that the most probable states with asymmetric bias are symmetric bias are

6,

5, … … ,

2,

1, … … ,

,

1 and with 2,

3 . To

develop a model that works with a great accuracy in the region of (

4 /

) whatever the drain to source voltage is either

symmetric bias or asymmetric bias, it must be taken into consideration the ten states 5,

6, 4, … … ,

5, … … , 1,

2,

3 or eight states

2 for less time consuming and

good accuracy.

68


-7

x 10 8

6 ID

4

2 0 0.3 0.25

0.2

0.2

0.15

0.15 0.1

0.1

VGS

0.05

0.05

0

VDS

0

(a) The probability of state nopt

The probability of state nopt+1

1

1

0.5

0.5 0.2

0 0.3

0.2

0.1 0.2

0.1

VGS

0

0

0 0.3

VDS


0.1 0.2

0.1

VGS

0

0

VDS


1

1

0.5

0.5 0.2

0 0.3

0.2

0.1 0.2

0.1

VGS

0

0

0 0.3

VDS

0.1 0.2

0.1 VGS

0

0

VDS

(b) Fig. (6.10): a) 3D pattern for drain current characteristics with VDS and VGS under steady state conditions and asymmetric bias voltage. b) Probabilities of the most probable states under asymmetric bias voltage. 69


The probability of state nopt-1


1

1

0.5

0.5 0.2

0 0.3

0.2

0.1 0.2

0.1

VGS

0

0

0 0.3

VDS


0.1 0.2

0.1 VGS

0

0

VDS


1

1

0.5

0.5 0.2

0 0.3

0.2

0.1 0.2

0.1 VGS

0

0

0 0.3

VDS


0.1 0.2

0.1 VGS

0

0

VDS


1

1

0.5

0.5 0.2

0 0.3

0.2

0.1 0.2

0.1

VGS

0

0

0 0.3

VDS

The probability of state nop-7

0.1 0.2

0.1 VGS

0

0

VDS

The probability of state nop-8

1

1

0.5

0.5 0.2

0 0.3

0.2

0.1 0.2

0.1

VGS

0

0

0 0.3

VDS

0.1 0.2

0.1 VGS

0

0

VDS

(b) (Continued) Fig. (6.10): (Continued) a) 3D pattern for drain current characteristics with VDS and VGS under steady state conditions and asymmetric bias voltage. b) Probabilities of the most probable states under asymmetric bias voltage.

70


-7

x 10 8

6 ID

4

2 0 0.3 0.25

0.2

0.2

0.15

0.15 0.1

0.1

VGS

0.05

0.05

0

VDS

0

(a) The probability of state nopt


1

1

ID 0.5 0 0.3

0.5 0.2

0.2

0.1 0.2

0.1

VGS

0

0

0 0.3

VDS


0.1 0.2

0.1

VGS

0

0

VDS


1

1

0.5

0.5 0.2

0 0.3

0.2

0.1 0.2

0.1

VGS

0

0

0 0.3

VDS

0.1 0.2

0.1 VGS

0

0

VDS

(b) Fig. (6.11): a) 3D pattern for drain current characteristics with VDS and VGS under steady state conditions and symmetric bias voltage. b) Probabilities of the most probable states under symmetric bias voltage.

71




1

1

0.5

0.5 0.2

0 0.3

0.2

0.1 0.2

0.1

0

VGS

0

0.1

0 0.3

VDS

0.2


0.1 VGS

0

0

VDS


1

1

0.5

0.5 0.2

0 0.3

0.2

0.1 0.2

0.1 VGS

0

0

0.1

0 0.3

VDS

0.2

0.1 VGS

0

0

VDS

(b) (Continued) Fig. (6.11): (Continued) a) 3D pattern for drain current characteristics with VDS and VGS under steady state conditions and symmetric bias voltage. b) Probabilities of the most probable states under symmetric bias voltage.

The recursion relation is another accurate method used in single electron transistor simulation [12]. It is used to determine the probability of each state in a simple way. The probability of occupation of each state is driven from the recursion relation given below 1

S

D S

From the fact that ∑

D

(6.16)

1, we can compute the probability

distribution function for the most probability states and the current is defined by Eq. (6.13). So our model makes use of the recursion relation to compute the probability distribution function in two steps. Firstly, we compute the coefficients

⁄

72

as follows


S

1

2

D

S

D

S

1 P n

D

S

P

D

P P

(6.17)

(6.18)

1

6.19

P

P

P S

D

S

D

S

D

S

D

P n

2 1

(6.20)

1

(6.21)

and so on for the coefficients of other states. S

D D

S

D

S S

1 (6.22)

D

Secondly, applying the fact ∑ of the optimum state ∑

1 to determine the probability

as described in equations below 6

3

1

5

∑

… … … …

6 2

3 1

……

2

(6.23)

5

… …

1

… …

(6.24)

……

(6.25)

Then, the probability of state can be computed using

73

(6.26)


After determining all probabilities of states and their tunneling rates, the current passing through single electron transistor can be computed using ∑

Γ

Γ

(6.27)

The details of our model in steps are described by simple flow chart as shown in Fig. (6.12).

74


Start

⁄2

∆ ∆

Γ

,

0

⁄2

No

Yes

∆F

Modeling and Simulation of Single Electron Systems ...

Modeling and Simulation of Single Electron Systems ...

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