Modeling of FPGA and memory using AMBA AHB for DSP ... - IJIRT

© June 2015 | IJIRT | Volume 2 Issue 1 | ISSN: 2349-6002

Modeling of FPGA and memory using AMBA AHB for DSP applications Supreetha M, Kiran Kumar V.G P.G. Student, Department of Electronics & Communication Engineering, SCEM, Mangalore, India Associate Professor, Department of Electronics & Communication Engineering, SCEM, Mangalore, India Abstract- The recent trends in the advancement of SOC chips along with the reusable IPs has led to the high demand of SOC in the market because of less cost and reduction in the time to market period. This demand has given rise to an issue of interfacing these IPs. The interface between the IPs is very important for the proper communication. The on chip bus of the SOC is required to provide high bandwidth to allow multiple parallel operations. The AMBA AHB bus is widely used by most of the SOC designers because of its simplicity and its better architecture with low power. This project details the usage of AMBA AHB protocol for the transfer of image which can be used for the DSP applications. Index Terms- Xilinx ISE, simulink, system generator, spartan 6

I. INTRODUCTION The specification for an on-chip communication standard for designing high-performance microcontrollers is the Advanced Microcontroller Bus Architecture. The classic System-on-Chip (SOC) design consists of many different IP cores linked together with well refined on-chip bus communication architectures, which results in the great impact on the systems performance. Several communication architectures being used in the industries are AMBA, PI-bus, Core Connect, Wishbone, Avalon etc. The standard interface specification which helps to make sure about the compatibility between different IP components provided by diverse design vendors is the AMBA. The high-performance system backbone bus (AMBA AHB or ASB), that is capable of maintaining the external memory bandwidth is contained in an embedded microcontroller involving AMBA. The high-bandwidth interface between different elements which are concerned in the different transfers is provided by the AHB bus. To access low peripheral devices present on high performance bus there is an availability of the AHB

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to APB Bridge. For APB bus, APB Bridge is the only master. The figure below shows the AMBA based microcontroller system. The AMBA, defined by ARM, is the often used open standard for the onchip bus system consisting of the high performance system backbone bus (AMBA AHB) which is capable of sustaining the external memory bandwidth on which the on-chip memory, CPU exist. The capability to provide the high bandwidth interface between the components concerned in majority transfer is involved in this bus. There are 3 different buses defined in the AMBA specification:  Advanced System Bus (ASB)  Advanced High Performance Bus (AHB)  Advanced Peripheral Bus (APB). All the structural configurations, signals, transfer modules for the ASB, AHB, APB are defined by AMBA specification.

Figure 1 : Typical AMBA system

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© June 2015 | IJIRT | Volume 2 Issue 1 | ISSN: 2349-6002 Advanced System Bus (ASB) The ASB specification defines the high performance bus that can be utilized in the designing high performance embedded microcontrollers with 16 and 32 bit. The AMBA ASB supports the wellorganized connection of memories that are on-chip, processors and the interfaces of external memory with low-power peripheral macrocell functions. The capability of supporting multiple bus masters is provided by the pipelined high performance ASB. The fundamental flow of bus operation is as follows:  The bus access granted to the master is determined by the arbiter.  The transfer is initiated by the master upon the permission granted.  The high order address line is used by the decoder to select the bus slave.  The data is transferred between the master and slave after the slave provides the response to the bus master.

Advanced Peripheral Bus(APB) The interfacing any peripheral requiring low bandwidth, not requiring the high performance of a pipelined bus then the AMBA APB can be used. The APB which is a part of AMBA has been optimized to have reduced interface complexity and to use minimal power. It is feasible to incorporate APB to several designs easily with the following advantages.  Can be used for low speed devices as peripheral bus  Can be bridged to system bus  It is synchronous  Supports single master and is nonpipelined. Advanced High Performance Bus (AHB) The new generation AMBA bus that is capable of providing the high performance system bus by supporting multiple masters and high bandwidth operation is the AHB. The AMBA AHB is able to implement features required for high performance and hence the AHB is chosen to transfer the image in this project. The FSM for the design is shown in the figure below.

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Figure 2: FSM for proposed design II. LITERATURE SURVEY Over past years a lot of communication architecture standards for bus have emerged to gear up the SOC integration and also to promote IP reuse over several designs. The bus based communication architecture standards define not only the interface between the bus architecture and components but also defines the bus architecture that implements the protocol used for data transfer. Several SOC architecture standards give the designers the freedom to implement the bus architecture in one of numerous ways. Numeral development in the field of on-chip bus based communication architecture standards are being done from the early 1990s to handle the communication requirements of the forthcoming SOC designs. ARM Microcontroller Bus Architecture (AMBA), IBM Core Connect, OpenCores Wishborn and Altera Avalon are some of the most popular bus architecture standard that are being used now-a-days. In the paper authored by Rishabh Singh Kurmi, Shruti Bhargava, Ajay Somkuwar [1] they demonstrated the working of AMBA-AHB bus and the coding has been carried out using VHDL. Here the main aim was to implement the AMBA AHB protocol using burst technique and verify the functionality using simulation results. In the paper [2] by Pravin S. Shete, Dr. Shruti Oza, involves design of the efficient AMBA AHB master by developing a FSM and has been implemented it using verilog HDL.

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© June 2015 | IJIRT | Volume 2 Issue 1 | ISSN: 2349-6002 In [3] by Shraddha Divekar, Archana Tiwari, the multilayer AMBA AHB bus is designed and implemented using Xilinx simulator and Spartan family FPGA and has said that the AMBA AHB bus provides the flexible system structure. The paper [4] authored by Dr.A.S.Hiwale, Mrs.Bhavana L. Mahajan, Prof.G.D.Salunke, Mrs.Kshitija S.Patil, in this paper the design architecture is coded using VHDL in Xilinx platform. The author has finalized the best suited algorithm for the implementation of arbiter in AMBA AHB bus. The paper[6],by Mohammed Vayada, A.C.Suthar, G.R.Kulkarni, C.B.Patel, in this paper they have presented the basic idea how image processing can be done in model based approach, they have demonstrated some of the image processing application which is done under SIMULINK and how this can be implemented using Xilinx System Generator (XSG). In this paper, they have shown how image read and enhance of image like gray scale image. III. AHB OPERATION The bus master has to be granted with the access to the bus before the AMBA AHB starts the transfer. In the beginning all masters are essentially required to assert a request signal to an arbiter, after which the arbiter will indicate when the master will obtain the bus grant. The decision to grant the access to bus is done using some arbitration mechanism like priority based or round robin mechanism etc. Master starts the transfer by first driving an address and control signals once the bus has been granted. The information about an address, width and direction of the transfer, burst transfer information if the transfer forms the part of the burst is provided by the address and control signals. AHB involves two different forms of burst transfers, they are  INCREMENTING: this is not supposed to wrap at address boundaries  WRAPPING: This is supposed to wrap at the address boundaries. Every transfer consists of two phases:  Address and control cycle phase  Data phase There is no possibility of extending the address phase and thus the slaves has to sample the address and control signals during this phase itself. It is possible to extend the data phase by using the HREADY signal . When HREADY = LOW wait

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states can be inserted in between transfer and HREADY = HIGH indicates the transfer completion. A master has to complete all the data transfers in a particular burst during normal operation prior to granting the access of bus to another master by an arbiter. IV. SIMULINK AND SYSTEM GENERATOR MATLAB is broadly used as interactive software for performing arithmetical computations. Many of the powerful operations is performed by making use of the available MATLAB commands. The one of the additional MATLAB toolbox that helps in modelling, simulating and analyzing the systems from within a graphical environment is the Simulink. Simulink has gained popularity among engineers and researchers and has the ability to design and verify hardware implementation from within the same software environment. System Generator was developed by the Xilinx, which enables the utilization of the Math works model-based simulink design environment for FPGA design. While working on the system generator past knowledge about the Xilinx FPGAs and even the RTL design methodologies are not essential. By utilizing a Xilinx specific blockset designs can be captured in the DSP friendly Simulink modelling environment. In order to create FPGA programming file, the entire downstream FPGA implementation steps together with synthesis and place and route will be automatically performed. V. RESULT AND ANALYSIS As mentioned earlier the software design platform used are MATLAB R2012a with Simulink from MathWorks, system generator 14.5 for DSP and ISE 14.5 from Xilinx using Spartan 6 FPGA.

Figure 3: Transfer of image to slave 1

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© June 2015 | IJIRT | Volume 2 Issue 1 | ISSN: 2349-6002 AMBA- AHB is studied and data sent to the slave in this project is a image which has been transmitted successfully using AMBA-AHB protocol by using system generator. The future scope of this project would be implementation of the required processing on the corrupted image as per the applications involved. REFERENCES

Figure 4: Transfer of image to slave 2

Figure 5: Timing details VI. CONCLUSION AND FUTURE SCOPE This project deals with the fact that number of memory elements can be accessed simultaneously by using AMBA-AHB protocol. Here the minimum period obtained is 0.767ns and can be considered as the better result. Since the AMBA protocol is independent of technology it is possible to use reusable peripherals and macrocells across range of ICs. The basic commands, operation of

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[1]“Design of AHB Protocol Block for Advanced Microcontrollers” by Rishabh Singh Kurmi, Shruti Bhargava, Ajay Somkuwar, [2]“Design of an Efficient FSM for an Implementation of AMBA AHB Master” by Pravin S. Shete, Dr. Shruti Oza, [3] “VLSI Design of Multichannel AMBA AHB” by Shraddha Divekar, Archana Tiwari, [4]“Implementation of AHB protocol using FPGA” by Dr.A.S.Hiwale, Mrs.Bhavana L. Mahajan, Prof.G.D.Salunke, Mrs.Kshitija S.Patil, [5] “AMBA AHB Protocol”, by ARM Co, [6] “Xilinx system generator for simulink” by Xilinx Systems, tutorials [7]“Hardware Software co-simulation for Image Processing Applications” by Mohammed Vayada, A.C.Suthar, G.R.Kulkarni, C.B.Patel, AUTHORS BIOGRAPHIES Ms. Supreetha M, receive B.E degree in Electronics and Communication Engineering from Srinivas Institute of Technology in 2013 and currently pursuing M.Tech in VLSI & Embedded systems in Sahyadri College of Engineering & Management, Mangalore. Mr.Kiran Kumar.V.G has done M.Tech in Microelectronics from NMAMIT, Nitte. He had secured 3rd rank in M.Tech (Microelectronics & control systems) in V.T.U. he has got 11 years of experience in teaching profession.

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