Modeling the Electromagnetic Emission of a Microcontroller ... - LATTIS

TEMC-241-2006.R1

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Modeling the Electromagnetic Emission of a Microcontroller Using a Single Model Cécile Labussière-Dorgan, Sonia Bendhia, Etienne Sicard, Member, IEEE, Junwu Tao, Henrique Jorge Quaresma, Student Member, IEEE, Christophe Lochot and Bertrand Vrignon

Abstract — This paper presents a methodology for building an integrated circuit behavioral model that enables the prediction of its electromagnetic emissions up to several GHz. The model, built upon S-parameter characterization and conducted emission measurements, is used to predict the electromagnetic emissions of a commercial 16-bit microcontroller. The emission measurements are performed according to several EMC standards, namely 1Ω/150Ω, surface scan and TEM/GTEM method, and their results show an excellent fit with model predictions.

TABLE I IEC 61697: MEASUREMENT OF ELECTROMAGNETIC EMISSION (1MHZ1GHZ) Standard

Description

IEC 61697-1

General and definitions TEM cell and wideband TEM cell (GTEM) – radiated emission Surface scan method – radiated emission 1Ω/150Ω – differential conducted emission Workbench Faraday cage (WBFC) – common conducted emission Magnetic probe – radiated emission Mode-stirred chamber – radiated emission

IEC 61697-2 IEC 61697-3 IEC 61697-4

Index Terms — integrated circuit, electromagnetic compatibility, microcontroller, measurement standards, conducted emission, radiated emission, integrated circuit emission model (ICEM).

I. INTRODUCTION

W

ITH the continuing trend towards increased integration of varied and complex electronic functions in modern vehicles, quarantining the electromagnetic compatibility (EMC) of automotive electronic systems is a great challenge, all the more so that their reliability is vital to the safety and security of passengers. Although automotive EMC engineers have traditionally focused their efforts on the design of printed circuit boards (PCB), shielding and cabling, it is the integrated circuits (IC) – and in particular microcontrollers – that are often considered as the main source of electromagnetic interference (EMI) [1]-[2]. Indeed as the integration density increases and the IC operating frequency continues to rise, faster and stronger current peaks are generated by the simultaneous switching of millions of

Manuscript received October 5, 2006; revised July 2, 2007 C. Labussière-Dorgan was with Freescale Semiconductor, Technology Solutions Organization, Toulouse, France. She is now with the French Ministerial Delegation for Armament (DGA-CEAT), Toulouse, France. B. Vrignon is with the Technology Solutions Organization of Freescale Semiconductor, Toulouse, France. S. Bendhia and E. Sicard are with the National Institute of Applied Sciences, Toulouse, France. J. W. Tao is with the National Engineer School of Electronics, Electrical Engineering, Hydraulics, Computer Sciences and Telecommunications, Toulouse, France. H. J. Quaresma is with the Instituto Telecomunicacoes/IST, Lisbon, Portugal. C. Lochot was with Freescale Semiconductor, Technology Solutions Organization, Toulouse, France. He is now with the Electric Department of Airbus, Toulouse, France.

IEC 61697-5 IEC 61697-6 IEC 61697-7

Status Standard Standard Technical Report Standard Standard Standard New proposal

transistors at the digital core level. These transient currents escape from the IC through silicon tracks, bonding wires and the package lead frame. Then, they propagate through PCB tracks that may act as unwanted antennas, and flow to other semiconductor devices, potentially disrupting their normal operation. Thus, EMC performance has become a criterion of choice among competing microcontrollers fulfilling the same function. Over the past few years, several measurement methods for characterizing the emission of an integrated circuit [3] or its immunity to electromagnetic disturbances [4] have been standardized by international regulatory committee. The standards related to emission measurements are given in Table I. Based on such IC-level measurements, the automotive EMC engineer is able to compare microcontroller performance and anticipate the use of decoupling components or shielding structures that will ensure EMC compliance at an equipment level. Similarly in the simulation domain, several models have been proposed for describing the EMC behavior of an integrated circuit in a standard way. The main purpose of this approach – from a semiconductor manufacturer viewpoint – is to provide automotive customers with a non-confidential model of the IC that can be re-used for EMC simulations at the PCB level. The first significant contribution to the EMC modeling of components came from IBIS (Input/Output Buffer Information Specification) [5], developed in the early 90’s to describe in a non-confidential way the electrical performance of the input/output (I/O) structures of an integrated circuit. However, the IBIS model does not account for high-frequency currents induced in the IC supply network

TEMC-241-2006.R1

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VDDX1 VSSX1

VSSA

VDDA VDD1 VSS1

VSS2 VDD2

VDDX2 VSSX2

VDDR2 VSSR2 portA

VSSR1 VDDR1

VSSPLL VDDPLL

Fig. 1. Pinout of the microcontroller under test [15], with the power and ground pins and an 8-bit I/O port highlighted.

by switching of the I/O buffers and by internal activity of the component, which are the main sources of IC parasitic emissions. In the last ten years, several other models have been proposed for predicting component emissions [1]. In Japan, a proposal called IMIC (Interface Module for Integrated Circuits) was put forward by a group of industrial and academic partners [6]. At the same time, research was initiated in France to establish the foundations for a standard model. Based on simple component characterization, a generic model (ICEM: Integrated Circuit Emission Model) applicable to complex ICs such as microcontrollers, was arrived at [7]. In [8], Lochot and Levant applied this methodology to a commercial component in order to predict the results of conducted emission measurements for the 1Ω/150Ω standard with reasonable accuracy. In [9], Vrignon presented the ICEM model of a test-chip designed in CMOS technology, showing good agreement with on-chip measurement results. Another model from Japan, LECCS (Linear Equivalent Circuit and Current Source), has been demonstrated in conjunction with analytical techniques for performing high-speed EMC simulations at the PCB level [10]-[11]. These proposals have been assessed by international regulatory committees, with the objective of setting up a single standard model that would draw upon the best features of each one. But thus far to our knowledge, no work has been published in which a single model applies also to the radiated emission measurement standards. Engel proposed a specific methodology to predict IC radiation in the TEM cell [12]. The component is modeled as the combination of elementary structures – loops, monopoles and dipoles on the same scale as the IC and its package – whose radiation resistance in the cell can be computed. Kralicek et al. introduced new modeling based on a multipole expansion of the electromagnetic field radiated by the IC [13]-[14]. Dedicated to simulations for system analysis, this model allows fast and accurate EMC simulations at the PCB level, but no information is given on how to compute the near-field radiation from the IC. The objective of this paper is to demonstrate that a single EMC model, built according to the ICEM methodology, can also accurately predict the International Electro-technical Commission (IEC) emission standards measurement results, both for conducted and radiated modes of a commercial integrated circuit. For this purpose a 16-bit microcontroller

Fig. 2. Picture of the test-board designed for the EMC characterization of the microcontroller [15].

commonly used in automotive applications will be considered. In the following sections, the measurement setup for the microcontroller's EMC characterization is presented (section II), and the methodology applied to build its ICEM model is described (section III). Then, the ICEM model is used to predict the results of three emission measurements standards: the 1Ω/150Ω conducted emission (section IV), the TEM cell approach (section V) and finally the surface scan method (section VI). Comparisons between simulation and experimental results are made throughout these sections, validating the complete modeling methodology. II. TEST IC AND EXPERIMENTAL SETUP In many publications dealing with EMC at the IC level, the device under test is a test-chip specially designed and manufactured for the particular experiments. In contrast, this work is focused on a commercial component, the S12X Freescale Semiconductor 16-bit microcontroller widely used in the most recent automotive electronic systems [15]. This IC is fabricated in 0.25µm CMOS technology. It has 8 pairs of power and ground pins to supply the I/O ports, the analog-todigital (A/D) converter, the oscillator, the phase-locked-loop (PLL) and the digital core. The pinout of the microcontroller mounted in a TQFP (Thin Quad Flat Patch) package with 144 pins is presented in Fig. 1, where the power, ground pins and, one of the 8-pin I/O ports (portA) are highlighted. A specific test board to house the microcontroller and all the external components and supplies required for its operation was designed and used in the experimental EMC characterization of the microcontroller [16]. A picture of this test-board is presented in Fig. 2. The board has 4 layers and 10 cm side length, allowing it to fit in the TEM cell aperture for radiated emission measurements. In addition, some SMA connectors are mounted on the board for conducted emission measurements. Three types of emission measurements are performed: TEM cell measurements, 1Ω/150Ω characterization and near-field scanning. More details on these individual setups are provided in the next sections. Since the microcontroller EMC activity strongly depends on the operations being executed, three elementary program scripts are developed and detailed in Table II. In the case of the CORE and PLL programs, only internal activity in the microcontroller exists. For the first program, the PLL is off, so the clock frequency is set to 8

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TABLE II TEST-PROGRAMS DEVELOPED FOR EMC MEASUREMENTS Programs name

TABLE III FUNCTION OF THE POWER AND GROUND PINS OF THE MICROCONTROLLER

Description

Supply pins

PLL off Bus clock frequency: 4 MHz Internal activity: RAM writing PLL on, frequency set to 64 MHz Bus clock frequency: 32 MHz Internal activity: RAM writing PLL on, frequency set to 64 MHz Bus clock frequency: 32 MHz External activity: 0x00/0xFF on port A Switching frequency: 2.27 MHz

CORE

PLL

PORT

Digital ICEM Model

VDD1/VSS1

2.5V

VDD2/VSS2

2.5V

VDDA/VSSA

5V

VDDR1/VSSR1

5V

VDDR2/VSSR2

5V

VDDX1/VSSX1

5V

VDDX2/VSSX2

5V

Analog ICEM Model VDDa

digital IA

analog IA

VSSd_int

analog PDN

VSSa

VDDPLL/VSSPLL

VSSa_int

isolation

VSSI/O_int

digital PDN

VDDI/O I/O IA

VDDd

Nominal VDD value

VSSd

I/O PDN

VSSI/O

I/O ICEM Model

Fig. 3. Example of ICEM architecture according to [7].

MHz by an external quartz. For the second one, the PLL is activated and configured to deliver a 64 MHz clock frequency. In the case of the PORT program, the 8-pin portA I/O is configured to deliver square wave signals in phase. The period of these output signals is 440 ns, which corresponds to a switching frequency of 2.27 MHz. For each emission measurement, one of these three program scripts is loaded into the microcontroller and executed in loop during the whole measurement. III. BUILDING THE ICEM MODEL OF THE MICROCONTROLLER According to the IEC standard [7], the basic architecture of the ICEM model is composed of two sub-models: 1) The Internal Activity (IA) sub-model is used to describe the internal activity of the analog, digital and I/O structures. An IA sub-model is typically a current source that can either be expressed in the time domain or in the frequency domain. A standard waveform (such as periodic triangular or exponential form), a measurement result described as piecewise functions, or a simulation file can be used. 2) The Passive Distribution Network (PDN) sub-model describes the electrical structure involved for powering the internal functions integrated on the chip such as a voltage regulator or a PLL. It corresponds to the impedance network seen between the VDD and ground pins; which consists of internal power supply rails (on-chip metal tracks, internal decoupling capacitances between power and ground tracks…)

2.5V

Description Internal power and ground generated by the internal voltage regulator. Internal power and ground generated by the internal voltage regulator. Operating voltage and ground for the analog-to-digital (A/D) converter, and reference for the internal voltage regulator. External power and ground, supply to some I/O pins and to the internal voltage regulator. External power and ground, supply to some I/O pins. External power and ground, supply to some I/O pins. External power and ground, supply to some I/O pins. Operating voltage and ground for the phase locked loop (PLL), and internal power and ground generated by the internal voltage regulator.

and the IC package (leads and bondings). The PDN is also used to describe how the I/Os are powered, and how they are connected to the other parts of the chip and to the PCB. Fig. 3 gives an example of a complete ICEM architecture composed of three basic ICEM models: one is used to express the EMC activity of the IC’s digital block, the second corresponds to the analog block, and the third model describes the I/O EMC activity. The block named isolation is included to model the parasitic coupling through the substrate between the different ground signals. A. Modeling the Passive DC Supply Distribution Network The microcontroller power and ground pins form a complex network. The functions of the DC supply pins are detailed in Table III. The internal voltage regulator is supplied through the VDDR1 pin by an external 5 V source, and delivers 2.5 V to the digital core and the PLL. VDD1 and VDD2 are not connected to any external voltage source: they are connected to the internal 2.5 V supply network of the core, and used only to add external core decoupling capacitances. VDDPLL plays exactly the same role for the PLL. Some of the I/O ports – portA for example – are supplied through the VDDR1 and VDDR2 pins, while the others are fed by VDDX1 and VDDX2. The model of the IC passive network is usually built with lumped R, L and C elements whose values are computed from electrostatic formula and tuned to fit with the results of ohmmeter or impedance-meter measurements. But at high frequencies, extensive parasitic coupling occur inside the IC, both at package and die level, which may be missed with such basic measurement methods. Thus, S-parameter measurements were performed to accurately characterize the impedance network up to several GHz. Using this technique, a preliminary SOLT (Short-OpenLoad-Thru) calibration is performed first to remove the effects of connectors and coaxial cables connecting the network

TEMC-241-2006.R1

measurement plane (SOLT calibration)

4

DUT plane

DUT plane

measurement plane (SOLT calibration)

schematic

has

a lines type 1

strong

link

lines type 2

to network analyzer port 2

to network analyzer port 1 device under test (DUT)

transition line

Fig. 4. Representation of a typical board used for the S-parameter characterization of surface-mounted components.

analyzer to the device under test (DUT) – shifting the measurement plane to the tips of the coaxial cables, Fig. 4. However, for surface-mount components such as microcontrollers, a PCB interconnect is required to interface the coaxial connector with the non-coaxial device. Therefore, the measured S-parameters include both the effect of the DUT and the transmission line effect of the PCB interconnections. To remove the latter effect, the TRL (Thru-Reflect-Line) calibration technique [17]-[18] is used. Fig. 5 shows a picture of the test-board manufactured with a Teflon substrate. Due to the small IC pitch – 0.5 mm between adjacent pins – two types of micro-strip lines were used to connect the 8 pairs of supply and ground pins to the on-board SMA connectors. Each type of PCB interconnection requires dedicated TRL calibration features. During the Passive Distribution Network (PDN) characterization measurements, no program is running inside the microcontroller, but the internal voltage regulator is activated. All the VDD pins are connected to an external 5 V source, except VDD1, VDD2 and VDDPLL that are internally set to 2.5 V. A set of two-port measurements were carried out in order to characterize the whole impedance network: VDDto-VDD, VSS-to-VSS and also VDD-to-VSS path. Where required, DC bias is applied through the network analyzer port using internal bias tees. To prevent wave reflection at the other ports of this multi-port network, all the non-connected tracks are terminated by a broadband 50 Ω matched load [19]. Some DC measurements are also performed on this board with an ohmmeter to quantify the amount of substrate coupling between the different ground pins, and to provide information about the metal connections between the VDD rails. Details on the measurement procedure up to 10 GHz are provided in [20]. Since most ICEM users are more familiar with lumped-element modeling than with S-parameters, an RLC equivalent model is developed and tuned to fit with all the measured S-parameter matrices up to 1 GHz, for both magnitude and phase. Both S11 (input reflection) and S21 (transmission) are worth of interest. The S11 information is translated into impedance Z(f) from which R, L and C elements are tuned manually. The first order coupling (substrate, rail-to-rail crosstalk) is extracted from S21 parameters again by manual fit. The resulting lumped-element model for the PDN is presented in Fig. 6. The circuit

SMA connectors microcontroller under test

Fig. 5. Picture of the test-board developed to perform the S-parameter characterization of the microcontroller passive distribution network.

with the PDN layout of the chip and physical on-chip decoupling. Although we deduced the R, L, and C elements from multiple S-parameters measurements, similar values may be obtained by using R, L and C post-layout extractor as previously stated in [9]. For example, the isolation model between the VSSPLL and VSS consists of a resistance, R_VSS_to_VSSPLL, extracted from DC substrate extraction. The equivalent serial inductance, L_VSS_to_VSSPLL, accounts for the connector distance between ground pins. The capacitance C_VSS_to_VSSPLL is the sum of the inter-metal capacitance and back-to-back protection diodes. However, it is very difficult to fit all the model parameters in both amplitude and phase as the number of R, L and C elements are very high. As an example, the measured and simulated S-parameter coefficients for the VDD1-to-VSS2 path are compared in Fig. 7-a, showing good agreement over the whole frequency range. In this figure, S11 and S22 have a resonance around 750 MHz due to the lead self resonance, e.g. L_lead_VDD1 and C_coupl_VDD1 for S11 and L_lead_VSS2 and C_coupl_VSS2 for S22. The proposed model is verified up to 1 GHz. However the model is valid up to 3 GHz as it fits well with Z-parameters measurements performed up to 10 GHz in Fig. 7-b. Above this frequency, dominant effects such as lead coupling and skin effect strongly impact the PDN [20].The other results are not presented here, but they fit in the same way. In the model, some inductive coupling coefficients are added between closest leads, the values of which are computed from electromagnetic simulations as described in more details in Section V-B. Moreover, it must be pointed out that this model does not include modeling of the internal voltage regulator. In accordance with DC measurement results, VDDR1 rail (that supplies the voltage regulator) is assumed to not be connected to VDD1, VDD2 and VDDPLL tracks (that are internally supplied by the voltage regulator). The only interaction between these signals is assumed to be due to parasitic coupling through the common silicon substrate.

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Fig. 6. ICEM model of the microcontroller’s passive distribution network (PDN).

A. Modeling the Internal Activity As shown in Fig. 6, a current source is added between the VDD1-VDD2 and VSS1-VSS2 rails in order to model the current peaks generated in the supply network by the IC internal activity. To approximate the actual current waveform, a piece-wise linear (PWL) current source is used. Particular attention has to be given to the definition of this current source, whose waveform is partially dependent on the program running inside the microcontroller.

Fig. 8 presents the source signal time waveform used for the CORE program. The period is set to 246 ns to model the 4 MHz frequency of the bus clock (i.e. half the clock frequency). Some secondary current peaks are included to model the 16 MHz internal activity on the RAM memory that is twice the clock frequency [15]. According to previous theoretical studies carried out to estimate the current consumption of a 16-bit microcontroller from the same family – the HC12 [21] – the magnitude of the peaks is initially set to

TEMC-241-2006.R1

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S11 phase [°]

900

current magnitude [mA]

S11 magnitude [dB]

measurement simulation

246 ns 700 500 300

61.5 ns 100 -100 200

frequency [Hz]

frequency [GHz]

S21 magnitude [dB]

S21 phase [°]

300

400

time [ns]

500

600

Fig. 8. Time waveform of the current source modeling the microcontroller internal activity in the case of CORE program. VddR1

W=540µm L_package 7n

Clock_signal

frequency [Hz]

frequency [GHz]

S22 magnitude [dB]

S22 phase [°]

W=180µm

R_package 1 ohm

L_pcb 20 n

C_package 1p

C_pad 1p

R_pcb 2 ohm C_load 10 p

C_pcb 5p

VssR1

Fig. 9. Non-confidential model of one pin of portA I/O. Vdc 5V Conducted emission Measurement setup

frequency [Hz]

frequency [GHz]

Clock_signal

W=540µm L_package R_package 7n 1 ohm

L_pcb 20 n

R_pcb 2 ohm

R_120 120 ohm

C_6n8 6.8 n

(a) W=180µm

C_pad 1p

C_package 1p

C_pcb 5p

R_51 51 ohm

R_SA 50 ohm

Fig. 10. Model of the experimental setup for conducted emission measurement on portA pin.

(b) Fig. 7. (a) S-parameter coefficients (magnitude and phase) for the VDD1-toVSS2 path: measurement vs. equivalent model. (b) Impedance between VSS1 and VSS2 pins in terms of frequency: measurement vs. equivalent model.

500 mA (100 mA for the secondary emission peaks). These values are then adjusted to 725 mA and 200 mA respectively in order to accurately fit with conducted emission results (see Section IV). In the same way, the rise time, peak duration and fall time are respectively tuned to 4 ns, 1 ns and 4 ns. These values play a significant role in the precise modeling of highfrequency emission peaks. In the case of the PLL program, the period is modified to represent the 64 MHz clock frequency, and accordingly the magnitude of the current peaks is slightly increased to take into account the PLL activity. Contrarily, the magnitude of the current peaks related to the PORT program is noticeably lower compared to the CORE and PLL programs, since in this case there is no RAM writing activity. The piece-wise linear current source is a first-order approximation of the actual current waveform. A more complex definition – based for example on VHDL simulations of the current consumption – or even full analog simulations may be used to improve the modeling at high frequency.

B. Modeling the I/O Ports In the case of the PORT program, portA I/O is activated, which significantly contributes to the microcontroller's overall emission. As a consequence, the model of the I/O has to be combined with the ICEM model of the power distribution network. The model used for describing one pin of this 8-pin port is presented in Fig. 9. The output buffer is modeled with a CMOS inverter driven by a 2.27 MHz clock signal with 7 ns rise/fall time. These values are set according to the voltage measured on portA pins with a high-impedance probe connected to an oscilloscope. The NMOS and PMOS transistor models and parameters are tuned to fit with the I/O’s I-V characteristic given in the IBIS model of the microcontroller [1]-[22]. The MOS structures are connected to the VDDR/VSSR network that supplies this I/O port. Lumped elements are added to model the package, the PCB tracks and the 10 pF capacitive load mounted on the board. These values do not necessarily reflect the actual technology of the microcontroller, but they allow the I/O port to be described in a non-confidential way. Conducted emission measurements are carried out on portA pins to validate this model. For comparison with experimental results, additional elements corresponding to the measurement setup are added to the portA model. As shown in Fig. 10, the 10 pF load is replaced by the appropriate resistors and capacitors of the measurement setup, and the spectrum analyzer is represented by a 50 Ω termination. The result of the electrical simulation, Vmeas, is expressed in the frequency

TEMC-241-2006.R1

7

115

Measurement Simulation

95 85 75 65 55

Measurement Simulation

85

voltage magnitude [dBµV]

voltage magnitude [dBµV]

105

75

65

55

45

35

45 25

35 1

10

100

frequency [MHz]

1000

Fig. 11. Comparison between the emission spectrum measured on one of the portA pins according to the 1Ω/150Ω standard and the results of simulation.

1

10

100

frequency [MHz]

1000

Fig. 13. Comparison between the emission spectrum measured on VDD1 pin and the results of simulation, CORE program being executed.

Passive Distribution Network Conducted emission Measurement setup R_49 C_220 49 ohm 220 n

V_meas

R_SA 50 ohm

R_1 1 ohm

Package C_VDD1 15 p

L_pack_VDD1 6.3 n

C_pack _VDD1 6p

L_VDD1 2n

R_VDD1 1 ohm C_decoupl 7n R_decoupl 0.05 ohm C_VSS1 15 p

L_pack_VSS1 6.2 n

C_pack_ VSS1 10 p

Fig. 14. TEM cell measurement setup. To Internal activity model

L_VSS1 2.2 n

R_VSS1 0.75 ohm

Fig. 12. Lumped-element modeling of the conducted emission setup on VDD1 pin according to 1Ω/150Ω standard.

domain after performing a Fast Fourier Transform (FFT) with a Hanning window function. In Fig. 11, the computed spectrum is compared with the spectrum analyzer measurement. Excellent agreement is observed between measurement and simulation, except in the 100 MHz-350 MHz band, where the model slightly overestimates the experimental results. The difference between the two plots reaches 10 dB within that interval and is attributed to the capacitors and resistors mounted on the PCB which start to deviate from their assumed ideal behavior. Furthermore, noticeable amplitude shifts occur between the computed and measured spectrums at high frequencies when using different windowing functions and different sampling rates. IV. MODELING OF CONDUCTED EMISSION MEASUREMENTS The test board of Fig. 2 was also designed to allow conducted emission measurements on the VDD1 pin according to the 1Ω/150Ω method [23]. The conducted emission spectrum is obtained with a spectrum analyzer connected to an output SMA connector on the test board. This experimental setup can be easily modeled by adding resistive and capacitive elements to the ICEM model of the microcontroller, as presented in Fig. 12. In Fig. 13, the emission spectrum measured with the CORE program running in a loop is compared with simulation results. Once the parameters of the current source (magnitude, rise/fall time…) are slightly tuned, a good fit to the measured results is obtained. This means in particular that the decoupling network between the digital core power and

ground pins (represented in the model by a 7 nF capacitor in series with a 50 mΩ resistor) is properly accounted for in the ICEM model. The 7 nF on-chip decoupling capacitor, C_decoupl, appearing in Figs. 6 and 12, consists of 2 nF intrinsic gate capacitance and added 5 nF capacitance built using all possible technology options: filler capacitance, metalinsulator-metal capacitance. This 5 nF capacitance induces a core oversize estimated to 2%. The Equivalent Serial Resistance (ESR) is particularly low as the decoupling capacitance is implemented very close to the current source. Possible ways to extract this ESR value include full layout extraction using dedicated CAD tools or approximations based on power floor plan. V. MODELING OF TEM CELL MEASUREMENTS A. Description of TEM Cell Measurement Setup The TEM-cell method is the standard technique for measuring the total radiation from an IC [24]. The TEM cell is an expanded rectangular waveguide with an inner conductor called the septum, having characteristic impedance of 50 Ω, and terminated by two tapered ends matched to 50 Ω coaxial connectors. Due to the shape of its cross section, a transverse electromagnetic (TEM) wave can propagate in the cell, while higher order modes are evanescent up to 1 GHz [25]. The test board is fitted in an aperture of the TEM cell outer wall, with the IC facing inside the cell. One of the ports of the TEM cell is connected to the spectrum analyzer, while the other port is terminated with a 50 Ω load. The measurement setup is presented in Fig. 14. As the IC is activated, its radiation excites the TEM mode that propagates towards the extremity of the cell. The voltage signal measured at the cell output with the spectrum analyzer is proportional to the IC electromagnetic emission spectrum. A group of TEM cell measurements were performed to characterize the microcontroller’s radiation for the three test programs and for several orientations of the test board in the TEM cell.

TEMC-241-2006.R1

8 TABLE IV VALUES OF THE LUMPED ELEMENTS COMPUTED FROM 3D SIMULATIONS

microcontroller package TEM cell outer conductor

lead of interest surrounded by two adjacent leads

Self and mutual elements Llead (nH) Lseptum (nH) Clead-septum (fF) k Clead-ground (fF) Cseptum-ground (pF)

“parallel” configuration 5.3 130 2.0 0.080 130 19

“orthogonal” configuration 5.2 130 2.0 0.0023 140 19

“oblique” configuration 7.0 130 3.4 0.077 200 19

TEM cell inner conductor (septum)

gnd

Fig. 15. 3D geometry simulated with an electromagnetic solver in order to quantify the coupling between the TEM cell and the IC package lead frame.

L lead

R lead

C lead-ground

lead

C_septum 19.2 p

R_SA 50 ohm

L_septum1 5n

R septum

C septum-ground L septum

R_load 50 ohm

C_die_septum 50 f

C lead-septum k

septum

L_septum2 5n

Inductive coupling with leads parallel to the wave propagation direction

Inductive coupling with leads parallel to the wave propagation direction

Fig. 17. Final lumped-element model of the TEM cell measurement setup. Fig. 16. Basic lumped-element model extracted from electromagnetic simulations.

B. Modeling the TEM Cell Bench The IC radiated emission is assumed to be mainly due to the flow of transient signals on the package leads that act as miniature antennas. The radiation of the chip itself and of bonding wires is neglected. The interaction between the TEM cell and the leads is quantified with custom FEM code that determines self-elements of the metal parts (lead, septum, and cell armature) as well as the different inductive and capacitive couplings between conductors. Several configurations are studied, with various positions of the lead inside the cell. An example of a simulated 3D geometry is given in Fig. 15, where the lead is parallel to the wave propagation direction inside the TEM cell. To take into account the strong coupling that exists between adjacent pins, the two leads next to the lead of interest are also included. The topology of the equivalent lumped-element model obtained from these electromagnetic simulations is presented Fig. 16, while Table IV lists the values of the elements computed for three configurations: a lead parallel to the wave propagation direction, a lead orthogonal to that direction, and a lead positioned in a corner of the package (corner leads do not have the same dimensions as central leads). The inductances of the leads (from 5.2 to 7 nH) are consistent with the values determined from S-parameter measurements. The TEM cell, i.e. the combination of the septum and the cell outer wall, is represented as a 50 Ω transmission line. Due to the small size of the leads, the very small capacitance representing the lead/septum coupling (a few fF) has no impact on the result of the electrical simulation up to 1 GHz. The resulting lumped-element model of the TEM cell is added to the ICEM model of the microcontroller, as presented in Fig. 17.

Only the global capacitive coupling between the septum and the die ground matters, and it is represented by means of a 5 pF capacitance between the cell inner conductor and VSS1-VSS2 rail. In the case of the PORT program, 1 pF capacitors are added to the TEM cell model to represent the capacitive coupling between the septum and the 5 cm PCB tracks connecting each I/O pin to the 10 pF load mounted on the board. Moreover, according to the results of electromagnetic simulations, the inductive coupling coefficients of the leads in the “orthogonal” configuration are negligible. Finally, the spectrum analyzer input and the TEM cell matched load are modeled with 50 Ω resistances. C. Comparison between Measurements and Simulations With reference to Fig. 17, the voltage signal Vout is taken across the 50 Ω resistor representing the spectrum analyzer. This voltage spectrum corresponds to the spectrum analyzer signal measured at the TEM cell output. A time-domain simulation is performed and the signal is converted to the frequency domain. Fig. 18 presents the radiation spectrum generated by the PLL program, with the microcontroller being positioned in order that VDD1/VSS1 and VDD2/VSS2 leads are parallel to the wave propagation direction inside the TEM cell. Experimental and simulation results have roughly the same shape. Although some secondary emission peaks are not identified by the model (particularly at high frequency), the 5 highest emission peaks detected experimentally are well predicted (Table V), and their radiation levels (except the 5th one) are not underestimated, which is of great importance. In Fig. 19, the radiation results are for the PORT program. The board is positioned so that VDD1/VSS1 and VDD2/VSS2 are in the “orthogonal” configuration. Again, measurement and simulation show good agreement up to 300 MHz. The two

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plots exhibit emission peaks at the 2.27 MHz harmonics, which means that the radiation is mostly due to I/O port activity. The emission levels are accurately predicted up to 300 MHz, but at higher frequencies, emissions are underestimated by the model. This high-frequency discrepancy is partially explained by the use of ideal R, L and C elements for modeling the PCB tracks, by FFT computation errors, and by the fact that the radiation of the chip and bonding wires are not taken into account. However, we assume the error is mostly due to the simplified model for the TEM cell measurement setup. To increase the accuracy of simulations, a higher-order modeling of the coupling mechanism between the IC and the cell, using either a distributed RLC network or an N-port S-parameter matrix, should be employed.

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30 30dB dB Pre-amplifier Pre-amplifier Spectrum Spectrum Analyzer Analyzer

Controller Controller Workstation Workstation

VI. MODELING OF NEAR-FIELD MEASUREMENTS A. Description of the Near-field scan Bench Adapted by Slattery to the problem of the integrated circuits [26], the surface scan method consists in measuring the electrical and magnetic fields radiated above the surface of an IC through the use of miniature probes. This near-field radiation can be linked to electrical phenomena inside the component. For instance, a current flowing through the IC generates a magnetic field above the current path, whereas a voltage signal propagating on an I/O port creates a vertical electrical field above the I/O pins [27]. A report describing this technique and giving some recommendations on the measurement set-up, the shape of the near-field probes and the calibration procedure has recently appeared [28]. The near-field measurement setup is schematically

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presented in Fig. 20. The IC under test is positioned on a table that can be moved automatically in the horizontal plane, with 1 µm mechanical precision. The height of the probe above the package is manually controlled through a micrometric screw. The probe output is connected to a spectrum analyzer through a 30 dB low-noise amplifier. A set of miniature coaxial probes (loops, monopoles and dipoles) allow each component of the electromagnetic field to be captured. A basic calibration technique is used to determine the actual magnitude of the radiated emission: the signal measured with the spectrum analyzer is proportional to the field component captured by the probe. Although more rigorous calibration procedures

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have been developed [29], this technique gives acceptable results for miniature loops [30]. For each test-program, measurements of the different field components are performed at several frequency points. In all measurements, the probe is positioned 250 µm above the microcontroller’s package. The scan area is 23 mm × 23 mm, and a 0.5 mm step size along both the X and Y axes is chosen. B. Modeling the Near-field Emissions Similarly to the TEM cell modeling, the methodology for modeling the near-field measurements consists of combining electrical simulations from the ICEM model with electromagnetic computations. To that end, current and voltage probes are added to the microcontroller’s ICEM model, especially at the location of the lumped elements which model the leads. The signals are computed in the timedomain and a FFT provides the magnitude and phase of the probed currents and voltages at the frequency of interest. The overall simulation flow is represented in Fig. 21. The geometry of a 3D package lead frame, presented in Fig. 22, has been simulated using an electromagnetic solver [31]. In this structure, voltage and current sources are placed at one end of each internal load (i.e. on the chip side), whereas the other lead extremities (at the PCB side) are terminated by matched load to prevent standing-wave phenomena. Once the values of the currents and voltages are defined in this 3D geometry according to the results of the ICEM electrical simulation, an electromagnetic simulation is launched. Based on the finite element method (FEM), the electromagnetic solver computes the near-field radiation generated by signals flowing in the IC’s lead frame. The magnitude of each electromagnetic field component can then be mapped at a given height above the package.

Fig. 24. Intensity graph of the Hz-field component radiated by the IC at 32 MHz when the program PLL is executed – measurement (left) and simulation (right).

Fig. 25. Intensity graph of the tangential magnetic field radiated by the IC at 2.27 MHz when the program PORT is executed – measurement (left) and simulation (right).

C. Comparison between Measurements and Simulations In Figs. 23 to 25, the field mappings computed from the microcontroller’s ICEM model are compared with experimental results. A good fit between simulations and measurements is obtained: not only are the locations of major emission spots well rendered, but the levels of radiation are also accurately predicted by the ICEM model. Fig. 23 shows the mapping of the Hy-field component radiated at 4 MHz when the CORE program is running. The Hy magnitude measured above the IC is proportional to the magnitude of the currents whose paths are collinear to the X-axis direction. Therefore, the field mapping allows the identification of strong currents on the VDD1/VSS1 and VDD2/VSS2 leads, which are the two pairs of supply pins dedicated to external core decoupling. A small magnetic field is also observed above the VSSA lead (the reference ground for the voltage regulator).

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Fig. 24 shows the mapping of the vertical magnetic field (Hz) radiated at 32 MHz for the PLL program. In this case, each current track corresponds to a minimum of Hz field radiation surrounded by two maximums. Hence, the Hz-field mapping highlights two major current paths: VDD1/VSS1 and VDD2/VSS2 leads, supporting the previous results of Fig. 23. Some lower-magnitude currents can also be seen on other VSS tracks. Indeed, at this frequency, the propagation of noise on the entire ground network on the silicon substrate is stronger than at 4 MHz. This substrate coupling phenomenon is modeled in the ICEM model by means of C elements in parallel with the RL networks (Fig. 6). Finally, Fig. 25 presents the total tangential magnetic field radiated at 2.27 MHz when the PORT program is executed. Measurements and simulations have been performed to determine the total tangential field radiated at 2.27 MHz which corresponds to the IO port switching frequency. As seen in Fig. 19, the 2.27 MHz harmonic dominates the measured spectrum. This mapping is obtained by combining the Hx and Hy fields: H tg

( f ,x, y,z ) =

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where f is the scan frequency, and (x,y,z) are the space coordinates of the probe. Notice that this equation induces the following objection: First assume that the magnetic field is linearly polarized with Hx and Hy both equal to 1 for some particular choice of (f, x, y, z). The equation correctly yields H tg ( f , x, y , z ) = 2 . Now suppose that the magnetic field is circularly polarized such that Hy is equal to j and Hx is equal to 1. Then the equation gives an incorrect result of H tg ( f , x, y , z ) = 2 while the correct result would be H tg ( f , x, y , z ) = 1 .

The discrepancy between these two

VII. CONCLUSION This paper has reported a set of investigations on conducted and radiated emissions of a 16-bit microcontroller. The Integrated Circuit Emission model was demonstrated to be a tool suitable for modeling the complete EMC behavior of an integrated circuit. Combined with an appropriate modeling of the measurement bench, the ICEM model allows one to predict the results of emission measurements, both for conducted and radiated modes. Therefore, this model can be used for representing the IC in EMC simulations at the equipment level. This paper also described in detail the methodology adopted for building up the ICEM of an integrated circuit based on experimental data. The passive distribution network is characterized by means of S-parameter measurements, whereas the internal activity is modeled by a current source whose waveform is validated through conducted emission measurements. Finally, the I/O ports are characterized according to the 1 Ω /150 Ω method and can be modeled in a non-confidential way. This experimental technique requires the development of dedicated boards, and it can only be applied once the component has been manufactured. The ultimate goal for IC manufacturers is to be able to predict if an integrated circuit will fulfill the EMC emission standards at an early stage of its design cycle. The authors are currently working on applying this technique to a 32-bit microcontroller, with the aim of forecasting its emission prior to fabrication. ACKNOWLEDGMENTS The authors would like to thank Gérard Bouisse for his precious support on the TRL method and RF board design. The authors also wish to thank Olivier Pigaglio and Alexandre Boyer for their valued help on EMC measurements.

answers is 20 × log10 ( 2 ) ≈ 3dB . This 3 dB error stems from the way that the near field scanning data is processed to extract the magnetic field components rather than being a result of the ICEM model itself. Strong currents can be observed on portA pins, and also on the supply pins of this I/O port, i.e. VDDR1/VSSR1 and VDDR2/VSSR2. The mapping also shows a small current on the VDD1/VSS1 leads. A current of the same magnitude is expected to propagate through VDD2/VSS2 pins, but the radiation due to this small current is masked by the highmagnitude radiation above theVDDR2/VSSR2 leads. Because of the 3D package geometry used for electromagnetic simulations, the radiation above the chip itself can not be computed. Only the radiation from the leads can be visualized. But the same methodology could be applied to the bonding wires and also to the chip, provided that some information about the layout of the microcontroller is available. This would include the bonding and the main internal IC tracks, which could be added to the original 3D geometric representation.

REFERENCES [1]

S. Bendhia, M. Ramdani and E. Sicard, EMC of ICs: Techniques for low emission and susceptibility,, Springer, 2005 [2] M. Coenen, “On-chip measures to achieve EMC” in Proc. 1997 International Symposium on Electromagnetic Compatibility, Zurich, Switzerland, pp. 31-36. [3] International Electro-technical Commission, IEC 61967, “Integrated Circuits, Measurements of Conducted and Radiated Electromagnetic Emission”, 2001. [4] International Electro-technical Commission, IEC 62132, “Integrated Circuits, Measurements of Susceptibility”, 2002. [5] International Electro-technical Commission, IEC 62014-1, “IBIS, Electronic Behavioral specifications of digital Integrated Circuits I/O Buffer Information Specification”, 2003. [6] International Electro-technical Commission, IEC 62404, “I/O Interface Model for Integrated Circuits (IMIC)”, 2003. [7] International Electro-technical Commission, IEC 62014-3, “Integrated Circuits Emission Model (ICEM)”, 2004. [8] C. Lochot and J. L. Levant, “ICEM: a New Standard for EMC of IC. Definition and Examples” in Proceedings of the 2003 IEEE International Symposium on Electromagnetic Compatibility, pp 892-897. [9] B. Vrignon, S. Bendhia, E. Lamoureux, and E. Sicard, “Characterization and modeling of parasitic emission in deep submicron CMOS” in IEEE Transactions on Electromagnetic Compatibility, vol. 47, May 2005, pp. 382-387. [10] H. Osaka, O. Wada, T. Kinoshita, Y. Toyota, D. Tanaka and R. Koga, “Power current modeling of IC/LSI with load dependency for EMI

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[11]

[12]

[13]

[14]

[15] [16]

[17] [18] [19]

[20]

[21] [22]

[23]

[24]

[25]

[26]

[27]

[28]

[29]

[30]

simulation” in Proceedings of the 2003 IEEE International Symposium on Electromagnetic Compatibility, vol. 1, pp 16-21. O. Wada et al., “High-speed simulation of PCB emission and immunity with frequency-domain IC/LSI source models”, in Proceedings of the 2003 IEEE International Symposium on Electromagnetic Compatibility, vol. 1, pp 4-9. A. Engel, “Model of IC emissions into a TEM cell” in Proceedings of the 1997 IEEE International Symposium on Electromagnetic Compatibility, pp 197-202. P. Kralicek, W. John and H. Garbe, “Modeling electromagnetic emission of integrated circuits for system analysis” in Proc. of the 2001 Design, Automation and Test Conference and Exhibition, pp 336-340. P. Kralicek, W. John, R. D. Smedt, K. Vervoort and H. Garbe, “A voltage controlled emission model of electromagnetic emission of IC for system analysis” in Proceedings of the 2001 IEEE International Symposium on Electromagnetic Compatibility, vol. 2, pp 1197-1202. MC9S12XDP512 Datasheet, Freescale Semiconductor Inc., 2005. C. Marot and C. Lochot, “Methodology to characterize the EMC IC behavior regarding the EMC application requirements” in Proceedings of the 2005 International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMCCOMPO 2005, pp 145-149, Munich, Nov. 2005 De-embedding and Embedding S-parameter Networks Using a Vector Network Analyzer, Agilent Technologies, Application note 1364-1. T. A. Winslow, “Component modeling for PCB design” in Microwave, 2000, pp. 61-63. S. Sercu and L. Martens, “Characterizing N-port packages and interconnections with a 2-port network analyzer” in Proc. of the IEEE 6th Topical Meeting on Electrical Performance of Electronic Packaging, 1997, pp 163-166. C. Labussière, G. Bouisse, J. Tao, E. Sicard and C. Lochot, “Characterization and modeling of the supply network from an integrated circuit up to 12GHz” in Proceedings of the International Symposium on Electromagnetic Compatibility, EMC Europe, pp. 894899, Barcelona, Sep. 2006. S. Calvet, “Contribution to the diminution of the parasitic emission from CMOS sub-micronic microcontrollers”, PhD thesis report, 2003. S. Bendhia., J. Joly., C. Lochot., C. Labussière., 2005, "A 16 bit Microcontroller emission measurements and modeling using different approaches and a specific test board, " in Proceedings of the 2005 International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMCCOMPO 2005, Munich, Nov. 2005 International Electro-technical Commission, IEC 61967-4, “Integrated Circuits, Measurement of Electromagnetic Emissions, 150kHz to 1GHz – Part 4: Measurement of Conducted Emissions, 1ohm/150ohm Direct Coupling Method”, 2002. International Electro-technical Commission, IEC 61967-2, “Integrated Circuits, Measurement of Electromagnetic Emissions, 150kHz to 1GHz – Part 2: Measurement of Radiated Emissions, TEM Cell and Wideband TEM Cell Method”, 2005. R. De Leo, T. Rozzi, C. Svara, and L. Zappelli, “Rigorous analysis of the GTEM cell” in IEEE Transactions on Microwave Theory and Techniques, vol. 39, issue 3, March 1991, pp. 488-500. K. P. Slattery, J. W. Neal, and C. Wei, “Near-field measurements of VLSI devices” in IEEE Transactions on Electromagnetic Compatibility, vol. 41, issue 4, Nov. 1999, pp. 374-384. C. Labussière, C. Lochot and A. Boyer, “Characterization of the radiation from a 16-bit microcontroller by using miniature near-field probes” in Proceedings of the 5th International Workshop on ElectroMagnetic Compatibility of Integrated Circuits, EMCCOMPO 2005, pp 33-38, Munich, Nov. 2005 International Electro-technical Commission, IEC/TS 61967-3, “Integrated Circuits, Measurement of Electromagnetic Emissions, 150kHz to 1GHz – Part 3: Measurement of Radiated Emissions, Surface Scan Method”, 2005. S. Jin, M. A. Cracraft, K. P. Slattery, M. Yamaguchi, R. E. DuBroff, “Calibration and compensation of near-field scan measurements” in IEEE Transactions on Electromagnetic Compatibility, vol. 47, issue 3, Aug. 2005, pp. 642-650. A. Boyer, C. Labussière, O. Pigaglio, J. W. Tao, E. Sicard and C. Lochot, “Methodology of Calibration of miniature Near-Field Probes for Quantitative Characterization of IC radiation”, in Proceedings of the 2nd International Conference on Electromagnetic Near-Field Characterization, ICONIC 2005.

12 [31] HFSS product information. Available: //www.ansoft.com/products/hf/ hfss/ Cécile LABUSSIERE-DORGAN was born in Orléans, France, in 1978. In 2002, she received the master degree in Electronics Engineering from the Institut National Polytechnique (INP-ENSEEIHT) of Toulouse, France. From 2003 to 2006, she was pursuing the Ph.D. degree at Freescale Semiconductor, Toulouse, France. Her research interests concerned the study and the modeling of IC emission measurements methods, in particular the TEM/GTEM cell standard and the surface-scan method. In 2006, she joined the Délégation Générale de l’Armement (DGA) as an EMC expert at the Centre d’Essais Aéronautique de Toulouse (CEAT). She is in charge of the expertise and the qualification of military equipments and systems. Sonia BENDHIA was born in Toulouse, France, in 1972. She received the engineering diploma in 1995, and the Ph.D. in Electronic Design from the National Institute of Applied Sciences (INSA), Toulouse, France, in 1998. She is currently at the rank of assistant professor at INSA-Toulouse, Department of Electrical and Computer Engineering. Her research interests include signal integrity in deep sub-micron CMOS ICs and electromagnetic compatibility of ICs. She has authored technical papers on signal integrity and EMC. She has contributed to the publication of books for educational and research purpose. Etienne SICARD received the B.S degree in 1984 and the PhD in Electrical Engineering from the University of Toulouse, France, in 1987. He stayed 18 months at Osaka University, Japan, and one year as an invited professor at the University of Balearic Islands, Spain. Etienne SICARD is currently a professor at INSA of Toulouse, Department of Electrical and Computer Engineering. He was a visiting professor at the electronic department of Carleton University, Ottawa, Canada in 2004. His research interests include several aspects of CAD tools for the design and electromagnetic compatibility of integrated circuits. He is the author of books, software and more than 100 technical papers in these areas. Etienne is a member of the SEE and IEEE societies. Junwu TAO was born in Hubei, China, in 1962. He received the B.Sc. degree in electronics from the Radio Engineering Department, Huazhong (Central China) University of Science and Technology, Wuhan, China, in 1982, the PhD degree (with honors) from the Institut National Polytechnique of Toulouse (INP), France in 1988, and the Habilitation degree from the University of Savoie, France in 1999. From 1983 to 1991, he was with the electronics laboratory of ENSEEIHT, Toulouse, France, where he worked on the application of various numerical methods to two- and threedimensional problems in electromagnetism, and the design of microwave and millimeter-wave device. From 1991 to 2001 has was with the microwave laboratory (LAHC) at the university of Savoie, Chambéry, France, where he was an associate professor in electrical engineering and involved in the full wave characterization of discontinuity in various planar waveguides and the nonlinear transmission line design. Since September 2001 he is a full position professor at INP Toulouse where he is involved in the numerical methods for electromagnetism, microwave and RF components design, microwave and millimeter-wave measurements.

TEMC-241-2006.R1 Henrique Jorge QUARESMA was born in Santarém, Portugal, in 1978. He received the Aerospace Engineering Degree from the Instituto Superior Técnico (IST), in 2001. From 2001 to 2002, he was a researcher at the Instituto de Telecomunicações (IT) in Lisbon, integrated in the Power Electronics for Telecommunications research group. He was also teaching assistant at the electrical and computer engineering department at IST from 2002 to 2004. In 2002, he joined the Radio, Microwave and Millimetre Waves research group at IT, where he is currently working toward the PhD in Aerospace Engineering. He stayed 15 months at LESIA-INSA in Toulouse, France in the context of his PhD work on the substrate coupling in integrated circuits. His current research interests include electromagnetic compatibility in and of integrated circuits, substrate crosstalk in integrated circuits, signal integrity and electromagnetic compatibility in onboard aircraft micro-systems. Christophe LOCHOT was born in Versailles, France, in 1970. He received the master degree and the Ph.D. degree in Electrotechnical Engineering from the Institut National Polytechnique de Toulouse, France respectively in 1994 and in 1999. From 1998 to 2000, he used to work at Airbus Industry, France as an electrical research engineer on new electrical architectures in the aircraft. He began at this time his first steps in the EMC. In 2001, he joined Motorola (then Freescale) as a research manager on the EMC for Integrated Circuit topic. From 2002 to 2006, he was a member of the EMC for IC task force at the UTE, the French standard committee. Since 2003, he is part-time associated researcher at the LESIA, Toulouse, France. Since March 2006, he is working at Airbus Industry as a system designer for the electrical network of the new A350 aircraft.

13 Bertrand Vrignon was born in Tours, France, in 1979. He received an engineering diploma from ESEO, Angers, France in 2002, and a Ph.D in Electronic Design from the National Institute of Applied Sciences, Toulouse, France, in 2005. His doctoral research was in cooperation with STMicroelectronics, Crolles, France, where he characterized low electromagnetic emission guidelines for integrated circuits. In 2005, he joined Freescale Semiconductor, Toulouse, France, where he continued to work on EMC at IC level. His research interests include several aspects of design methodology to reduce emission, and noise susceptibility of deep-submicron ICs.