Models and Implementation of a Dynamic Element Matching DAC Niklas U. Andersson1,2, K. Ola Andersson1,2, Mark Vesterbacka2 and J Jacob Wikner3 1Linköping
Design Center, Ericsson Microelectronics AB, Box 1544, SE-581 15 Linköping, Sweden Department of Electrical Engineering, Linköping University, SE-581 83 Linköping, Sweden 3Swindon Design Centre, Ericsson Microelectronics, Westmead Dr., Swindon SN5 7UN, UK
2
{niklasa, olaa, markv}@isy.liu.se,
[email protected]
Abstract — The dynamic element matching (DEM) technique for digital-to-analog converters (DACs) has been suggested as a promising method to increase matching between the DAC’s references. However none of these comparisons have taken the dynamic effects that limit the performance for higher frequencies in the DAC into account. In this paper we compare the simulated results of a model describing the dynamic properties of a DEM DAC with measurements of an implemented 14-bit current-steering 0.35-um CMOS DEM DAC. It is shown that measured data agrees well with the results predicted by the used model. It is also shown that the DEM technique does not increase the performance of a DAC when dynamic errors are dominating the achievable performance.
1 INTRODUCTION Designing high-resolution, wideband digital-to-analog converters (DACs) is hard, since very linear components, i.e., good device matching, as well as high speed building blocks are required. Mismatch between the DAC’s reference levels introduces significant noise and distortion to the output, setting the achievable spurious-free dynamic range (SFDR) of the converter, at least at low frequencies. The device mismatch, arising from process irregularities [1] and parasitic components, can however be decreased using either static or dynamic methods. Static element matching (SEM) techniques, e.g., special layout techniques, laser trimming and distributed biasing, will not compensate for matching errors occurring after processing, e.g., aging and temperature variations. The dynamic methods on the other hand can be used during operation and are continuously compensating for matching errors by manipulating the input signal or the circuit elements using digital circuitry. This technique is commonly referred to as dynamic element matching (DEM) [2-6]. DEM modifies the distortion terms, hence signal-dependent errors, to become signal-independent noise. Therefore, using DEM we try to maximize the SFDR. In this work we show how dynamic errors, determined by e.g. signal-dependent impedance, limit the performance at higher frequencies which lets us come to the conclusion that only a limited amount of DEM has to be used in order to reach a certain performance. This allows us to reduce the design overhead and circuit complexity. In [6] we presented related work on DEM and in this work we show an extension of the results where the dynamic effects in the DAC have been added to the work. We also compare this model with measurement results of a 14-bit current-steering 0.35-um CMOS DEM DAC. In Sec. 2 we discuss some different DEM techniques and in Sec. 3 we describe a dynamic model of a current-steering DAC. To verify this model a test chip was implemented (Sec. 4.1) and a comparison between simulated and measured data is found in Sec. 4. The work is concluded in Sec. 5
2 DYNAMIC ELEMENT MATCHING IN DACS The DEM techniques [2-6] have shown significant results on improving linearity in DACs. A high-level topology of DEM for D/A conversion is shown in Fig. 1(a). The binary input word is thermometer coded and then the bits are scrambled before entering the 1-bit DACs. The outputs of the 1-bit DACs are summed forming the desired output. This structure has the advantage that by using 1-bit DACs a perfect linear performance can be achieved [2]. However this approach is not suitable for high resolution DACs due to the high hardware complexity, so trade offs usually have to be done. One straight-forward approach is to apply the DEM technique in Fig. 1(a) to a number of the most significant bits (MSBs) only and keep the least significant bits (LSBs) binary weighted. Another approach proposed in [4] is the partial randomization DEM, PRDEM, technique which is over viewed in next section. Although not treated in this paper it is worth to notice that DEM spoils the good glitch performance achieved by using thermometer code [7], even a DC input may result in glitches! 2.1 Partial randomization DEM A generalized partial randomization DEM, PRDEM, structure [4] is shown in Fig. 1(b). It utilizes a binary switching tree containing switching blocks, S k, r , where k denotes the layer and r the position of the switching block in the layer. The switching block (Fig. 1c) has one ( k + 1 ) -bit input and two k -bit outputs, as well as a random control bit c k [ n ] equal for all blocks S k, r in the k th layer. Every c k [ n ] is a random or pseudo random bit-sequence, PRBS, uncorrelated with the control bits used in all other layers. S k, r has the following operation: when c k [ n ] = 1 , the MSB, x k , of the input is copied k times and mapped to the top output, while the and the remaining k bits of the input are mapped directly to the k bits of the bottom output. For c k [ n ] = 0 the situation is reversed. Digital Encoder
Scrambler
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Figure 1: A general (a) DEM and (b) PRDEM structure and schematics of a (c) binary switching block and (d) (R-1)/1-bit DAC bank
y(n)
In PRDEM we introduce switching in a limited number of layers, i.e., in layers b through R (Fig. 1b), where 2 ≤ R ≤ b . Since no randomness is introduced in layers 1 through R – 1 we can simply substitute these layers by N = 2 b – R + 1 nominally identical DAC-banks each with an R -bit input (Fig. 1d). The LSB of the input controls a unit DAC element, whereas the remaining R – 1 bits control an ( R – 1 ) -bit conventional DAC. A tree with switching in all layers, i.e., layer 1 through b , and hereby is terminated by a set of 1-bit DACs is referred to as a full randomization DEM, FRDEM, system. This system will in theory achieve ideal SFDR performance [2], but again it suffers from a large hardware cost [3].
3 MODEL OF DYNAMIC PROPERTIES IN CURRENT-STEERING DACs We choose to implement the DAC as an unbuffered current-steering DAC since it shows to be very fast and hence well suited for wideband applications. The general structure of a differential binary weighted current-steering DAC is shown in Fig. 2(a). The switches are controlled by the input bits, x i , where i = 1, 2, ... , N , and N is the number of bits. x 0 is the least significant bit, LSB, and the corresponding current source has the nominal value I 0 . The source controlled by bit x i has a strength of 2 i – 1 ⋅ I LSB , hence the most significant bit, MSB, current + source therefore has the nominal value I MSB = 2 N – 1 ⋅ I 0 . The dual DAC outputs, I OUT and I OUT , are terminated with load resistors. In our dynamic DAC model [8] the current source is modeled as an ideal current source in parallel with a resistance and capacitance, the current switch is approximated by the switch-on resistance of the switch transistor, and the load impedance together with the wire is modeled as a lumped resistance and capacitance. A circuit schematic of the model is shown in Fig. 2(b).
N-1
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1
I0
2 I0
b2
bN
current source
0
2 I0
b1 switch
V+
V+ IOUT
IOUT
V+
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load
(a)
(b) Figure 2: Circuit schematic of (a) a binary weighted, current-steering DAC, and (b) its corresponding 1st-order DAC model
The nodal equations for this circuit can be expressed in state-space form and solved in, e.g, Matlab. This approach is similar to, e.g., a Spice simulator but with Matlab a much more flexible interface is allowed. Quantitative values of the circuit parameters are given in Table 1.
4 SIMULATION AND MEASUREMENT RESULTS It has been shown [4,5] that the PRDEM yields same SFDR performance as the FRDEM with only a few switching layers but at a significantly lower hardware cost. However none of these investigations take the dynamic effects in the DAC into account. Therefore it is of large interest to see how well an implemented PRDEM structure, described in Sec. 4.1, corresponds to the PRDEM DAC model described in Sec. 3. 4.1 PRDEM test chip A block view of the test chip is shown in Fig. 6(a). Each control bit c k [ n ] (equal for all blocks S k, r within the k th layer) can be programmed to be random or fixed. This setup enables the DAC to have zero to four switching layers. If all control bits are fixed we get a 14-bit binary weighted DAC without switching. If the first control bit is set to random we get a PRDEM DAC with one switching layer and so on. Additional chip data is found in Table 1. 4.2 Simulation setup and simulation results In the simulations a Gaussian distributed error current with a standard deviation of approximately 10% has been added to each unit current source. This is a rather large value but it includes all static errors in the DAC, e.g., mismatch between current sources, mismatch in biasing, gain errors between the DAC banks etc. The input is a full scale single-tone sinusoid with a sampling frequency of f samp = 10MHz and the single-ended output, terminated over 50 Ω , is examined. In Fig. 4(a) we show the output without randomization. We find that the SFDR (60.2dB) is limited by the third harmonic. When introducing switching in the first layer (Fig. 4b) the SFDR is increased to 67.7dB, a gain of 7.5dB corresponding to about one bit in performance, to the cost of a somewhat higher noise floor. The SFDR is now limited by the second harmonic. When introducing switching in all four layers (Fig. 4c) we can see some smaller differences compared to Fig. 4(b) but the SFDR remains the same hence we do not gain any SFDR performance by having more than one switching layer. This can be explained by observing the second harmonic in Fig. 4(a), (b) and (c). The second harmonic is almost unaffected by the randomization, i.e., it arises from dynamic errors in the DAC and as soon as the third harmonic, arising from mismatch, is suppressed below the second harmonic we do not gain in SFDR performance by using DEM [11]. Simulated Spectrum Without DEM
Simulated With 1 Layer DEM
0 −10
0
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SFDR = 59.6 dB
SFDR = 67.8 dB
SFDR = 68.1 dB
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(a) (b) (c) Figure 3: Simulated spectra, 10MHz sampling frequency, (a) without randomization, with (b) one switching layer and (c) four layer switching
5
4.3 Measurement results To verify the simulated results in Sec. 4.2 the implemented DAC is measured with the same sampling frequency, f samp = 10MHz . In Fig. 4(a) and Fig. 4(b) we compare the gain in performance between using no randomization and using one layer switching. We find that the SFDR is increased from 60.7dB to 67.7dB, a gain of 7.5dB which could be predicted from the simulation results. When switching all four layers (Fig. 4c) we do not gain much in SFDR performance compared to the results in Fig. 4(b). Measured Spectrum Without DEM
Measured With 1 Layer DEM
0 −10
0
−10
SFDR = 60.7 dB
−10
SFDR = 67.3 dB
SFDR = 68 dB
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Figure 4: Measured spectra, 10MHz sampling frequency, (a) without randomization, with (b) one switching layer and (c) four layer switching
4.4 SFDR for different sampling frequencies To see how well the model works for different sampling frequencies, f samp , the simulated results were compared with measurement results from the real PRDEM DAC. The sampling frequency is swept while the f sig ⁄ f samp ratio is held constant where f sig is the single tone frequency. In Fig. 5(a) we compare the simulated and measured SFDR without randomization. We find from Fig. 5(a) and Fig. 5(b) that the simulated and measured results behaves similarly. Simulated and measured SFDR without DEM
Simulated and measured SFDR with DEM
65 Measured Simulated
Measured Simulated
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71 62
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68
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(a) (b) Figure 5: Simulated and measured SFDR performance for different sampling frequencies with (a) no randomization, and (b) switching in all layers
5 CONCLUSIONS We have presented a DAC model describing the dynamic effects and used it to investigate especially the SFDR performance when using DEM on a DAC. We have found that once the distortion terms arising from mismatch, typically the 3rd harmonic, have been suppressed below the distortion terms arising from dynamic effects, typically the second harmonic, we do not gain in performance but the hardware complexity is rapidly increasing [3]. We have also shown that the dynamic PRDEM DAC model works well for different sampling frequencies. The authors would like to thank Prof. Lars Wanhammar at the dept. of Electrical Engineering, Linköping University, and Dr. Gunnar Björklund at Microelectronics Research Center, Ericsson Microelectronics, for all help and support.
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S14,1
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(a)
(b) Figure 6: (a) Block view and (b) chip photo of the PRDEM test DAC DAC model parameters
Value
Chip parameters
Value
unit current
1.22 µA
Process
0.35-um CMOS
output resistance (unit current source)
1 GΩ
No. input bits
14
output capacitance (unit current source)
10 fF
Area (core)
5 mm2
switch resistance
200 Ω
No. transistors
~78 000
load resistance
50 Ω
load capacitance
100 pF Table 1: DAC model and chip parameters
References [1] M.J.M. Pelgrom, et al., “Matching Properties of MOS Transistors,” IEEE J. of Solid-State Circuits, vol. 24, no. 5, pp. 1433-9, Oct. 1989. [2] P. Carbone and I. Galton, “Conversion error in D/A converters employing dynamic element matching,” Proc. of IEEE ISCAS‘94, vol. 2, pp. 13-16, 1994. [3] H.T. Jensen and I. Galton, “A low-complexity dynamic element matching DAC for direct digital synthesis,” IEEE Trans. of Circuits and Systems II, vol. 45.1, pp. 13-27, Jan. 1998. [4] H.T. Jensen and I. Galton, “An analysis of the partial randomization dynamic element matching technique,” IEEE Trans. of Circuits and Systems II, vol. 45.12, pp. 1538-49, Dec. 1998. [5] N.U. Andersson and J.J. Wikner, “Comparison of different dynamic element matching techniques for wideband CMOS DACs," Proc. of the NorChip Conf., Oslo, Norway, 1999. [6] N.U. Andersson and J.J. Wikner, “A strategy of implementing dynamic element matching in current-steering DACs," Proc. of IEEE SSMSD’00, San Diego, CA, U.S.A., 2000. [7] D.A. Johns and K. Martin, Analog integrated circuit design, John Wiley & Sons, New York, NY, USA, 1997. [8] K. O. Andersson and J. J. Wikner, “Characterization of a CMOS Current-Steering DAC using State-Space Models,” Proc. of MWSCAS’00, Lansing, Michigan, U.S.A., 2000. [9] R.J. van de Plassche, Integrated analog-to-digital and digital-to-analog converters, Kluwer academic publishers, Boston, U.S.A., 1994. [10] M Gustavsson, J.J. Wikner and N. Tan, CMOS Data Converters for Communications, Kluwer academic publishers, U.S.A., 2000. [11] J.J. Wikner, Studies on CMOS Digital-to-Analog Converters, Dissertation, Linköping University, Thesis No. 667, ISBN 91-7219-910-5, Linköping Sweden, March 2001.
