Module 1

Module 1 Power Semiconductor Devices Version 2 EE IIT, Kharagpur 1

Lesson 1 Power Electronics Version 2 EE IIT, Kharagpur 2

Introduction This lesson provides the reader the following: (i) (ii) (iii) (iv) (v)

Create an awareness of the general nature of Power electronic equipment; Brief idea about topics of study involved, The key features of the principal Power Electronic Devices; An idea about which device to choose for a particular application. A few issues like base drive and protection of PE devices and equipment common to most varieties.

Power Electronics is the art of converting electrical energy from one form to another in an efficient, clean, compact, and robust manner for convenient utilisation. A passenger lift in a modern building equipped with a Variable-Voltage-Variable-Speed induction-machine drive offers a comfortable ride and stops exactly at the floor level. Behind the scene it consumes less power with reduced stresses on the motor and corruption of the utility mains.

Fig. 1.1 The block diagram of a typical Power Electronic converter Power Electronics involves the study of • • • • • • • •

Power semiconductor devices - their physics, characteristics, drive requirements and their protection for optimum utilisation of their capacities, Power converter topologies involving them, Control strategies of the converters, Digital, analogue and microelectronics involved, Capacitive and magnetic energy storage elements, Rotating and static electrical devices, Quality of waveforms generated, Electro Magnetic and Radio Frequency Interference, Version 2 EE IIT, Kharagpur 3

• Thermal Management The typical converter in Fig. 1.1 illustrates the multidisciplinary nature of this subject.

How is Power electronics distinct from linear electronics? It is not primarily in their power handling capacities. While power management IC's in mobile sets working on Power Electronic principles are meant to handle only a few milliwatts, large linear audio amplifiers are rated at a few thousand watts. The utilisation of the Bipolar junction transistor, Fig. 1.2 in the two types of amplifiers best symbolises the difference. In Power Electronics all devices are operated in the switching mode either 'FULLY-ON' or 'FULLY-OFF' states. The linear amplifier concentrates on fidelity in signal amplification, requiring transistors to operate strictly in the linear (active) zone, Fig 1.3. Saturation and cutoff zones in the VCE - IC plane are avoided. In a Power electronic switching amplifier, only those areas in the VCE - IC plane which have been skirted above, are suitable. Onstate dissipation is minimum if the device is in saturation (or quasi-saturation for optimising other losses). In the off-state also, losses are minimum if the BJT is reverse biased. A BJT switch will try to traverse the active zone as fast as possible to minimise switching losses.

Fig. 1.2 Typical Bipolar transistor based (a) linear (common emitter) (voltage) amplifier stage and (b) switching (power) amplifier

Version 2 EE IIT, Kharagpur 4

Fig 1.3 Operating zones for operating a Bipolar Junction Transistor as a linear and a switching amplifier Linear operation Active zone selected: Good linearity between input/output

Switching operation Active zone avoided : High losses, encountered only during transients Saturation & cut-off zones avoided: poor Saturation & cut-off (negative bias) zones linearity selected: low losses Transistor biased to operate around No concept of quiescent point quiescent point Common emitter, Common collector, Transistor driven directly at base - emitter common base modes and load either on collector or emitter Output transistor barely protected Switching-Aid-Network (SAN) and other protection to main transistor Utilisation of transistor rating of secondary Utilisation of transistor rating optimised importance


An example illustrating the linear and switching solutions to a power supply specification will emphasise the difference. Spec: Input : 230 V, 50 Hz, Output:

12 V regulated DC, 20 W Ferrite core HF transfr: Light, efficient

Series regulator high losses 230 V

230 V

Line freq transformer: heavy, lossy

(b)

(a) High-freq Duty-ratio (ON/OFF) control - low losses

Fig. 1.4 (a) A Linear regulator and (b) a switching regulator solution of the specification above The linear solution, Fig. 1.4 (a), to this quite common specification would first step down the supply voltage to 12-0-12 V through a power frequency transformer. The output would be rectified using Power frequency diodes, electrolytic capacitor filter and then series regulated using a chip or a audio power transistor. The tantalum capacitor filter would follow. The balance of the voltage between the output of the rectifier and the output drops across the regulator device which also carries the full load current. The power loss is therefore considerable. Also, the stepdown iron-core transformer is both heavy, and lossy. However, only twice-line-frequency ripples appear at the output and material cost and technical know-how required is low. In the switching solution Fig. 1.4 (b) using a MOSFET driven flyback converter, first the line voltage is rectified and then isolated, stepped-down and regulated. A ferrite-core high-frequency (HF) transformer is used. Losses are negligible compared to the first solution and the converter is extremely light. However significant high frequency (related to the switching frequency) noise appear at the output which can only be minimised through the use of costly 'grass' capacitors.

Power Semiconductor device - history Power electronics and converters utilizing them made a head start when the first device the Silicon Controlled Rectifier was proposed by Bell Labs and commercially produced by General Electric in the earlier fifties. The Mercury Arc Rectifiers were well in use by that time and the robust and compact SCR first started replacing it in the rectifiers and cycloconverters. The necessity arose of extending the application of the SCR beyond the line-commutated mode of action, which called for external measures to circumvent its turn-off incapability via its control terminals. Various turn-off schemes were proposed and their classification was suggested but it became increasingly obvious that a device with turn-off capability was desirable, which would permit it a wider application. The turn-off networks and aids were impractical at higher powers. The Bipolar transistor, which had by the sixties been developed to handle a few tens of amperes and block a few hundred volts, arrived as the first competitor to the SCR. It is superior to the SCR in its turn-off capability, which could be exercised via its control terminals. This permitted the replacement of the SCR in all forced-commutated inverters and choppers. However, the gain (power) of the SCR is a few decades superior to that of the Bipolar transistor Version 2 EE IIT, Kharagpur 6

and the high base currents required to switch the Bipolar spawned the Darlington. Three or more stage Darlingtons are available as a single chip complete with accessories for its convenient drive. Higher operating frequencies were obtainable with a discrete Bipolars compared to the 'fast' inverter-grade SCRs permitting reduction of filter components. But the Darlington's operating frequency had to be reduced to permit a sequential turn-off of the drivers and the main transistor. Further, the incapability of the Bipolar to block reverse voltages restricted its use. The Power MOSFET burst into the scene commercially near the end seventies. This device also represents the first successful marriage between modern integrated circuit and discrete power semiconductor manufacturing technologies. Its voltage drive capability – giving it again a higher gain, the ease of its paralleling and most importantly the much higher operating frequencies reaching upto a few MHz saw it replacing the Bipolar also at the sub-10 KW range mainly for SMPS type of applications. Extension of VLSI manufacturing facilities for the MOSFET reduced its price vis-à-vis the Bipolar also. However, being a majority carrier device its on-state voltage is dictated by the RDS(ON) of the device, which in turn is proportional to about VDSS2.3 rating of the MOSFET. Consequently, high-voltage MOSFETS are not commercially viable. Improvements were being tried out on the SCR regarding its turn-off capability mostly by reducing the turn-on gain. Different versions of the Gate-turn-off device, the Gate turn-off Thyristor (GTO), were proposed by various manufacturers - each advocating their own symbol for the device. The requirement for an extremely high turn-off control current via the gate and the comparatively higher cost of the device restricted its application only to inverters rated above a few hundred KVA. The lookout for a more efficient, cheap, fast and robust turn-off-able device proceeded in different directions with MOS drives for both the basic thysistor and the Bipolar. The Insulated Gate Bipolar Transistor (IGBT) – basically a MOSFET driven Bipolar from its terminal characteristics has been a successful proposition with devices being made available at about 4 KV and 4 KA. Its switching frequency of about 25 KHz and ease of connection and drive saw it totally removing the Bipolar from practically all applications. Industrially, only the MOSFET has been able to continue in the sub – 10 KVA range primarily because of its high switching frequency. The IGBT has also pushed up the GTO to applications above 2-5 MVA. Subsequent developments in converter topologies – especially the three-level inverter permitted use of the IGBT in converters of 5 MVA range. However at ratings above that the GTO (6KV/6KA device of Mitsubishi) based converters had some space. Only SCR based converters are possible at the highest range where line-commutated or load-commutated converters were the only solution. The surge current, the peak repetition voltage and I2t ratings are applicable only to the thyristors making them more robust, specially thermally, than the transistors of all varieties.

1200V Version 3 ASIPM

Presently there are few hybrid devices and Intelligent Power Modules (IPM) are marketed by some manufacturers. The IPMs have already gathered wide acceptance. The 4500 V, 1200 A Version 2 EE IIT, Kharagpur 7

IEGT (injection-enhanced gate transistor) of Toshiba or the 6000 V, 3500 A IGCT (Integrated Gate Commutated Thyristors) of ABB which are promising at the higher power ranges. However these new devices must prove themselves before they are accepted by the industry at large. Silicon carbide is a wide band gap semiconductor with an energy band gap wider than about 2 eV that possesses extremely high thermal, chemical, and mechanical stability. Silicon carbide is the only wide band gap semiconductor among gallium nitride (GaN, EG = 3.4 eV), aluminum nitride (AlN, EG = 6.2 eV), and silicon carbide that possesses a high-quality native oxide suitable for use as an MOS insulator in electronic devices The breakdown field in SiC is about 8 times higher than in silicon. This is important for high-voltage power switching transistors. For example, a device of a given size in SiC will have a blocking voltage 8 times higher than the same device in silicon. More importantly, the on-resistance of the SiC device will be about two decades lower than the silicon device. Consequently, the efficiency of the power converter is higher. In addition, SiC-based semiconductor switches can operate at high temperatures (~600 C) without much change in their electrical properties. Thus the converter has a higher reliability. Reduced losses and allowable higher operating temperatures result in smaller heatsink size. Moreover, the high frequency operating capability of SiC converters lowers the filtering requirement and the filter size. As a result, they are compact, light, reliable, and efficient and have a high power density. These qualities satisfy the requirements of power converters for most applications and they are expected to be the devices of the future. Ratings have been progressively increasing for all devices while the newer devices offer substantially better performance. With the SCR and the pin-diodes, so called because of the sandwiched intrinsic ‘i’-layer between the ‘p’ and ‘n’ layers, having mostly line-commutated converter applications, emphasis was mostly on their static characteristics - forward and reverse voltage blocking, current carrying and over-current ratings, on-state forward voltage etc and also on issues like paralleling and series operation of the devices. As the operating speeds of the devices increased, the dynamic (switching) characteristics of the devices assumed greater importance as most of the dissipation was during these transients. Attention turned to the development of efficient drive networks and protection techniques which were found to enhance the performance of the devices and their peak power handling capacities. Issues related to paralleling were resolved by the system designer within the device itself like in MOSFETS, while the converter topology was required to take care of their series operation as in multi-level converters. The range of power devices thus developed over the last few decades can be represented as a tree, Fig. 1.5, on the basis of their controllability and other dominant features.


POWER SEMICONDUCTOR DEVICES

UNCONTROLLED

RECTIFIERS

POWER SILICON DIODES FREDS SCHOTTKY

CONTROLLED

ACCESSORIES

REGENERATIVE SCR TRIAC GTO

DIAC Zenner MOV

NON-REGENERATIVE BJT MOSFET IGBT

INTEGRATED IGCT PIC INTELLIGENT POWER MODULES

Fig. 1.5 Power semiconductor device variety

Power Diodes diF /dt

t0

t1

SNAPPY

t2

SOFT Δ to

Q1

Q2

IRM

VRM

Fig. 1.6 Typical turn-off dynamics of a soft and a 'snappy' diode' Silicon Power diodes are the successors of Selenium rectifiers having significantly improved forward characteristics and voltage ratings. They are classified mainly by their turn-off (dynamic) characteristics Fig. 1.6. The minority carriers in the diodes require finite time - trr (reverse recovery time) to recombine with opposite charges and neutralise. Large values of Qrr (= Q1 + Q2) - the charge to be dissipated as a negative current when the and diode turns off and trr (= t2 - t0) - the time it takes to regain its blocking features, impose strong current stresses on the controlled device in series. Also a 'snappy' type of recovery of the diode effects high di/dt voltages on all associated power device in the converter because of load or stray inductances present in the network. There are broadly three types of diodes used in Power electronic applications: Line-frequency diodes: These PIN diodes with general-purpose rectifier type applications, are available at the highest voltage (~5kV) and current ratings (~5kA) and have excellent overcurrent (surge rating about six times average current rating) and surge-voltage withstand capability. They have relatively large Qrr and trr specifications.


Fast recovery diodes: Fast recovery diffused diodes and fast recovery epitaxial diodes, FRED's, have significantly lower Qrr and trr (~ 1.0 sec). They are available at high powers and are mainly used in association with fast controlled-devices as free-wheeling or DC-DC choppers and rectifier applications. Fast recovery diodes also find application in induction heating, UPS and traction. Schottky rectifiers: These are the fastest rectifiers being majority carrier devices without any Qrr.. However, they are available with voltage ratings up to a hundred volts only though current ratings may be high. Their conduction voltages specifications are excellent (~0.2V). The freedom from minority carrier recovery permits reduced snubber requirements. Schottky diodes face no competition in low voltage SPMS applications and in instrumentation.

Silicon Controlled Rectifier (SCR) The Silicon Controlled Rectifier is the most popular of the thyristor family of four layer regenerative devices. It is normally turned on by the application of a gate pulse when a forward bias voltage is present at the main terminals. However, being regenerative or 'latching', it cannot be turned off via the gate terminals specially at the extremely high amplification factor of the gate. There are two main types of SCR's. Converter grade or Phase Control thyristors These devices are the work horses of the Power Electronics. They are turned off by natural (line) commutation and are reverse biased at least for a few milliseconds subsequent to a conduction period. No fast switching feature is desired of these devices. They are available at voltage ratings in excess of 5 KV starting from about 50 V and current ratings of about 5 KA. The largest converters for HVDC transmission are built with series-parallel combination of these devices. Conduction voltages are device voltage rating dependent and range between 1.5 V (600V) to about 3.0 V (+5 KV). These devices are unsuitable for any 'forced-commutated' circuit requiring unwieldy large commutation components. The dynamic di/dt and dv/dt capabilities of the SCR have vastly improved over the years borrowing emitter shorting and other techniques adopted for the faster variety. The requirement for hard gate drives and di/dt limting inductors have been eliminated in the process. Inverter grade thyristors: Turn-off times of these thyristors range from about 5 to 50 μsecs when hard switched. They are thus called fast or 'inverter grade' SCR's. The SCR's are mainly used in circuits that are operated on DC supplies and no alternating voltage is available to turn them off. Commutation networks have to be added to the basic converter only to turn-off the SCR's. The efficiency, size and weight of these networks are directly related to the turn-off time, tq of the SCR. The commutation circuits utilised resonant networks or charged capacitors. Quite a few commutation networks were designed and some like the McMurray-Bedford became widely accepted. Asymmetrical, light-activated, reverse conducting SCR's Quite a few varieties of the basic SCR have been proposed for specific applications. The Asymmetrical thyristor is convenient when reactive powers are involved and the light activated SCR assists in paralleling or series operation.


MOSFET The Power MOSFET technology has mostly reached maturity and is the most popular device for SMPS, lighting ballast type of application where high switching frequencies are desired but operating voltages are low. Being a voltage fed, majority carrier device (resistive behaviour) with a typically rectangular Safe Operating Area, it can be conveniently utilized. Utilising shared manufacturing processes, comparative costs of MOSFETs are attractive. For low frequency applications, where the currents drawn by the equivalent capacitances across its terminals are small, it can also be driven directly by integrated circuits. These capacitances are the main hindrance to operating the MOSFETS at speeds of several MHz. The resistive characteristics of its main terminals permit easy paralleling externally also. At high current low voltage applications the MOSFET offers best conduction voltage specifications as the RDS(ON) specification is current rating dependent. However, the inferior features of the inherent antiparallel diode and its higher conduction losses at power frequencies and voltage levels restrict its wider application.

The IGBT It is a voltage controlled four-layer device with the advantages of the MOSFET driver and the Bipolar Main terminal. IGBTs can be classified as punch-through (PT) and non-punchthrough (NPT) structures. In the punch-through IGBT, a better trade-off between the forward voltage drop and turn-off time can be achieved. Punch-through IGBTs are available up to about 1200 V. NPT IGBTs of up to about 4 KV have been reported in literature and they are more robust than PT IGBTs particularly under short circuit conditions. However they have a higher forward voltage drop than the PT IGBTs. Its switching times can be controlled by suitably shaping the drive signal. This gives the IGBT a number of advantages: it does not require protective circuits, it can be connected in parallel without difficulty, and series connection is possible without dv/dt snubbers. The IGBT is presently one of the most popular device in view of its wide ratings, switching speed of about 100 KHz a easy voltage drive and a square Safe Operating Area devoid of a Second Breakdown region.

The GTO The GTO is a power switching device that can be turned on by a short pulse of gate current and turned off by a reverse gate pulse. This reverse gate current amplitude is dependent on the anode current to be turned off. Hence there is no need for an external commutation circuit to turn it off. Because turn-off is provided by bypassing carriers directly to the gate circuit, its turn-off time is short, thus giving it more capability for highfrequency operation than thyristors. The GTO symbol and turn-off characteristics are shown in Fig. 30.3. GTOs have the I2t withstand capability and hence can be protected by semiconductor fuses. For reliable operation of GTOs, the critical aspects are proper design of the gate turn-off circuit and the snubber circuit.

Power Converter Topologies A Power Electronic Converter processes the available form to another having a different frequency and/or voltage magnitude. There can be four basic types of converters depending upon the function performed: Version 2 EE IIT, Kharagpur 11

CONVERSION FROM/TO

NAME

FUNCTION

DC to DC

Chopper

Constant to variable DC or variable to constant DC

DC to AC

Inverter

DC to AC of desired voltage and frequency

AC to DC

AC to AC

SYMBOL

~

Rectifier

AC to unipolar (DC) current

~

Cycloconverter, AC-PAC, Matrix converter

AC of desired frequency and/or magnitude from generally line AC

~

~

Base / gate drive circuit All discrete controlled devices, regenerative or otherwise have three terminals. Two of these are the Main Terminals. One of the Main Terminals and the third form the Control Terminal. The amplification factor of all the devices (barring the now practically obsolete BJT) are quite high, though turn-on gain is not equal to turn-off gain. The drive circuit is required to satisfy the control terminal characteristics to efficiently tun-on each of the devices of the converter, turn them off, if possible, again optimally and also to protect the device against faults, mostly overcurrents. Being driven by a common controller, the drives must also be isolated from each other as the potentials of the Main Terminal which doubles as a Control terminal are different at various locations of the converter. Gate-turn-off-able devices require precise gate drive waveform for optimal switching. This necessitates a wave-shaping amplifier. This amplifier is located after the isolation stage. Thus separate isolated power supplies are also required for each Power device in the converter (the ones having a common Control Terminal - say the Emitter in an IGBT - may require a few less). There are functionally two types of isolators: the pulse transformer which can transmit after isolation, in a multi-device converter, both the un-shaped signal and power and optical isolators which transmit only the signal. The former is sufficient for a SCR without isolated power supplies at the secondary. The latter is a must for practically all other devices. Fig. 1.7 illustrates to typical drive circuits for an IGBT and an SCR. Version 2 EE IIT, Kharagpur 12

IGBT

Vref COMPARATOR

TIMER

Fig. 1.7 Simple gate-drive and protection circuit for a stand-alone IGBT and a SCR

Protection of Power devices and converters Power electronic converters often operate from the utility mains and are exposed to the disturbances associated with it. Even otherwise, the transients associated with switching circuits and faults that occur at the load point stress converters and devices. Consequently, several protection schemes must be incorporated in a converter. It is necessary to protect both the Main Terminals and the control terminals. Some of these techniques are common for all devices and converters. However, differences in essential features of devices call for special protection schemes particular for those devices. The IGBT must be protected against latching, and similarly the GTO's turn-off drive is to be disabled if the Anode current exceeds the maximum permissible turn-off-able current specification. Power semiconductor devices are commonly protected against: 1. 2. 3. 4. 5. 6. 7. 8.

Over-current; di/dt; Voltage spike or over-voltage; dv/dt ; Gate-under voltage; Over voltage at gate; Excessive temperature rise; Electro-static discharge;

Semiconductor devices of all types exhibit similar responses to most of the stresses, however there are marked differences. The SCR is the most robust device on practically all counts. That it has an I2t rating is proof that its internal thermal capacities are excellent. A HRC fuse, suitably selected, and in co-ordination with fast circuit breakers would mostly protect it. This sometimes becomes a curse when the cost of the fuse becomes exorbitant. All transistors, specially the BJT and the IGBT is actively protected (without any operating cost!) by sensing the Main Terminal voltage, as shown in Fig. 1.7. This voltage is related to the current carried by the device. Further, the transistors permit designed gate current waveforms to minimise voltage spikes as a consequence of sharply rising Main terminal currents. Gate resistances have significant effect on turn-on and turn-off times of these devices - permitting optimisation of switching times for the reduction of switching losses and voltage spikes.


Protection schemes for over-voltages - the prolonged ones and those of short duration - are guided by the energy content of the surges. Metal Oxide Varistors (MOV's), capacitive dynamic voltage-clamps and crow-bar circuits are some of the strategies commonly used. For high dv/dt stresses, which again have similar effect on all devices, R-C or R-C-D clamps are used depending on the speed of the device. These 'snubbers' or 'switching-aid-networks', additionally minimise switching losses of the device - thus reducing its temperature rise. Gates of all devices are required to be protected against over-voltages (typically + 20 V) specially for the voltage driven ones. This is achieved with the help of Zener clamps - the zener being also a very fast-acting device. Protection against issues like excessive case temperatures and ESD follow well-set practices. Forced-cooling techniques are very important for the higher rated converters and whole environments are air-cooled to lower the ambient.

Objective type questions Qs#1 Which is the Power semiconductor device having a) b) c) d)

Highest switching speed; Highest voltage / current ratings; Easy drive features; Can be most effectively paralleled; e) Can be protected against over-currents with a fuse; f) Gate-turn off capability with regenerative features; g) Easy drive and High power handling capability Ans:

a) MOSFET; b) SCR; c) MOSFET; d) MOSFET; e) SCR ; (f) GTO; (g) IGBT

Qs#2 An SCR requires 50 mA gate current to switch it on. It has a resistive load and is supplied from a 100 V DC supply. Specify the Pulse transformer details and the circuit following it, if the driver circuit supply voltage is 10 V and the gate-cathode drop is about 1 V. Ans: The most important ratings of the Pulse transformer are its volt-secs rating, the isolation voltage and the turns ratio. The volt-secs is decided by the product of the primary pulse-voltage multiplied by the period for which the pulse is applied to the winding If the primary pulse voltage = (Supply voltage – drive transistor drop) The turn-on time of he SCR may be in the range 50 μsecs for an SCR of this rating. Consequently the volt secs may be in the range of 9 x 50 = 450 μvolt-secs = 2.5 KV, IM = 150 mA The Pulse transformer may be chosen as: 1:1, 450 μVs, Visol The circuit shown in Fig. 1.7 may be used. Diodes 1N4002 Series resistance = (Supply voltage – drive transistor drop – gate-cathode drop)/100mA = (10 –1 –1) / 100 E-3 = 80 Ohm = 49 or 57 Ohm (nearest available lower value) Version 2 EE IIT, Kharagpur 14

Module 2 AC to DC Converters Version 2 EE IIT, Kharagpur 1

Lesson 10 Single Phase Fully Controlled Rectifier Version 2 EE IIT, Kharagpur 2

Operation and Analysis of single phase fully controlled converter.

Instructional Objectives On completion the student will be able to •

Differentiate between the constructional and operation features of uncontrolled and controlled converters

•

Draw the waveforms and calculate their average and RMS values of different variables associated with a single phase fully controlled half wave converter.

•

Explain the operating principle of a single phase fully controlled bridge converter.

•

Identify the mode of operation of the converter (continuous or discontinuous) for a given load parameters and firing angle.

•

Analyze the converter operation in both continuous and discontinuous conduction mode and there by find out the average and RMS values of input/output, voltage/currents.

•

Explain the operation of the converter in the inverter mode.


10.1 Introduction Single phase uncontrolled rectifiers are extensively used in a number of power electronic based converters. In most cases they are used to provide an intermediate unregulated dc voltage source which is further processed to obtain a regulated dc or ac output. They have, in general, been proved to be efficient and robust power stages. However, they suffer from a few disadvantages. The main among them is their inability to control the output dc voltage / current magnitude when the input ac voltage and load parameters remain fixed. They are also unidirectional in the sense that they allow electrical power to flow from the ac side to the dc side only. These two disadvantages are the direct consequences of using power diodes in these converters which can block voltage only in one direction. As will be shown in this module, these two disadvantages are overcome if the diodes are replaced by thyristors, the resulting converters are called fully controlled converters. Thyristors are semicontrolled devices which can be turned ON by applying a current pulse at its gate terminal at a desired instance. However, they cannot be turned off from the gate terminals. Therefore, the fully controlled converter continues to exhibit load dependent output voltage / current waveforms as in the case of their uncontrolled counterpart. However, since the thyristor can block forward voltage, the output voltage / current magnitude can be controlled by controlling the turn on instants of the thyristors. Working principle of thyristors based single phase fully controlled converters will be explained first in the case of a single thyristor halfwave rectifier circuit supplying an R or R-L load. However, such converters are rarely used in practice. Full bridge is the most popular configuration used with single phase fully controlled rectifiers. Analysis and performance of this rectifier supplying an R-L-E load (which may represent a dc motor) will be studied in detail in this lesson.


10.2 Single phase fully controlled halfwave rectifier 10.2.1 Resistive load

Fig.10. 1(a) shows the circuit diagram of a single phase fully controlled halfwave rectifier supplying a purely resistive load. At ωt = 0 when the input supply voltage becomes positive the thyristor T becomes forward biased. However, unlike a diode, it does not turn ON till a gate pulse is applied at ωt = α. During the period 0 < ωt ≤ α, the thyristor blocks the supply voltage and the load voltage remains zero as shown in fig 10.1(b). Consequently, no load current flows during this interval. As soon as a gate pulse is applied to the thyristor at ωt = α it turns ON. The voltage across the thyristor collapses to almost zero and the full supply voltage appears across the load. From this point onwards the load voltage follows the supply voltage. The load being purely resistive the load current io is proportional to the load voltage. At ωt = π as the supply voltage passes through the negative going zero crossing the load voltage and hence the load current becomes zero and tries to reverse direction. In the process the thyristor undergoes reverse recovery and starts blocking the negative supply voltage. Therefore, the load voltage and the load current remains clamped at zero till the thyristor is fired again at ωt = 2π + α. The same process repeats there after. From the discussion above and Fig 10.1 (b) one can write For α < ωt ≤ π v 0 = vi = 2 Vi sinωt (10.1)

i0 =

v0 V = 2 i sinωt R R

(10.2) Version 2 EE IIT, Kharagpur 5

v0 = i0 = 0 otherwise. Therefore

1 2π 1 π v dωt = 2 Vi sinωt dωt 0 2π ∫0 2π ∫α V Or VOAV = i (1+ cosα) 2π 1 2π 2 VORMS = v0 dωt 2π ∫0 VOAV =

=

(10.4)

(10.5)

1 π 2 2 2vi sin ωtdωt 2π ∫α

Vi2 = 2π =

(10.3)

Vi2 2π

∫

π

α

(1- cos2ωt)dωt

sin2α ⎤ ⎡ ⎢⎣ π - α + 2 ⎥⎦ 1

V α sin2α ⎞ 2 = i ⎛⎜ 1- + ⎟ 2π ⎠ 2⎝ π 1

∴

FFVO =

VORMS VOAV

α sin2α ⎞ 2 π ⎛⎜ 1- + ⎟ 2π ⎠ = ⎝ π (1+ cosα)

(10.6)

Similar calculation can be done for i0. In particulars for pure resistive loads FFio = FFvo.

10.2.2 Resistive-Inductive load Fig 10.2 (a) and (b) shows the circuit diagram and the waveforms of a single phase fully controlled halfwave rectifier supplying a resistive inductive load. Although this circuit is hardly used in practice its analysis does provide useful insight into the operation of fully controlled rectifiers which will help to appreciate the operation of single phase bridge converters to be discussed later.


As in the case of a resistive load, the thyristor T becomes forward biased when the supply voltage becomes positive at ωt = 0. However, it does not start conduction until a gate pulse is applied at ωt = α. As the thyristor turns ON at ωt = α the input voltage appears across the load and the load current starts building up. However, unlike a resistive load, the load current does not become zero at ωt = π, instead it continues to flow through the thyristor and the negative supply voltage appears across the load forcing the load current to decrease. Finally, at ωt = β (β > π) the load current becomes zero and the thyristor undergoes reverse recovery. From this point onwards the thyristor starts blocking the supply voltage and the load voltage remains zero until the thyristor is turned ON again in the next cycle. It is to be noted that the value of β depends on the load parameters. Therefore, unlike the resistive load the average and RMS output voltage depends on the load parameters. Since the thyristors does not conduct over the entire input supply cycle this mode of operation is called the “discontinuous conduction mode”. From above discussion one can write. α ≤ ωt ≤ β For

v 0 = vi = 2 Vi sinωt v0 = 0 otherwise Therefore

1 2π v0 dωt 2π ∫0 1 β 2 Vi sinωt dωt = 2π ∫α

VOAV =

(10.7)

(10.8)


=

Vi

VORMS = =

2π

(cosα - cosβ)

1 2π 2 v0 dωt 2π ∫0

(10.9)

1 β 2 2 2vi sin ωt dωt 2π ∫α 1

V β - α sin2α - sin2β ⎞ 2 = i ⎛⎜ + ⎟ 2π ⎠ 2⎝ π V Vi I OAV = OAV = (cosα - cosβ) R 2πR Since the average voltage drop across the inductor is zero.

(10.10)

However, IORMS can not be obtained from VORMS directly. For that a closed from expression for i0 will be required. The value of β in terms of the circuit parameters can also be found from the expression of i0. α ≤ ωt ≤ β di Rio + L o = v0 = 2Vi sinωt dt The general solution of which is given by (ωt-α) 2Vi i 0 = I0 e tanϕ + sin(ωt - ϕ) Z ωL Where tanφ = and Z = R 2 + ω2 L2 R

For

i0

ωt =α

(10.11)

(10.12)

=0 ∴ 0 = I0 +

2Vi sin(α - φ) Z

( ωt-α ) 2Vi ⎡ ⎤ tanφ sin(φ α)e + sin(ωt φ) ⎢ ⎥⎦ ⎣ Z i0 = 0 otherwise.

∴ i0 =

(10.13)

Equation (10.13) can be used to find out IORMS. To find out β it is noted that i0 ωt=β = 0 ∴ sin(φ - α)e

α-β tanφ

= sin(φ - β)

(10.14)

Equation (10.14) can be solved to find out β Exercise 10.1

Fill in the blank(s) with appropriate word(s) Version 2 EE IIT, Kharagpur 8

i) ii) iii) iv) v)

In a single phase fully controlled converter the _________ of an uncontrolled converters are replaced by ____________. In a fully controlled converter the load voltage is controlled by controlling the _________ of the converter. A single phase half wave controlled converter always operates in the ________ conduction mode. The voltage form factor of a single phase fully controlled half wave converter with a resistive inductive load is _________ compared to the same converter with a resistive load. The load current form factor of a single phase fully controlled half wave converter with a resistive inductive load is _________ compared to the same converter with a resistive load.

Answers: (i) diodes, thyristors; (ii) firing angle; (iii) discontinuous (iv) poorer; (v) better.

2) Explain qualitatively, what will happen if a free-wheeling diode(cathode of the diode shorted with the cathode of the thyristor) is connected across the load in Fig 10.2.(a) Answer: Referring to Fig 10.2(b), the free wheeling diode will remain off till ωt = π since the positive load voltage across the load will reverse bias the diode. However, beyond this point as the load voltage tends to become negative the free wheeling diode comes into conduction. The load voltage is clamped to zero there after. As a result

i) ii) iii)

Average load voltage increases RMS load voltage reduces and hence the load voltage form factor reduces. Conduction angle of load current increases as does its average value. The load current ripple factor reduces.


10.3 Single phase fully controlled bridge converter

Fig 10.3 (a) shows the circuit diagram of a single phase fully controlled bridge converter. It is one of the most popular converter circuits and is widely used in the speed control of separately excited dc machines. Indeed, the R–L–E load shown in this figure may represent the electrical equivalent circuit of a separately excited dc motor. The single phase fully controlled bridge converter is obtained by replacing all the diode of the corresponding uncontrolled converter by thyristors. Thyristors T1 and T2 are fired together while T3 and T4 are fired 180º after T1 and T2. From the circuit diagram of Fig 10.3(a) it is clear that for any load current to flow at least one thyristor from the top group (T1, T3) and one thyristor from the bottom group (T2, T4) must conduct. It can also be argued that neither T1T3 nor T2T4 can conduct simultaneously. For example whenever T3 and T4 are in the forward blocking state and a gate pulse is applied to them, they turn ON and at the same time a negative voltage is applied across T1 and T2 commutating them immediately. Similar argument holds for T1 and T2. For the same reason T1T4 or T2T3 can not conduct simultaneously. Therefore, the only possible conduction modes when the current i0 can flow are T1T2 and T3T4. Of coarse it is possible that at a given moment none of the thyristors conduct. This situation will typically occur when the load current becomes zero in between the firings of T1T2 and T3T4. Once the load current becomes zero all thyristors remain off. In this mode the load current remains zero. Consequently the converter is said to be operating in the discontinuous conduction mode. Fig 10.3(b) shows the voltage across different devices and the dc output voltage during each of these conduction modes. It is to be noted that whenever T1 and T2 conducts, the voltage across T3 and T4 becomes –vi. Therefore T3 and T4 can be fired only when vi is negative i.e, over the negative half cycle of the input supply voltage. Similarly T1 and T2 can be fired only over the positive half cycle of the input supply. The voltage across the devices when none of the thyristors conduct depends on the off state impedance of each device. The values listed in Fig 10.3 (b) assume identical devices. Under normal operating condition of the converter the load current may or may not remain zero over some interval of the input voltage cycle. If i0 is always greater than zero then the converter is said to be operating in the continuous conduction mode. In this mode of operation of the converter T1T2 and T3T4 conducts for alternate half cycle of the input supply. Version 2 EE IIT, Kharagpur 10

However, in the discontinuous conduction mode none of the thyristors conduct over some portion of the input cycle. The load current remains zero during that period.

10.3.1 Operation in the continuous conduction mode As has been explained earlier in the continuous conduction mode of operation i0 never becomes zero, therefore, either T1T2 or T3T4 conducts. Fig 10.4 shows the waveforms of different variables in the steady state. The firing angle of the converter is α. The angle θ is given by sinθ =

E 2V1

(10.15)

It is assumed that at t = 0- T3T4 was conducting. As T1T2 are fired at ωt = α they turn on commutating T3T4 immediately. T3T4 are again fired at ωt = π + α. Till this point T1T2 conducts. The period of conduction of different thyristors are pictorially depicted in the second waveform (also called the conduction diagram) of Fig 10.4.



The dc link voltage waveform shown next follows from this conduction diagram and the conduction table shown in Fig 10.3(b). It is observed that the emf source E is greater than the dc link voltage till ωt = α. Therefore, the load current i0 continues to fall till this point. However, as T1T2 are fired at this point v0 becomes greater than E and i0 starts increasing through R-L and E. At ωt = π – θ v0 again equals E. Depending upon the load circuit parameters io reaches its maximum at around this point and starts falling afterwards. Continuous conduction mode will be possible only if i0 remains greater than zero till T3T4 are fired at ωt = π + α where upon the same process repeats. The resulting i0 waveform is shown below v0. The input ac current waveform ii is obtained from i0 by noting that whenever T1T2 conducts ii = i0 and ii = - i0 whenever T3T4 conducts. The last waveform shows the typical voltage waveform across the thyristor T1. It is to be noted that when the thyristor turns off at ωt = π + α a negative voltage is applied across it for a duration of π – α. The thyristor must turn off during this interval for successful operation of the converter. It is noted that the dc voltage waveform is periodic over half the input cycle. Therefore, it can be expressed in a Fourier series as follows. α

v 0 = VOAV + ∑ [ v an cos2nωt + v bn sin2nωt ]

(10.16)

n =1

Where

1 π+α 2 2 v 0 dωt = Vi cosα ∫ α π π 2 π 2 2 ⎡ cos(2n +1)α cos(2n -1)α ⎤ v an = ∫ v 0 cos2nωt dωt = Vi ⎢ π 0 π ⎣ 2n +1 2n -1 ⎥⎦ VOAV =

v bn =

2 π 2 2 ⎡ sin(2n +1)α sin(2n -1)α ⎤ v 0 sin2nωt dωt = Vi ⎢ ∫ 0 π π ⎣ 2n +1 2n -1 ⎥⎦

Therefore the RMS value of the nth harmonic 1 2 VOnRMS = v an + v 2bn 2

(10.17) (10.18) (10.19)

(10.20)

RMS value of v0 can of course be completed directly from. 1 π+α 2 VORMS = v0 dωt = Vi π ∫α

(10.21)

Fourier series expression of v0 is important because it provides a simple method of estimating individual and total RMS harmonic current injected into the load as follows: The impedance offered by the load at nth harmonic frequency is given by Z n = R 2 + (2nωL) 2

(10.22) 1 2

VonRMS ⎡ α 2 ⎤ (10.23) ; IOHRMS = ⎢ ∑ IonRMS ⎥ Zn ⎣ n =1 ⎦ From (10.18) – (10.23) it can be argued that in an inductive circuit IonRMS → 0 as fast as 1/n2. So in practice it will be sufficient to consider only first few harmonics to obtain a reasonably accurate estimate of IOHRMS form equation 10.23. This method will be useful, for example, while calculating the required current derating of a dc motor to be used with such a converter. IonRMS =


However to obtain the current rating of the device to be used it is necessary to find out a closed form expression of i0. This will also help to establish the condition under which the converter will operate in the continuous conduction mode. To begin with we observe that the voltage waveform and hence the current waveform is periodic over an interval π. Therefore, finding out an expression for i0 over any interval of length π will be sufficient. We choose the interval α ≤ ωt ≤ π + α. In this interval

di0 + Ri 0 + E = 2Vi sinωt dt The general solution of which is given by L

( ) - ωt-α tanφ

(10.24)

sinθ ⎤ ⎡ (10.25) ⎢sin(ωt - φ) - cosφ ⎥ ⎣ ⎦ ωL Z = R 2 + ω2 L2 ; tanφ = ; E = 2Vi sinθ; R = Zcosφ Where, R Now at steady state i 0 ωt=α = i0 ωt =π+α since i0 is periodic over the chosen interval. Using this i 0 = Ie

+

2Vi Z

boundary condition we obtain i0 =

( ωt-α ) 2Vi ⎡ 2sin(φ - α) e- tanφ + sin(ωt - φ) - sinθ ⎤ ⎢ ⎥ π cosφ Z ⎢ ⎥ ⎣ 1- e tanφ ⎦

The input current ii is related to i0 as follows: ii = i 0 for α ≤ ωt ≤ π + α ii = - i0 otherwise.

(10.26)

(10.27)

Fig 10.5 shows the waveform of ii in relation to the vi waveform.


It will be of interest to find out a Fourier series expression of ii. However, using actual expression for ii will lead to exceedingly complex calculation. Significant simplification can be made by replacing i0 with its average value I0. This will be justified provided the load is highly inductive and the ripple on i0 is negligible compared to I0. Under this assumption the idealized waveform of ii becomes a square wave with transitions at ωt = α and ωt = α + π as shown in Fig 10.5. ii1 is the fundamental component of this idealized ii. Evidently the input current displacement factor defined as the cosine of the angle between input voltage (vi) and the fundamental component of input current (ii1) waveforms is cosα (lagging). It can be shown that Ii1RMS =

2 2 I0 π


and

IiRMS = I0

(10.29)

Ii1RMS 2 2 = IiRMS π VI cosα Actual Power = i i1RMS The input power factor = Apparent Power Vi IiRMS

Therefore the input current distortion factor =

=

2 2 cosα (lagging) π

(10.30)

(10.31)

Therefore, the rectifier appears as a lagging power factor load to the input ac system. Larger the ‘α’ poorer is the power factor. The input current ii also contain significant amount of harmonic current (3rd, 5th, etc) and therefore appears as a harmonic source to the utility. Exact composition of the harmonic currents can be obtained by Fourier series analysis of ii and is left as an exercise. Exercise 10.2

Fill in the blank(s) with the appropriate word(s). i)

A single phase fully controlled bridge converter can operate either in the _________ or ________ conduction mode.

ii)

In the continuous conduction mode at least _________ thyristors conduct at all times.

iii)

In the continuous conduction mode the output voltage waveform does not depend on the ________ parameters.

iv)

The minimum frequency of the output voltage harmonic in a single phase fully controlled bridge converter is _________ the input supply frequency.

v)

The input displacement factor of a single phase fully controlled bridge converter in the continuous conduction mode is equal to the cosine of the ________ angle.

Answer: (i) continuous, discontinuous; (ii) two; (iii) load; (iv) twice; (v) firing.

2. A single phase fully controlled bridge converter operates in the continuous conduction mode from a 230V, 50HZ single phase supply with a firing angle α = 30°. The load resistance and inductances are 10Ω and 50mH respectively. Find out the 6th harmonic load current as a percentage of the average load current. Answer: The average dc output voltage is 2 2 VOAV = Vi cosα = 179.33 Volts π V Average output load current = OAV = 17.93 Amps RL From equation (10.18) Va3 = 10.25 Volts From equation (10.19) Vb3 = 35.5 Volts

∴ V03RMS = 26.126 Volts, Z3 = R 2L + (6× 2× π×50×50×10-3 ) 2 = 94.78 ohms Version 2 EE IIT, Kharagpur 16

∴ I3RMS =

V03RMS = 0.2756 Amps = 1.54% of I OAV . Z3

10.3.2 Operation in the discontinuous conduction mode So far we have assumed that the converter operates in continuous conduction mode without paying attention to the load condition required for it. In figure 10.4 the voltage across the R and L component of the load is negative in the region π - θ ≤ ωt ≤ π + α. Therefore i0 continues to decrease till a new pair of thyristor is fired at ωt = π + α. Now if the value of R, L and E are such that i0 becomes zero before ωt = π + α the conduction becomes discontinuous. Obviously then, at the boundary between continuous and discontinuous conduction the minimum value of i0 which occurs at ωt = α and ωt = π + α will be zero. Putting this condition in (10.26) we obtain the condition for continuous conduction as. 2sin(φ - α) 1- e

π tanφ

- sin(φ - α) -

sinθ ≥0 cosφ

(10.32)


Fig 10.6 shows waveforms of different variables on the boundary between continuous and discontinuous conduction modes and in the discontinuous conduction mode. It should be stressed that on the boundary between continuous and discontinuous conduction modes the load current is still continuous. Therefore, all the analysis of continuous conduction mode applies to this case as well. However in the discontinuous conduction mode i0 remains zero for certain interval. During this interval none of the thyristors conduct. These intervals are shown by hatched lines in the conduction diagram of Fig 10.6(b). In this conduction mode i0 starts rising from zero as T1T2 are fired at ωt = α. The load current continues to increase till ωt = π – θ. After this, the output voltage v0 falls below the emf E and i0 decreases till ωt = β when it becomes zero. Since the thyristors cannot conduct current in the reverse direction i0 remains at zero till ωt = π + α when T3 and T4 are fired. During the period β ≤ ωt ≤ π + α none of the thyristors conduct. During this period v0 attains the value E. Performance of the rectifier such as VOAV, VORMS, IOAV, IORMS etc can be found in terms of α, β and θ. For example Version 2 EE IIT, Kharagpur 18

Or

π+α 1 π+α 1⎡ β v dωt = 2V sinωt dωt + 0 i ∫β 2Vi sinθ dωt ⎤⎥⎦ (10.33) π ∫α π ⎢⎣ ∫α 2Vi (10.34) VOAV = [cosα - cosβ + sinθ(π + α - β)] π V - E VOAV - 2Vi sinθ (10.35) IOAV = OAV = R Zcosφ

Or

IOAV =

VOAV =

2Vi [cosα - cosβ + sinθ(α - β)] π Zcosφ

(10.36)

It is observed that the performance of the converter is strongly affected by the value of β. The value of β in terms of the load parameters (i.e, θ, φ and Z) and α can be found as follows. In the interval α ≤ ωt ≤ β di L o + Rio + E = 2Vi sinωt dt i 0 ωt =α = 0

(10.37)

From which the solution of i0 can be written as ( ) - ωt-α ⎤ 2Vi ⎡ ( ) sinθ tanφ - ωt-α i0 = sin(φ α)e + sin(ωt - φ) ⎥ ⎢ tanφ Z ⎣ cosφ 1- e ⎦

{

Now

i0

ωt=β

}

(10.38)

=0 α-β tanφ

α-β sinθ ⎡ ⎤ tanφ + sin(β - φ) = 0 ⎦ cosφ ⎣1- e Given φ, α and θ, the value of β can be found by solving equation 10.39.

∴ sin(φ - α)e

-

(10.39)

10.3.3 Inverter Mode of operation The expression for average dc voltage from a single phase fully controlled converter in continuous conduction mode was 2 2 (10.40) Vi cosα π For α < π/2, Vd > 0. Since the thyristors conducts current only in one direction I0 > 0 always. Therefore power flowing to the dc side P = V0I0 > 0 for α < π/2. However for α > π/2, V0 < 0. Hence P < 0. This may be interpreted as the load side giving power back to the ac side and the converter in this case operate as a line commutated current source inverter. So it may be tempting to conclude that the same converter circuit may be operated as an inverter by just increasing α beyond π/2. This might have been true had it been possible to maintain continuous conduction for α < π/2 without making any modification to the converter or load connection. To supply power, the load EMF source can be utilized. However the connection of this source in Fig 10.3 is such that it can only absorb power but can not supply it. In fact, if an attempt is made to supply power to the ac side (by making α > π/2) the energy stored in the load inductor will be exhausted and the current will become discontinuous as shown in Fig 10.7 (a). V0 =


Therefore for sustained inverter mode of operation the connection of E must be reversed as shown in Fig 10.7(b). Fig 10.8 (a) and (b) below shows the waveforms of the inverter operating in continuous conduction mode and discontinuous conduction mode respectively. Analysis of the converter remains unaltered from the rectifier mode of operation provided θ is defined as shown.


Exercise 10.3

Fill in the blank(s) with the appropriate word(s) i)

In the discontinuous conduction mode the load current remains __________ for a part of the input cycle.

ii)

For the same firing angle the load voltage in the discontinuous conduction mode is __________ compared to the continuous conduction mode of operation.

iii)

The load current ripple factor in the continuous conduction mode is _______ compared to the discontinuous conduction mode. Version 2 EE IIT, Kharagpur 21

iv)

In the inverter mode of operation electrical power flows from the ________ side to the __________side.

v)

In the continuous conduction mode if the firing angle of the converter is increased beyond _________ degrees the converter operates in the _______ mode.

Answers: (i) zero; (ii) higher; (iii) lower; (iv) dc, ac; (v) 90, inverter.

2. A 220 V, 20A, 1500 RPM separately excited dc motor has an armature resistance of 0.75Ω and inductance of 50mH. The motor is supplied from a 230V, 50Hz, single phase supply through a fully controlled bridge converter. Find the no load speed of the motor and the speed of the motor at the boundary between continuous and discontinuous modes when α = 25°. Answer: At no load the average motor torque and hence the average motor armature current is zero. However, since a converter carries only unidirectional current, zero average armature current implies that the armature current is zero at all time. From Fig 10.6(b) this situation can occur only when θ = π/2, i.e the back emf is equal to the peak of the supply voltage. Therefore, E b no load = 2 × 230 V = 325.27 V, Under rated condition E b 1500 = 205 V

325.27 ×1500 = 2380 RPM 205 At the boundary between continuous and discontinuous conduction modes from equation 10.32 1+ e -π/tanφ sinθ = cosφsin(φ - α) 1- e-π/tanφ From the given data φ = 87.27°, α = 25° ∴ sinθ = 0.5632 ∴ E b = 2Vi sinθ = 183.18 Volts 183.18 ∴ Motor speed N = ×1500 = 1340 RPM . 205 ∴ N no load =

Summary •

Single phase fully controlled converters are obtained by replacing the diodes of an uncontrolled converter with thyristors.

•

In a fully controlled converter the output voltage can be controlled by controlling the firing delay angle (α) of the thyristors.

•

Single phase fully controlled half wave converters always operate in the discontinuous conduction mode.

•

Half wave controlled converters usually have poorer output voltage form factor compared to uncontrolled converter.

•

Single phase fully controlled bridge converters are extensively used for small dc motor drives.


•

Depending on the load condition and the firing angle a fully controlled bridge converter can operate either in the continuous conduction mode or in the discontinuous conduction mode.

•

In the continuous conduction mode the load voltage depends only on the firing angle and not on load parameters.

•

In the discontinuous conduction mode the output voltage decreases with increasing load current. However the output voltage is always greater than that in the continuous conduction mode for the same firing angle.

•

The fully controlled bridge converter can operate as an inverter provided (i) α > π 2 , (ii) a dc power source of suitable polarity exists on the load side.

References 1) “Power Electronics” P.C.Sen; Tata McGraw-Hill 1995 2) “Power Electronics; Circuits, Devices and Applications”, Second Edition, Muhammad H.Rashid; Prentice-Hall of India; 1994. 3) “Power Electronics; Converters, Applications and Design” Third Edition, Mohan, Undeland, Robbins, John Wileys and Sons Inc, 2003.

Practice Problems and Answers Q1.

Is it possible to operate a single phase fully controlled half wave converter in the inverting mode? Explain.

Q2.

A 220V, 20A 1500 RPM separately excited dc motor has an armature resistance of 0.75Ω and inductance of 50 mH. The motor is supplied from a single phase fully controlled converter operating from a 230 V, 50 Hz, single phase supply with a firing angle of α = 30°. At what speed the motor will supply full load torque. Will the conduction be continuous under this condition?

Q3.

The speed of the dc motor in question Q2 is controlled by varying the firing angle of the converter while the load torque is maintained constant at the rated value. Find the “power factor” of the converter as a function of the motor speed. Assume continuous conduction and ripple free armature current.

Q4.

Find the load torque at which the dc motor of Q2 will operate at 2000 RPM with the field current and α remaining same.

Q5.

A separately excited dc motor is being braked by a single phase fully controlled bridge converter operating in the inverter mode as shown in Fig 10.7 (b). Explain what will happen if a commutation failure occurs in any one of the thyristors. Version 2 EE IIT, Kharagpur 23

Answers 1. As explained in section 10.3.3, the load circuit must contain a voltage source of proper polarity. Such a load circuit and the associated waveforms are shown in the figure next.

Figure shows that it is indeed possible for the half wave converter to operate in the inverting mode for some values of the firing angle. However, care should be taken such that i0 becomes zero before vi exceeds E in the negative half cycle. Otherwise i0 will start increasing again and the thyristor T will fail to commutate. 2. For the machine to deliver full load torque with rated field the armature current should be 20 Amps. 2 2 × 230 Assuming continuous conduction v 0 = cos30o = 179.33 volts. π For 20 Amps armature current to flow the back emf will be Eb = Va – IaRa = 179.33 – 20 × 0.75 = 164.33 volts E = 0.505 . ∴ sinθ = b 2Vi


For the given machine, tanφ =

ωL a = 20.944, φ = 87.266o . Ra

Now from equation (10.32) 2sin(φ - α) - sin(φ - α) = 11.2369. 1- e-π/tanφ sinθ and = 10.589 cosφ ∴ the conduction is continuous. At 1500 RPM the back emf is 220 – 20 × 0.75 = 205 volts. ∴The speed at which the machine delivers rated torques 164.33 is N r = ×1500 = 1202 RPM . 205 3.

To maintain constant load torque equal to the rated value the armature voltage should be N Va = ra I a rated + E b rated N rated N = 0.75 × 20 + 205 × = 0.137 N + 15 V 1500 In a fully controlled converter operating in the continuous conduction mode 2 2 Va = Vi cosα = 207.073 cosα π ∴ cosα = 6.616 × 10- 4 N + 0.0724 Now the power factor from equation 10.31 is 2 2 pf = cosα = 5.9565 × 10- 4 N + 0.0652 π This gives the input power factor as a function of speed.

4.

At 2000 RPM, E b = ∴ sinθ =

Eb

2000 × 205 = 273.33 volts 1500

= 0.84, φ = 87.266o , α = 30o

2Vi From equation 10.32 it can be shown that the conduction will be discontinuous. Now from equation 10.39

sinθ ⎡ sinθ ⎤ ⎢ cosφ + sin ( φ - α ) ⎥ = cosφ ⎣ ⎦ .0477(α - β) o e [17.61+ .8412] - sin ⎡⎣57.266 + ( α - β ) ⎤⎦ = 17.61

sin ⎡⎣( α - φ ) - ( α - β ) ⎤⎦ + e or

α -β tanφ

18.4515 e.0477(α - β) - sin ⎡⎣( α - β ) + 57.266o ⎤⎦ = 17.61 Solving which β ≈ 140°


∴ from equation 10.36 2Vi Ioav = [cosα - cosβ + sinθ(α - β)] = 2.676 Amps πZcosφ 2.676 ∴ the load torque should be ×100 = 13.38% of the full load torque. 20 5.

Referring to Fig 10.8 (a) let there be a commutation failure of T1 at ωt = α. In that case the conduction mode will be T3 T2 instead of T1 T2 and v0 will be zero during that period. As a result average value of V0 will be less negative and the average armature current will increase. However the converter will continue to operate in the inverter mode and the motor will be braked.



Lesson 11 Single Phase Half Controlled Bridge Converter Version 2 EE IIT, Kharagpur 2

Operation and analysis of single phase half controlled converters


Draw different topologies of single phase half controlled converter.

•

Identify the design implications of each topology.

•

Construct the conduction table and thereby draw the waveforms of different system variables in the continuous conduction mode of operation of the converter.

•

Analyze the operation of the converter in the continuous conduction mode to find out the average and RMS values of different system variables.

•

Find out an analytical condition for continuous conduction relating the load parameters with the firing angle.

•

Analyze the operation of the converter in the discontinuous conduction mode of operation.


11.1 Introduction Single phase fully controlled bridge converters are widely used in many industrial applications. They can supply unidirectional current with both positive and negative voltage polarity. Thus they can operate either as a controlled rectifier or an inverter. However, many of the industrial application do not utilize the inverter mode operation capability of the fully controlled converter. In such situations a fully controlled converter with four thyristors and their associated control and gate drive circuit is definitely a more complex and expensive proposition. Single phase fully controlled converters have other disadvantages as well such as relatively poor output voltage (and current for lightly inductive load) form factor and input power factor. The inverter mode of operation of a single phase fully controlled converter is made possible by the forward voltage blocking capability of the thyristors which allows the output voltage to go negative. The disadvantages of the single phase fully controlled converter are also related to the same capability. In order to improve the output voltage and current form factor the negative excursion of the output voltage may be prevented by connecting a diode across the output as shown in Fig 11.1(a). Here as the output voltage tries to go negative the diode across the load becomes forward bias and clamp the load voltage to zero. Of course this circuit will not be able to operate in the inverter mode. The complexity of the circuit is not reduced, however. For that, two of the thyristors of a single phase fully controlled converter has to be replaced by two diodes as shown in Fig 11.1 (b) and (c). The resulting converters are called single phase half controlled converters. As in the case of fully controlled converters, the devices T1 and D2 conducts in the positive input voltage half cycle after T1 is turned on. As the input voltage passes through negative going zero crossing D4 comes into conduction commutating D2 in Fig 11.1 (b) or T1 in Fig 11.1 (c). The load voltage is thus clamped to zero until T3 is fired in the negative half cycle. As far as the input and output behavior of the circuit is concerned the circuits in Fig 11.1 (b) and (c) are identical although the device designs differs. In Fig 11.1 (c) the diodes carry current for a considerably longer duration than the thyristors. However, in Fig 11.1 (b) both the thyristors and the diodes carry current for half the input cycle. In this lesson the operating principle and characteristics of a single phase half controlled converter will be presented with reference to the circuit in Fig 11.1 (b).


11.2 Operating principle of a single phase half controlled bridge converter With reference of Fig 11.1 (b), it can be stated that for any load current to flow one device from the top group (T1 or T3) and one device from the bottom group must conduct. However, T1 T3 or D2 D4 cannot conduct simultaneously. On the other hand T1 D4 and T3 D2 conducts simultaneously whenever T1 or T3 are on and the output voltage tends to go negative. Therefore, there are four operating modes of this converter when current flows through the load. Of course it is always possible that none of the four devices conduct. The load current during such periods will be zero. The operating modes of this converter and the voltage across different devices during these operating modes are shown in the conduction table of Fig 11.2. This table has been prepared with reference to Fig 11.1 (b).


It is observed that whenever D2 conducts the voltage across D4 is -vi and whenever D4 conducts the voltage across D2 is vi. Since diodes can block only negative voltage it can be concluded that D2 and D4 conducts in the positive and the negative half cycle of the input supply respectively. Similar conclusions can be drawn regarding the conduction of T1 and T3. The operation of the converter can be explained as follows when T1 is fired in the positive half cycle of the input voltage. Load current flows through T1 and D2. If at the negative going zero crossing of the input voltage load current is still positive it commutates from D2 to D4 and the load voltage becomes zero. If the load current further continuous till T3 is fired current commutates from T1 to T3. This mode of conduction when the load current always remains above zero is called the continuous conduction mode. Otherwise the mode of conduction becomes discontinuous. Exercise 11.1 Fill in the blanks(s) with the appropriate word(s) i. ii. iii. iv. v.

In a half controlled converter two ___________________ of a fully controlled converter are replaced by two ___________________. Depending on the positions of the ___________________ the half controlled converter can have ___________________ different circuit topologies. The input/output waveforms of the two different circuit topologies of a half controlled converter are ___________________ while the device ratings are ___________________. A half controlled converter has better output voltage ___________________ compared to a fully controlled converter. A half controlled converter has improved input ___________________ compared to a fully controlled converter.

Answer: (i) thyristors, diodes; (ii) diodes, two; (iii) same, different; (iv) form factor; (v) power factor.


2. Find out an expression of the ration of the thyristor to diode RMS current ratings in the single phase half controlled converter topologies of Fig. 11.1(b) & (c). Assume ripple free continuous output current. Answer

In the first conduction diagram the diodes and the thyristors conduct for equal periods, since the load current is constant. The ration of the thyristors to the diode RMS current ratings will be unity for the circuit of Fig 11.1 (b). From the second conduction diagram the thyristors conduct for π - α radians while the diodes conduct for π + α radians. Since the load current is constant. Thyristor RMS current rating 1− α / π = Diode RMS current rating 1+ α / π in this case

11.2.1 Single phase half controlled converter in the continuous conduction mode From the conduction table and the discussion in the previous section it can be concluded that the diode D2 and D4 conducts for the positive and negative half cycle of the input voltage waveform respectively. On the other hand T1 starts conduction when it is fired in the positive half cycle of the input voltage waveform and continuous conduction till T3 is fired in the negative half cycle. Fig. 11.3 shows the circuit diagram and the waveforms of a single phase half controlled converter supplying an R – L – E load.


Referring to Fig 11.3 (b) T1 D2 starts conduction at ωt = α. Output voltage during this period becomes equal to vi. At ωt = π as vi tends to go negative D4 is forward biased and the load current commutates from D2 to D4 and freewheels through D4 and T1. The output voltage remains clamped to zero till T3 is fired at ωt = π + α. The T3 D4 conduction mode continues upto ωt = 2π. Where upon load current again free wheels through T3 and D2 while the load voltage is clamped to zero. From the discussion in the previous paragraph it can be concluded that the output voltage (hence the output current) is periodic over half the input cycle. Hence 2Vi 1 π 1 π vo dωt = ∫ 2Vi sin ωt dωt = (1+ cosα) ∫ o α π π π V -E 2Vi Iov = oav = (1+ cosα - π sinθ) R πR Voav =

(11.1) (11.2)


Clearly in addition to the average component, the output voltage (and current) contains a large number of harmonic components. The minimum harmonic voltage frequency is twice the input supply frequency. Magnitude of the harmonic voltages can be found by Fourier series analysis of the load voltage and is left as an exercise. The Fourier series representation of the load current can be obtained from the load voltage by applying superposition principle in the same way as in the case of a fully controlled converter. However, the closed form expression of io can be found as explained next. In the period α ≤ ωt ≤ π

dio + Rio + E = 2Vi sin ωt dt (ωt-α) 2Vi ⎡ sinθ ⎤ io = I1e tanφ + sin(ωt - φ) ⎢ Z ⎣ cosφ ⎥⎦ E ωL ; Z = R2 + ω2 L2 ; tanφ = Where sinθ = R 2Vi L

⎡ sinθ ⎤ ⎢sin(α - φ) - cosφ ⎥ ⎣ ⎦ (π - α) 2Vi ⎡ sinθ ⎤ = I1 + sinφ ⎢ tanφ Z ⎣ cosφ ⎥⎦

io α = I1 + io

π

2Vi Z

(11.3) (11.4)

(11.5) (11.6)

In the period π ≤ ωt ≤ π + α L

dio + Rio + E = 0 dt


-

io = io π e ∴ ∴

-

io = I1 e io

(ωt-α) tanφ

-

π+α

(ωt-π) 2Vi sinθ ⎡ - tanφ ⎤ ⎢1- e ⎥ Z cosφ ⎢⎣ ⎥⎦ (ωt-π) 2Vi ⎡ sinθ ⎤ tanφ + ⎢sinφ e ⎥ Z ⎣⎢ cosφ ⎦⎥

(ωt-π) tanφ

= I1e

π tanφ

2Vi + Z

(11.8) (11.9)

α ⎡ sinθ ⎤ tanφ ⎢sinφ e ⎥ cosφ ⎦⎥ ⎣⎢

(11.10)

Due to periodic operation io α = io π+α

∴

I1 =

2Vi Z

-

sin(φ - α) + sinφ e -

1- e

α tanφ

(11.11)

π tanφ

∴ For α ≤ ωt ≤ π (ωt-α) ⎧ ⎫ α ⎡ ⎤ 2Vi ⎪ e tanφ sinθ ⎪ tanφ io = + sin(ωt - φ) ⎥ ⎨ ⎢sin(φ - α) + sinφe ⎬ π Z ⎪ ⎣⎢ cosφ ⎪ ⎦⎥ 1- e tanφ ⎩ ⎭

For

(11.12)

π ≤ ωt ≤ π + α (ωt-α) ⎧ ⎫ α (ωt-π) ⎡ ⎤ 2Vi ⎪ e tanφ sinθ ⎪ tanφ tanφ io = + sinφ e ⎥ ⎨ ⎢sin(φ - α) + sinφe ⎬ π Z ⎪ ⎣⎢ cosφ ⎪ ⎦⎥ 1- e tanφ ⎩ ⎭

(11.13)

The input current ii is given by ii = i0 ii = - i0 ii = 0

for α ≤ ωt ≤ π for π + α ≤ ωt ≤ 2π otherwise

(11.14)

However, it will be very difficult to find out the characteristic parameters of ii using equation 11.14 since the expression of i0 is considerably complex. Considerable simplification can however be obtained if the actual ii waveform is replaced by a quasisquare wave current waveform with an amplitude of Ioav as shown in Fig 11.5.


From Fig 11.5

IiRMS = 1- α/π Ioav

(11.15)

The displacement factor = cos α/2

(11.16)

∴

Vi Ii1 cos α = Vo I oav = 2

∴

Ii1 =

2Vi (1+ cosα)I OAV π

2 2 IOAV cos α 2 π

Ii1

(11.18) 2 cos α 2 π(π - α)

∴

Distortion factor =

∴

Power factor = displacement factor × distortion factor 2 = (1+ cosα) π(π - α)

IiRMS

=2

(11.17)

(11.19)

(11.20)

Exercise 11.2

Fill in the blank(s) with the appropriate word(s). i.

In a half controlled converter the output voltage can not become ___________________ and hence it can not operate in the ___________________ mode.

ii.

For the same firing angle and input voltage the half controlled converter gives ___________________ output voltage form factor compared to a fully controlled converter.

iii.

For ripple-free continuous output current the input current displacement factor of a half controlled converter is given by ___________________.

iv.

For the same supply and load parameters the output current form factor of a half controlled converter is ___________________ compared to a fully controlled converter. Version 2 EE IIT, Kharagpur 11

The free wheeling operating mode of a half controlled converter helps to make the output current ___________________. π Answer: (i) negative, inverter; (ii) lower; (iii) cos ; (iv) lower; (v) continuous. 2 2. A single phase half controlled converter is used to supply the field winding of a separately excited dc machine. With the rated armature voltage the motor operates at the rated no load speed for a fining angle α =0°. Find the value of α which will increase the motor no load speed by 30%. Neglect lasses and saturation. Assume continuous conduction. v.

Answer:

N NO load α 1

or φf α

φf

1 N NO load

In order to increase Nno load by 30% φf should be reduced by 23%. Therefore the applied field voltage must by 23%. Now by (11.1) Vf ( α ) = Vf ( α = 0 ) ∴ 1−

1 + cos α 1 − cos α = = 0.23 2 2 ∴ α = 57.4o

1 + cos α 2

11.2.2 Single phase half controlled converter in the discontinuous conduction mode. So far we have discussed the operating characteristics of a single phase half controlled converter in the continuous conduction mode without identifying the condition required to achieve it. Such a condition exists however and can be found by carefully examining the way this converter works. Referring to Fig 11.3 (b), when T1 is fired at ωt = α the output voltage (instantaneous value) is larger than the back emf. Therefore, the load current increases till vo becomes equal to E again at ωt = π – θ. There, onwards the load current starts decreasing. Now if io becomes zero before T3 is fired at ωt = π + α the conduction becomes discontinuous. So clearly the condition for continuous conduction will be

io

ωt

=α≥0

(11.21)

Which in conjunction with the equation (11.12) gives -

sin(φ - α) + sinφ e π tanφ

1- e

α tanφ

- sin(φ - α) ≥

sinθ cosφ


-

or

sin(φ - α)e

π tanφ

+ sinφ e

π tanφ

1- e

-

α tanφ

≥

sinθ cosφ

(11.22)

If the condition in Eq. 11.22 is violated the conduction will become discontinuous. Clearly, two possibilities exist. In the first case the load current becomes zero before ωt = π. In the second case io continuous beyond ωt = π but becomes zero before ωt = π + α. In both cases however, io starts from zero at ωt = α. Fig. 11.6 shows the wave forms in these two cases.

Of these two cases the second one will be analyzed in detail here. The analysis of the first case is left as an exercise. For this case vo = vi vo = 0 vo = E

for α ≤ ωt ≤ π for π ≤ ωt ≤ β for β ≤ ωt ≤ π + α

(11.23)


Therefore

1 π+α v o dωt π ∫α π+α 1 π 2vi sinθ dωt ⎤ = ⎡ ∫ 2vi sinωt dωt + ∫ ⎢ α β ⎣ ⎦⎥ π 2Vi = [1+ cosα + (π + α - β)sinθ ] π

VOAV =

IOAV = VORMS

(11.24)

VOAV - E 2Vi = [1+ cosα + (α - β)sinθ] R π Z cosφ 1 π+α 2 = vo dωt π ∫α

(11.25)

1

π+α 1 π 2 = ⎡ ∫ 2vi2 sin 2 ωt dωt + ∫ 2vi2 sin 2θ dωt ⎤ ⎢ ⎥ α β ⎣ ⎦ π 1

=

2Vi ⎡ π - α 1 ⎤2 + (π + α - β) sin 2θ + sin 2α ⎥ ⎢ π ⎣ 2 4 ⎦

(11.26)

However IORMS cannot be computed directly from VORMS. For this the closed form expression for io has to be obtained. This will also help to find out an expression for the conduction angle β. For α ≤ ωt ≤ π 2Vi sin ωt = Ri o + L

di o +E dt

(11.27)

The general solution is given by (ωt-α) tanφ

2Vi 2Vi sinθ sin(ωt - φ) Z Z cosφ Where Z = R 2 + ω2 L2 ; tanφ = ωL ; E = 2Vi sinθ R At ωt = α, io = 0 -

io = Io e

+

(11.28)

⎤ 2Vi ⎡ sinθ + sin(φ - α) ⎥ ⎢ Z ⎣ cosφ ⎦ ωt-α ⎤ - tanφ 2Vi ⎧⎪ ⎡ sinθ sinθ ⎫⎪ io = + sin(φ α) e + sin(ωt φ) ∴ ⎨ ⎬ ⎥ Z ⎪⎩ ⎢⎣ cosφ cosφ ⎪⎭ ⎦ α-π ⎤ tanφ 2Vi ⎧⎪ ⎡ sinθ sinθ ⎫⎪ + sin(φ - α) ⎥ e + sinφ io at ωt = π = ⎨⎢ ⎬ Z ⎩⎪ ⎣ cosφ cosφ ⎭⎪ ⎦ ∴

Io =

(11.29) (11.30) (11.31)

For π ≤ ωt ≤ β O = Ri o + L

di o +E dt

(11.32)


-

∴ io

io = I1 e ωt = π

= I1 -

ωt-π tanφ

2Vi sinθ Z cosφ

-

(11.33)

2Vi sinθ Z cosφ

α-π ⎧⎪ ⎡ sinθ ⎤ tanφ sinθ ⎫⎪ + sin(φ α) e + sinφ = ⎨⎢ ⎬ ⎥ cosφ ⎪⎭ ⎦ ⎩⎪ ⎣ cosφ α-π ⎤ tanφ 2Vi ⎧⎪ ⎡ sinθ ⎪⎫ I1 = + sin(φ α) e + sinφ ⎨ ⎬ ⎥ Z ⎪⎩ ⎢⎣ cosφ ⎦ ⎪⎭ ωt-α ωt-π ⎤ - tanφ 2Vi ⎧⎪ ⎡ sinθ sinθ ⎫⎪ io = + sin(φ - α) ⎥ e + sinφe tanφ ⎨⎢ ⎬ Z ⎩⎪ ⎣ cosφ cosφ ⎭⎪ ⎦

2Vi Z

∴ ∴

(11.34) (11.35) (11.36)

Equations (11.30) and (11.36) gives closed from expression of io in this conduction mode. To find out β we note that at ωt = β, io = 0. So from equation (11.36) α-β

π-β

⎡ sinθ ⎤ tanφ sinθ + sinφ e tanφ =0 ⎢ cosφ + sin(φ - α) ⎥ e cosφ ⎣ ⎦ β

or

π

α

(11.37) α

sinθ tanφ sinθ tanφ e = sinφ e tanφ + sin(φ - α) e tanφ + e cosφ cosφ

(11.38)

Given the values of ϕ, θ and α the value of β can be obtained from equation 11.38. Exercise 11.3 (After section 11.2.2)


At the boundary between continuous and discontinuous conduction the value of the output current at ωt = α is ___________________.

ii.

The output voltage and current waveform of a single phase fully controlled and half controlled converter will be same provided the extinction angle β is less than ___________________.

iii.

For the same value of the firing angle the average output voltage of a single phase half controlled converter is ___________________ in the discontinuous conduction mode compared to the continuous conduction mode.

iv.

Single phase half controlled converters are most suitable for loads requiring ___________________ voltage and current.

Answer: (i) zero; (ii) π; (iii) higher; (iv) unidirectional.

2. A single phase half controlled converter charges a 48v 50Ah battery from a 50v, 50Hz single phase supply through a 50mH line inductor. The battery has on interval resistance of 0.1Ω. The Version 2 EE IIT, Kharagpur 15

firing angle of the converter is adjusted such that the battery is charged at C/5 rate when it is fully discharged at 42 volts. Find out whether the conduction will be continuous or discontinuous at this condition. Up to what battery voltage will the conduction remain continuous? If the charging current of the battery is to become zero when it is fully charged at 52 volts what should be the value of the firing angle. Answer: From the given data assuming continuous conduction the output voltage of the converter to charge the battery at C/5 (10 Amps) rate will be

Vo = E + Ib rb = 42 + 0.1×10 = 43volts ∴ α = 24.43o

φ = tan −1

ωL = 89.63o , tan φ = 157.08, sin φ = 0.99998 cos φ = 6.3 × 10−3 R

Putting these values in equation (11.22) one finds that the conduction will be continuous. The conduction will remain continuous till

sin θ =

E = 2vi

cos φ sin ( φ − α ) e

− π tan φ

1− e

−π

−α tan φ 1 + sin 2φ e 2

tan φ

From the given value this gives. E = 2 × 50 × 0.606 = 42.8V

At E = 52 volts io is zero. Therefore

2Vi sin α = E = 52 sin 52 ∴ α = 180o − = 132.66o 2 × 50

References [1]

“Power Electronics”; P.C. Sen; Tata McGraw Hill Publishing Company Limited 1995.

[2]

“Power Electronics, circuits, devices and applications”; Second Edition; Muhammad H. Rashid; Prentice – Hall of India; 1994.

[3]

“Power Electronics, converters, applications and design”; Third Edition; Mohan, Undeland, Robbins; John Wiley and Sons Inc., 2003.


Lesson Summary •

Single phase half controlled converters are obtained from fully controlled converters by replacing two thyristors by two diodes.

•

Two thyristors of one phase leg or one group (top or bottom) can be replaced resulting in two different topologies of the half controlled converter. From the operational point of view these two topologies are identical.

•

In a half controlled converter the output voltage does not become negative and hence the converter cannot operate in the inverter mode.

•

For the same firing angle and input voltage the half controlled converter in the continuous conduction mode gives higher output voltage compared to a fully controlled converter.

•

For the same input voltage, firing angle and load parameters the half controlled converter has better output voltage and current form factor compared to a fully controlled converter.

•

For the same firing angle and load current the half controlled converter in the continuous conduction mode has better input power factor compared to a fully controlled converter.

•

Half controlled converters are most favored in applications requiring unidirectional output voltage and current.

Practice Problems and Answers Q1. The thyristor T3 of Fig 1.1(b) fails to turn on at the desired instant. Describe how this circuit will work in the presence of the fault. Q2. A single phase half controlled converter is used to boost the no load speed of a separately excited dc machine by weakening its field supply. At α = 0° the half controlled converter produces the rated field voltage. If the field inductance is large enough to make the field current almost ripple face what will be the input power factor when the dc motor no load speed is bossed to 150%? Q3.

A single phase half controlled converter supplies a 220V, 1500rpm, 20A dc motor from a 230V 50HZ single phase supply. The motor has a armature resistance of 1.0Ω and inductance of 50mH. What will be the operating modes and torques for α = 30°; and speed of 1400 RPM.


Answer to practice problems

Figure above explains the operation of the circuit following the fault. T1 is tired at ωt = α and the load current commutates from T3 to T1. The conduction periods T1 D2 & T1 D4 commences as usual. However at ωt = π + α when T3 is fired it fails to turn ON and as a consequences T1 does not commutate. Now if the load is highly inductive T1 D4 will continue to conduct till ωt = 2π and the load voltage will be clamped to zero during this period. However, since T1 does not stop conduction fining angle control on it is lost after words. Hence T1 D2 conduction period starts right after ωt = 2π instead of at ωt = 2π + α. Thus the full positive half cycle of supply voltage is applied across the load followed by a entire half cycle of zero voltage. Thus the load voltage becomes a half wave rectified sine wave and voltage control through fining angle is last. This is the effect of the fault. [Note: This phenomenon is known as “half cycle brusting”. It can be easily verified that this possibility does not existion the circuit shown in Fig 11.1 (c)] 2.

For a separately excited dc motor

ωNO load α

1 1 α φf Vf

Vf rated for boosting no load speed by 150% 1.5 Vf 1 + cos α 1 = = but Vf rated 2 1.5

∴ Vf =

∴ α = 70.53o

using equation 11.20 the power factor will be 0.77.


3.

From

the

given

data,

tanφ

=

ωL = 15.7, φ = 86.36o R

E 14 220 − 20 × 1.0 = × = 0.578 substituting these values in equation 11.22 it can be 2Vi 15 2 × 230 conducted that the conduction is continuous sinθ =

∴ Va = 193.2V, E = 186.7V V −E ∴ Ia = a = 6.53A ra 6.53 ∴ Motor torque will be ×100 = 32.67% of full load torque. 20



Lesson 12 Single Phase Uncontrolled Rectifier Version 2 EE IIT, Kharagpur 2

Operation and Analysis of three phase uncontrolled rectifier.


Draw the conduction table and waveforms of a three phase half wave uncontrolled converter supplying resistive and resistive inductive loads.

•

Calculate the average and RMS values of the input / output current and voltage waveforms of a three phase uncontrolled half wave converter.

•

Analyze the operation of a three phase full wave uncontrolled converter to find out the input / output current and voltage waveforms along with their RMS and Average values.

•

Find out the harmonic components in the input / output voltage and current waveforms of a three phase uncontrolled full wave converter.

•

Analyze the operation of a three phase full wave uncontrolled converter supplying a Capacitive – Resistive load.


12.1 Introduction Single phase rectifiers, as already discussed, are extensively used in low power applications particularly for power supplies to electronic circuits. They are also found useful for supplying small dc loads rarely exceeding 5 KW. Above this power level three phase ac – dc power supplies are usually employed. Single phase ac – dc converters have several disadvantages such as •

Large output voltage and current form factor.

•

Large low frequency harmonic ripple current causing harmonic power loss and reduced efficiency.

•

Very large filter capacitor for obtaining smooth output dc voltage.

•

Low frequency harmonic current is injected in the input ac line which is difficult to filter. The situation becomes worse with capacitive loads.

Many of these disadvantages are mitigated to a large extent by using three phase ac – dc converters. In a way it is also natural that bulk loads are supplied by three phase converters since bulk electrical power is always transmitted and distributed in three phases and high power should load three phases symmetrically. Polyphase rectifiers produce less ripple output voltage and current compared to single phase rectifiers. The efficiency of polyphase rectifier is also higher while the associated equipments are smaller. A three phase supply gives the choice of a number of circuits. These can be placed in one of two groups according to whether three or six diodes are used. These topologies will be analyzed in detail in this section.

12.2 Operating principle of three phase half wave uncontrolled rectifier The half wave uncontrolled converter is the simplest of all three phase rectifier topologies. Although not much used in practice it does provide useful insight into the operation of three phase converters. Fig. 12.1 shows the circuit diagram, conduction table and wave forms of a three phase half wave uncontrolled converter supplying a resistive inductive load.


For simplicity the load current (io) has been assumed to be ripple free. As shown in Fig. 12.1 (a), in a three phase half wave uncontrolled converter the anode of a diode is connected to each phase voltage source. The cathodes of all three diodes are connected together to form the positive load terminal. The negative terminal of the load is connected to the supply neutral. Fig. 12.1 (b) shows the conduction table of the converter. It should be noted that for the type of load chosen the converter always operates in the continuous conduction mode. The conduction diagram for the diodes (as shown in Fig. 12.1 (c) second waveform) can be drawn easily from the conduction diagram. Since the diodes can block only negative voltage it follows from the conduction table that a phase diode conducts only when that phase voltage is maximum Version 2 EE IIT, Kharagpur 5

of the three. (In signal electronics the circuit of Fig. 12.1 (a) is also known as the “maximum value” circuit). Once the conduction diagram is drawn other waveforms of Fig. 12.1 (c) are easily obtained from the supply voltage waveforms in conjunction with the conduction table. The phase current waveforms of Fig. 12.1 (c) deserve special mention. All of them have a dc component which flows through the ac source. This may cause “dc saturation” in the ac side transformer. This is one reason for which the converter configuration is not preferred very much in practice. From the waveforms of Fig. 12.1 (c)

3 5π/6 2Vi sin ωt d(ωt) 2π ∫π/6 3 6 Vi = 2π

VOAV =

(12.1) 1

VORMS

⎡ 3 5π/6 ⎤2 = ⎢ ∫ 2Vi2 sin 2 ωt d(ωt) ⎥ ⎣ 2π π/6 ⎦ 1

⎡ 3 3 ⎤2 = ⎢1 + ⎥ Vi 4π ⎦ ⎣

(12.2)

∴ The output voltage form factor =

IO av =

VORMS = 1.01 VOAV

(12.3)

VOAV , R

Ii RMS = I a RMS = I b RMS = I c RMS =

IO 3

(12.4)

3 6 Vi IO 3 AV = 2π = ∴ Input power factor = (12.5) IO 3Vi Ii RMS 2π 3Vi 3 The harmonics present in vo and ii can be found by Fourier series analysis of the corresponding waveforms of Fig. 12.1 (c) and is left as an exercise. VO av IO

Exercise 12.1


Three phase half wave uncontrolled rectifier uses ________ diodes.

ii)

Three phase half wave uncontrolled rectifier requires ________ phase ______ wire power supply. Version 2 EE IIT, Kharagpur 6

iii)

In a three phase half wave uncontrolled rectifier each diode conduct for _________ radians.

iv)

The minimum frequency of the output voltage ripple in a three phase half wave uncontrolled rectifier is _________ times the input voltage frequency.

v)

The input line current of a three phase half wave uncontrolled rectifier contain ________ component.

Answers: (i) three; (ii) three, four; (iii) 2π/3; (iv) three; (v) dc.

2. Assuming ripple free output current, find out the, displacement factor, distortion factor and power factor of a three phase half wave rectifier supplying an R – L load. With reference to Fig 12.1 the expression for phase current ia can be written as π 5π ≤ ωt ≤ 6 6 otherwise.

i a = Id ia = 0

Fundamental component of ia can be written as

i a1 = 2 Ia1 sin(ωt + φ)

2 Ia1 = A12 + B12 and φ = tan -1

where

A1 B1

1 2π i a cosωt dωt π ∫0 1 2π B1 = ∫ i a sinωt dωt π 0

A1 =

∴

5π

1 A1 = ∫π6 Id cosωt dωt = 0 π 6 5π

B1 =

1 6 3 Id π I d sinωt dωt = ∫ π 6 π

3 Id 3 ∴ Ia1 = Id 2 π π φ = 0 ∴ Displacement factor = cosφ = 1. ∴

2I a1 = B1 =

R.M.S value of ia = Ia = ∴ Distortion factor =

Id 3

Ia1 3 = Ia 2π

Power Factor = Disp. Factor × Dist. Factor =

3 2π


12.3 Three phase full wave uncontrolled converter As has been explained earlier three phase half wave converter suffers from several disadvantages. Chief among them are dc component in the input ac current, requirement of neutral connection and comparatively lower output voltage. In addition the input and output waveforms contain lower order harmonics which require heavy filtering. Most of these disadvantages can be mitigated by using a three phase full wave bridge rectifier. This is probably the most extensively used rectifier topology from low (>5 KW) to moderately high power (> 100 KW) applications. In this section the operation of a three phase full wave uncontrolled bridge rectifier with two different types of loads namely the R – L – E type load and the capacitive load will be described.

12.3.1 Operation of a 3 phase full wave uncontrolled bridge rectifier supplying an R – L – E load This type of load may represent a dc motor or a battery. Usually for driving these loads a variable output voltage is required. This requirement has to be met by using a variable ac source (e.g a 3 phase variable) since the average output voltage of an uncontrolled rectifier is constant for a given ac voltage. It will also be assumed in the following analysis that the load side inductance is large enough to keep the load current continuous. The relevant condition for continuous conduction will be derived but analysis of discontinuous conduction mode will not be attempted. Compared to single phase converters the cases of discontinuous conduction in 3 phase bridge converter are negligible.



Since the load current is assumed to be continuous at least one diode from the top group (D1, D3 and D5) and one diode from the bottom group (D2, D4 and D6) must conduct at all time. It can be easily verified that only one diode from each group (either top or bottom) conducts at a time and two diodes from the same phase leg never conducts simultaneously. Thus the converter Version 2 EE IIT, Kharagpur 10

has six different diode conduction modes. These are D1D2, D2D3, D3D4, D4D5, D5D6 and D6D1. Each conduction mode lasts for π/3 rad and each diode conducts for 120º. Fig. 12.2 (b) shows voltages across different diodes and the output voltage in each of these conduction modes. The time interval during which a particular conduction mode will be effective can be ascertained from this table. For example the D1D2 conduction mode will occur when the voltage across all other diodes (i.e. vba, vca and vcb) are negative. This implies that D1D2 conducts in the interval 0 ≤ ωt ≤ π/3 as shown in Fig. 12.2 (c). The diodes have been numbered such that the conduction sequence is D1 → D2 → D3 → D4 → D5 → D6 → D1---. When a diode stops conduction its current is commutated to another diode in the same group (top or bottom). This way the sequence of conduction modes become, D1D2 → D2D3 → D3D4 → D4D5 → D5D6 → D6D1 → D1D2 ---. The conduction diagram in Fig. 12.2 (c) is constructed accordingly. The output dc voltage can be constructed from this conduction diagram using appropriate line voltage segments as specified in the conduction table. The input ac line currents can be constructed from the conduction diagram and the output current. For example for 0 ≤ ωt ≤ π/3 and 5π/3 ≤ ωt ≤ 2π ia = io for 2π/3 ≤ ωt ≤ 4π/3 ia = - io otherwise. (12.6) ia = 0 The line current wave forms and their fundamental components are shown in Fig. 12.2 (c). It is clear from Fig 12.2 (c) that the dc voltage output is periodic over one sixth of the input ac cycle. For

π/3 ≤ ωt ≤ 2π/3 v o = 2VL sin ωt

VOAV =

(12.7)

3 2π/3 3 2 2VL sin ωt dωt = VL ∫ π/3 π π

VORMS =

3 2π/3 2 2VL sin 2 ωt dωt ∫ π/3 π

⎛ 3 3⎞ = ⎜⎜ 1 + ⎟VL 2π ⎟⎠ ⎝

Ii RMS =

(12.8)

2 IOAV ; 3

IOAV =

Ii1 RMS can be found as follows 3 VL Ii 1 = VOAV IOAV

(12.9)

VOAV − E R

(12.10)

(12.11)


Since input displacement factor is unity

∴ Ii1 =

VOAV 6 IOAV = IOAV π 3VL

(12.12) Ii1

3 Ii RMS π A closed form expression for io can be found as follows

∴ Power factor = distortion factor =

(12.13)

=

for π/3 ≤ ωt ≤ 2π/3 di o L + Ri o + E = v o = 2VLsinωt dt

(12.14)

The general solution is given by

io = I1e

-

Where tanφ =

ωt - π/3 tanφ

+

ωL ; R

2VL ⎡ sinθ ⎤ sin(ωt - φ) ⎢ Z ⎣ cosφ ⎥⎦ E sinθ = ; Z = R 2 + ω2 L2 2VL

(12.15)

Now since the current waveform is periodic over one sixth of the input ac cycle π⎞ 2π ⎞ ⎛ ⎛ i o ⎜ ωt = ⎟ = i o ⎜ ωt = ⎟ 3⎠ 3 ⎠ ⎝ ⎝

∴

2VL I1 + Z

∴

I1 =

∴

2VL Z

(12.16) π

⎡ ⎛ π ⎞ sinθ ⎤ 2VL ⎡ ⎛ 2π ⎞ sinθ ⎤ 3tanφ sin φ = I e + sin ⎜ - φ ⎟ ⎥ ⎢ ⎜ 3 ⎟ cosφ ⎥ 1 Z ⎢⎣ ⎝ 3 ⎠ ⎠ cosφ ⎦ ⎣ ⎝ ⎦

sinφ 1- e

-

(12.17)

(12.18)

π 3tanφ

ωt - π/3 ⎡ ⎤ 2VL ⎢ sinφ - 3tanφ sinθ ⎥ io = e + sin ( ωt - φ ) π Z ⎢ - 3tanφ cosφ ⎥ ⎣1- e ⎦

(12.19)

Exercise 12.2


Three phase full wave uncontrolled rectifier uses _________ diodes.

ii)

Three phase full wave uncontrolled rectifier does not require ________ wire connection.

iii)

In a three phase full wave uncontrolled rectifier each diode conducts for _______ radians. Version 2 EE IIT, Kharagpur 12

iv)

The minimum frequency of the output voltage ripple in a three phase full wave rectifier is _________ times the input voltage frequency.

v)

The input ac line current of a three phase full wave uncontrolled rectifiers supplying an R – L – E load contain only ________ harmonics but no ________ harmonic or __________ component.

vi)

A three phase full wave uncontrolled rectifier supplying an R – L – E load normally operates in the ________ conduction mode.

Answers: (i) six; (ii) neutral; (iii) 2π/3; (iv) six; (v) odd, tripler, dc; (vi) continuous.

2. A 220 V, 1500 rpm 20 A separately excited dc motor has armature resistance of 1Ω and negligible armature inductance. The motor is supplied from a three phase full wave uncontrolled rectifier connected to a 220 V, 3 phase, 50 Hz supply through a Δ/Y transformer. Find out the transformer turns ratio so that the converter applies rated voltage to the motor. What is the maximum torque as a percentage of the rated torque the motor will be able to supply without over heating. Assume ideal transformer and continuous conduction. Answer: Average output voltage of the converter is 3 2 VL = 220V π ∴ VL = 163 Volts. This is the line voltage of the secondary side of the transformer. The secondary is star connected. So 163 Secondary phase voltage = = 94 volts . 3 Primary side is delta connected. So Primary phase voltage = 220 V. 220 = 2.34 :1 ∴ The required turns ratio = 94 V0 =

Output voltage can be written as α

v 0 = V0 + ∑ v hn

Where vhn = nth harmonic voltage magnitude.

n =1

V0 - E α v hn +∑ r n =1 r Where E = back emf and r = armature resistance

∴

i0 =

2

∴

2

I 0RMS

α ⎛ V -E⎞ ⎛ Vhn ⎞ =⎜ 0 + ⎟ ⎟ ∑⎜ ⎝ r ⎠ n=1 ⎝ r ⎠

2

2 2 α V0AV V0AV ⎛ Vhn ⎞ + + ∑ ⎜ ⎟ 2 2 r r n=1 ⎝ r ⎠ 2 V2 V0RMS 2 = I 0AV - 0AV + r2 r2

2

2 = I0AV -


2 = I 0AV +

2 V0AV ( FF2 -1) r2

To prevent over heating I0RMS = 20 A 2 ⎛ V0RMS ⎞ 2 For the given converter FF = ⎜ ⎟ = 1.00176 ⎝ V0AV ⎠ 2202 (1.00176 -1) 1 ∴ I0AV = 17.743 Amps. = 314.816

∴

2 202 = I 0AV +

∴

2 I 0AV

In a separately excited dc machine Te ∝ I0AV ∴ Maximum allowable torque =

17.743 ×100 = 88.715 % of full load torque. 20

12.3.2 Operation of a three phase uncontrolled bridge rectifier supplying a capacitive load A three phase uncontrolled bridge rectifier supplying a capacitive load is a very popular power electronic converter. It is very widely used as the front end of a variable voltage variable frequency dc – ac inverter. Fig. 12.3 (a) shows the power circuit diagram of such a converter. Operation of the converter can be explained as follows. The top group diodes (D1, D3, D5) form a “Maximum value circuit” and therefore the maximum of the phase voltages van, vbn, vcn appears at the positive dc bus. On the other hand, the bottom group diodes (D2, D4, D6) form a “Minimum value circuit”. Therefore the minimum of the phase voltages van, vbn and vcn appears at the negative dc bus. Therefore, the output voltage waveform at any instant is equal to the maximum of the six line voltages vab, vbc, vca, vba, vcb and vac provided at least one diode from the top group and one from the bottom group conducts at that instant. None of the diodes will conducts, however if the output capacitor voltage is larger than the maximum line voltage. All the six operating modes of a 3 phase bridge rectifier namely, D1D2, D2D3, D3D4, D4D5, D5D6 and D6D1 appear in that order. In addition an additional operating mode in which none of the diodes conduct appears in the conduction diagram as shown in Fig. 12.3 (b). During these periods the output capacitor discharges through the load. As the capacitor voltage decreases its voltage becomes equal to the incoming line voltage. At this instant the appropriate diodes from both the top and the bottom group starts conducting and continuous to do so till the sum of the capacitor charging current and the load current becomes zero.



From Fig. 12.3 (b) In the interval α ≤ ωt ≤ β

v o = 2VL sin ωt

(12.20)

dvo = 2VL ωc cos ωt dt v V i o = o = 2 L sin ωt R R VL ∴ ii = i o + i c = 2 [ ωRC cos ωt + sin ωt ] R V = 2 L 1+ ω2 R 2 C2 cos (ωt - φ) R 1 Where tanφ = ωRC ∴ ic = c

(12.21) (12.22)

(12.23)

At ωt = β, ii = 0 ∴ cos (β - φ) = 0

or β =

π +φ 2

(12.24)

in the interval β ≤ ωt ≤ α + π/3 c

dvo v o + =0 dt R

v o β = 2VL sinβ = 2VL cosφ = 2VL

∴ vo = vo β e

-

(ωt - β) ωRC

= 2VL

ωRC 1+ ω2 R 2 C 2

e

-

(ωt - β) ωRC

ωRC 1+ ω 2 R 2 C 2

(12.25)

(12.26)

at ωt = α + π/3 v o = 2VL

ωRC 1+ ω2 R 2 C 2

e

π/6 - α + φ ωRC

(12.27)

Also at ωt = α + π/3 π⎞ ⎛ v o = 2VL sin ⎜ ωt - ⎟ 3 ⎠ ωt = α + π ⎝

3

= 2VL sin α


∴ sinα =

1 π/6 - α + tan -1 ωRC

ωRC 2

2

1+ ω R C

2

e

(12.28)

ωRC

From which the value of α can be found. Equation 12.23 gives the expression of the output current ii of the rectifier. It is observed that ii is discontinuous and contains large ripple. This is a major disadvantage of this converter. This ripple is also reflected in the input current of the rectifier as shown in Fig 12.3 (b). However, the displacement factor of the converter still remains unity. The current ii can be made continuous by connecting an inductor of appropriate value between the rectifier and the capacitor. Analysis of such a converter is similar to a converter V supplying an R – L – E load where the value of E is 3 2 L . π Exercise 12.3

Fill in the blank(s) with the appropriate word(s) i)

A three phase full wave uncontrolled rectifier supplying a capacitive load can operate in the _________ conduction mode.

ii)

The output _________ ripple factor of a three phase full wave uncontrolled rectifier supplying a capacitive load is very low.

iii)

The output _________ ripple factor of a three phase full wave uncontrolled rectifier supplying a capacitive load is very high.

iv)

The input current displacement factor of a three phase full wave uncontrolled rectifier supplying a capacitive load is ___________.

v)

The input current distortion factor of a three phase full wave uncontrolled rectifier supplying a capacitive load is very ________.

Answers: (i) discontinuous; (ii) voltage; (iii) current; (iv) unity; (v) high.

2. A three phase full wave rectifier operates from 220 volts, three phase 50 Hz supply and supplies a capacitive resistive load of 20 Amps. An inductor of negligible resistance is inserted between the rectifier and the capacitor. Assuming the capacitor to be large enough so that the output voltage is almost ripple free. Calculate the value of the inductor so that the rectifier output current is continuous. Answers: The following figure shows the circuit arrangement and the corresponding waveforms.


Since the conduction is continuous V0 3 3 2 = or θ = 72.73º V0 = VL and sinθ = π 2VL π In the interval

π 2π ≤ ωt ≤ 3 3 di v0 + L L = 2VL sinωt dt

Since v0 is almost ripple free v0 = V0 = ∴

Now

3 2 VL π

di 3 2 VL + ωL L = 2VL sinωt π dωt 2VL 3 2 i L = I0 cosωt VL ωt ωL πωL i L av = 20A


∴

I0 -

3VL 3 2 1 π2 3 VL × × × = 20A or I 0 = 20 + πωL 2 3 π 2ωL

2VL ⎡ 3 3 ⎤ - cosωt - ωt ⎥ ⎢ ωL ⎣ 2 π ⎦ For just continuous conduction iL = 0 at ωt = θ 2VL ⎡ 3 3 ⎤ 0 = 20 + - cosθ - θ ⎥ ∴ ⎢ ωL ⎣ 2 π ⎦ or ωL = 1.0306 Ω or L = 3.28 mH. ∴

i L = 20 +

References [1]

“Power Electronics”, P.C. Sen; Tata MC Grawhill publishing company limited; 1995.

[2]

“Power Electronics, Converters, Applications and Design”; Mohan, Undeland, Robbins; John Willey and Sons Ine, Third Edition, 2003.

Lesson Summary •

Three phase uncontrolled rectifiers are available in half wave and full wave configuration.

•

Three phase uncontrolled half wave rectifier require three phase four wire power supply.

•

The input ac line current in a three phase uncontrolled half wave rectifier contain dc component which may cause “dc saturation” of input transformer.

•

Three phase full wave uncontrolled rectifier is most widely used in the medium power applications particularly as the input stage of the dc link inverter.

•

Three phase full wave uncontrolled rectifier uses six diodes instead of three of the half wave rectifier.

•

Full bridge rectifier does not require neutral connection.

•

The output voltage of a three phase full bridge rectifier contains multiplies of 6th harmonic of input cycle.

•

The input ac current of a three phase full bridge rectifier contain only odd harmonics but no dc component or triplen harmonics.

•

The input displacement factor of the three phase bridge rectifier is always unity.

•

Three phase full bridge converter supplying an R – L – E load usually operate in the continuous conduction mode.

•

Compared to single phase rectifiers, three phase bridge converter require smaller inductor to obtain the same output current ripple factor. Version 2 EE IIT, Kharagpur 19

•

Three phase bridge rectifier supplying a capacitive load has very good output voltage form factor but very poor input current THD.

•

Compared to single phase converters three phase bridge rectifier require smaller capacitor to obtain a given output voltage form factor.

Practice Problems and Answers Q1.

A three phase half wave rectifier operates from a three phase 220 V, 50 Hz supply and supplies a resistive load rated at 200 Volts 1 KW through an inductance large enough to make the load current ripple free. Find out the power consumed by the load? What will be the load power if the inductor is shorted?

Q2.

A three phase full wave rectifier operates from a three phase 220 V 50 Hz supply through a three phase Δ/Y transformer and supplies a 200 V 1500 R.P.M, 50 Amps separately excited dc motor. Find out the turns ratio of the transformer so that the motor operates at rated speed at full load. If the motor armature resistance is 0.5 Ω find out the inductance to be connected in series with the motor such that the rectifier operates in the continuous conduction mode at 50 % of the full load torque.

Q3.

A three phase full wave rectifier supplies a resistive capacitive load of 50 Amps from a 220 V. 3 phase 50 Hz supply. Find out the value of the load capacitance such that the load voltage ripple is less than 5 %.

Answers to practice problems 1. Since the load current is ripple free the power consumed by the load will be PL = I

2 0AV

R LOAD

2 V0AV = R LOAD

3 2VL 3 2 × 220 = = 148.55 volts 2π 2π

Now

V0AV =

∴

2 V0AV ⎛ 148.55 ⎞ PL = =⎜ ⎟ ×1 KW = 551.7 watts R LOAD ⎝ 200 ⎠

2

When the inductor is shorted 2 V0RMS PL = R LOAD Now from Equ. (12.2) V0RMS =

1 3 + VL = 151.01 volts 3 4π


2

∴

2 V0RMS ⎛ 151.01 ⎞ PL = =⎜ ⎟ ×1 KW = 570 watts R LOAD ⎝ 200 ⎠

2. To run at rated speed at full load the motor terminal voltage must be 200 volts. 3 2 VL = 200 volts, ∴ VL = 148.1 volts π Where VL is the secondary line voltage. Secondary is star connected. So secondary phase voltage

∴

V0AL =

V2 =

VL = 85.5 volts 3

Primary is delta connected. So primary phase voltage V1 = 220 V V ∴ Required turns ratio = 1 = 1: 0.38865 2 At 50% of the full load torque motor current is 25 Amps ∴ back Emf = 200 – 0.5 × 25 = 187.5 Volts. 187.5 ×1500 = 1607 RPM . ∴ speed at 50% of full load torque = 200 - 0.5×50 At 50% of full load torque the motor operates in the continuous conduction mode, with reference to Fig. 12.2 and equation 12.19. ωt-π/3 ⎡ ⎤ 2VL ⎢ sinφ - tanφ sinθ ⎥ e + sin(ωt φ) π z ⎢ cosφ ⎥ 3tanφ ⎣1- e ⎦ E 187.5 = = 0.9375 Where sinθ = 200 2VL θ = 69.64º = 1.2154 rad.

i0 =

At the junction of continuous and discontinuous conduction

i 0 Min = i 0 ωt = θ = 0 sinφ

∴

1- e

π 3tanφ

e

-

( θ-π/3) tanφ

+ sin(θ - φ) -

sinθ =0 cosφ

( π/3 - θ )

OR

1 sin2φe tanφ 1 1 + sinθ - sin(θ - 2φ) = sinθ π 2 2 2 1- e 3tanφ


( π/3 - θ )

OR

sin2φ

e

tanφ -

π 3tanφ

- sin(θ - 2φ) = sinθ

1- e Solving which φ = 34.65º. ωL ∴ = tanφ = 0.6911 R ∴ ωL = 0.3456 Ω or L = 1.1 mH.

3. Assuming linear ripple V0Max + V0Min 2 = V0Max - V0Min

V0AV = ˆ V 0pp

∴

∴ ∴

ˆ 2 ( V0Max + V0Min ) V = 0pp = 0.05 V0Max + V0Min V0AV 1- V0Min /V0Max = 0.025 1+ V0Min /V0Max V0Min /V0Max = 0.9512 .

V0Max = 2VL = 2 × 220 V = 311 volts From Fig. 12.3, ∴ V0Min = 295.943 Volts ∴ V0AV = 303.47 V. ∴ R = 6.0694 Ω. I0AV = 50 Amps From Fig. 12.3. V0Min occurs at ωt = α ∴ V0Min = 2VLsinα = 295.943 ∴ sin α = 0.9512 or α = 72º But from Equation (12.28) ⎛π ⎞ tanφ ⎜ - α+φ ⎟

⎠ sinα = cosφ e ⎝ 6 1 where tanφ = ωRC from which φ = 3.5º ∴ tanφ = 0.06116 1 ∴ R = 6.0694 Ω ωRC = = 16.35 , tanφ ∴ ωC = 2.6938, ∴ C = 8575 μF.



Lesson 13 Operation and Analysis of the Three Phase Fully Controlled Bridge Converter Version 2 EE IIT, Kharagpur 2


Draw the circuit diagram and waveforms associated with a three phase fully controlled bridge converter.

•

Find out the average, RMS valves and the harmonic spectrum of the output voltage / current waveforms of the converter.

•

Find out the closed form expression of the output current and hence the condition for continuous conduction.

•

Find out the displacement factor, distortion factor and the power factor of the input current as well as its harmonic spectrum.

•

Analyze the operation of higher pulse number converters and dual converter.

•

Design the triggering circuit of the three phase fully controlled bridge converter.


13.1 Introduction The three phase fully controlled bridge converter has been probably the most widely used power electronic converter in the medium to high power applications. Three phase circuits are preferable when large power is involved. The controlled rectifier can provide controllable out put dc voltage in a single unit instead of a three phase autotransformer and a diode bridge rectifier. The controlled rectifier is obtained by replacing the diodes of the uncontrolled rectifier with thyristors. Control over the output dc voltage is obtained by controlling the conduction interval of each thyristor. This method is known as phase control and converters are also called “phase controlled converters”. Since thyristors can block voltage in both directions it is possible to reverse the polarity of the output dc voltage and hence feed power back to the ac supply from the dc side. Under such condition the converter is said to be operating in the “inverting mode”. The thyristors in the converter circuit are commutated with the help of the supply voltage in the rectifying mode of operation and are known as “Line commutated converter”. The same circuit while operating in the inverter mode requires load side counter emf. for commutation and are referred to as the “Load commutated inverter”. In phase controlled rectifiers though the output voltage can be varied continuously the load harmonic voltage increases considerably as the average value goes down. Of course the magnitude of harmonic voltage is lower in three phase converter compared to the single phase circuit. Since the frequency of the harmonic voltage is higher smaller load inductance leads to continuous conduction. Input current wave shape become rectangular and contain 5th and higher order odd harmonics. The displacement angle of the input current increases with firing angle. The frequency of the harmonic voltage and current can be increased by increasing the pulse number of the converter which can be achieved by series and parallel connection of basic 6 pulse converters. The control circuit become considerably complicated and the use of coupling transformer and / or interphase reactors become mandatory. With the introduction of high power IGBTs the three phase bridge converter has all but been replaced by dc link voltage source converters in the medium to moderately high power range. However in very high power application (such as HV dc transmission system, cycloconverter drives, load commutated inverter synchronous motor drives, static scherbius drives etc.) the basic B phase bridge converter block is still used. In this lesson the operating principle and characteristic of this very important converter topology will be discussed in source depth.

13.2 Operating principle of 3 phase fully controlled bridge converter A three phase fully controlled converter is obtained by replacing all the six diodes of an uncontrolled converter by six thyristors as shown in Fig. 13.1 (a)



For any current to flow in the load at least one device from the top group (T1, T3, T5) and one from the bottom group (T2, T4, T6) must conduct. It can be argued as in the case of an uncontrolled converter only one device from these two groups will conduct. Then from symmetry consideration it can be argued that each thyristor conducts for 120° of the input cycle. Now the thyristors are fired in the sequence T1 → T2 → T3 → T4 → T5 → T6 → T1 with 60° interval between each firing. Therefore thyristors on the same phase leg are fired at an interval of 180° and hence can not conduct simultaneously. This leaves only six possible conduction mode for the converter in the continuous conduction mode of operation. These are T1T2, T2T3, T3T4, T4T5, T5T6, T6T1. Each conduction mode is of 60° duration and appears in the sequence mentioned. The conduction table of Fig. 13.1 (b) shows voltage across different devices and the dc output voltage for each conduction interval. The phasor diagram of the line voltages appear in Fig. 13.1 (c). Each of these line voltages can be associated with the firing of a thyristor with the help of the conduction table-1. For example the thyristor T1 is fired at the end of T5T6 conduction interval. During this period the voltage across T1 was vac. Therefore T1 is fired α angle after the positive going zero crossing of vac. Similar observation can be made about other thyristors. The phasor diagram of Fig. 13.1 (c) also confirms that all the thyristors are fired in the correct sequence with 60° interval between each firing. Fig. 13.2 shows the waveforms of different variables (shown in Fig. 13.1 (a)). To arrive at the waveforms it is necessary to draw the conduction diagram which shows the interval of conduction for each thyristor and can be drawn with the help of the phasor diagram of fig. 13.1 (c). If the converter firing angle is α each thyristor is fired “α” angle after the positive going zero crossing of the line voltage with which it’s firing is associated. Once the conduction diagram is drawn all other voltage waveforms can be drawn from the line voltage waveforms and from the conduction table of fig. 13.1 (b). Similarly line currents can be drawn from the output current and the conduction diagram. It is clear from the waveforms that output voltage and current waveforms are periodic over one sixth of the input cycle. Therefore this converter is also called the “six pulse” converter. The input current on the other hand contains only odds harmonics of the input frequency other than the triplex (3rd, 9th etc.) harmonics. The next section will analyze the operation of this converter in more details.


Exercise 13.1 Fill in the blank(s) with the appropriate word(s) i) The three phase fully controlled bridge converter is obtained by replacing six _________ of an uncontrolled converter by six __________. Version 2 EE IIT, Kharagpur 7

ii) The pulse number of a three phase fully controlled bridge converter is _________. iii) In a three phase fully controlled converter each device conducts for an interval of __________ degrees. iv) In a three phase fully controlled converter operating in continuous conduction there are ________ different conduction modes. v) The output voltage of a three phase fully controlled converter operating in the continuous conduction mode consists of segments of the input ac ________ voltage. vi) The peak voltage appearing across any device of a three phase fully controlled converter is equal to the ________ input ac ________ voltage. vii) The input ac current of a three phase fully controlled converter has a ________ step waveform. viii) The input ac current of a three phase fully controlled converter contains only _________ harmonics but no _________ harmonic. ix) A three phase fully controlled converter can also operate in the _________ mode. x) Discontinuous conduction in a three phase fully controlled converter is _________. Answers: (i) diodes, thyristors; (ii) six; (iii) 120; (iv) six; (v) line; (vi) peak, line; (vii) six; (viii) odd, tripler; (ix) inverting; (x) rare.

13.2.1 Analysis of the converter in the rectifier mode The output voltage waveform can be written as α

v0 = V0 +

∑V

AK

K=1,2

cos 6 Kωt +

∑V

BK

sin 6 Kωt

(13.1)

K=1,2

π α+ 3 α+ π3 3 2 π⎞ ⎛ 3 v dωt = V sin ⎜ ωt + ⎟ dωt 0 L ∫ ∫ α π α π 3⎠ ⎝

V0 = =

VAK

α

3 2 VL cosα π

(13.2)

6 α+ π3 = ∫ v0 cos6 Kωt dωt π α 6 α+ π π⎞ ⎛ = ∫ 3 2 VLsin ⎜ ωt + ⎟ cos6 ωt dωt π α 3⎠ ⎝

=

3 2 ⎡ cos(6K +1)α cos(6K -1)α ⎤ VL ⎢ π 6K -1 ⎥⎦ ⎣ 6K +1


6 α+ π3 v 0 sin6 Kωt dωt π ∫α 6 α+ π3 π⎞ ⎛ = ∫ 2 VLsin ⎜ ωt + ⎟ sin6 ωt dωt α π 3⎠ ⎝

VBK =

=

3 2 ⎡ sin(6K +1)α sin(6K -1)α ⎤ VL ⎢ π 6K -1 ⎥⎦ ⎣ 6K +1

(13.4) 1

V0RMS =

3 π ∫α

α+

π 3

⎡ 3 3 ⎤2 v02 dωt = VL ⎢1+ cos2α ⎥ 4π ⎣ ⎦

The input phase current ia is expressed as α ≤ ωt ≤ α +

ia = i0 ia = - i0 ia = i0

ia = 0

π 3

2π 4π ≤ ωt ≤ α + 3 3 5π α+ ≤ ωt ≤ α + 2π 3 otherwise α+

From Fig. 13.2 it can be observed that i0 itself has a ripple at a frequency six times the input frequency. The closed from expression of i0, as will be seen later is some what complicated. However, considerable simplification in the expression of ia can be obtained if i0 is replaced by its average value I0. This approximation will be valid provided the ripple on i0 is small, i.e, the load is highly inductive. The modified input current waveform will then be ia which can be expressed in terms of a fourier series as α I A0 α ˆ i a ≈ ia = + ∑ I An cos nωt + ∑ I Bn sin nωt 2 n=1 n=1

(13.5)

Where 1 α+2π i a dωt = 0 2π ∫α 1 α+2π = ∫ i a cos nωt n≠0 π α 4I nπ nπ = 0 cos sin cos nα nπ 6 2

I A0 = I An

∴

I An = ( -1)

K

2 3I 0 π⎞ ⎛ sin ⎜ Kπ ± ⎟ cos ( 6K ±1) α 2⎠ ( 6K ±1) π ⎝

(13.6)

(13.7)

(13.8)

for n = 6K ±1, K = 0, 1, 2, 3 ....

IAn = 0

otherwise.


1 α+2π i a sin nωt dωt π ∫α 4I nπ nπ = 0 cos sin nα sin nπ 6 2

I Bn =

∴

I Bn = ( -1)

K

(13.9)

2 3I 0 π⎞ ⎛ sin ⎜ Kπ ± ⎟ sin ( 6K ±1) α 2⎠ ( 6K ±1) π ⎝

(13.10)

for n = 6K ±1, K = 0, 1, 2, ....

IBn = 0 ∴

otherwise.

( -1) 2 3I0 sin ⎛ Kπ ± π ⎞ cos ⎡ 6K ±1 ωt - α ⎤ ia = ∑ )( )⎦ ⎜ ⎟ ⎣( 2⎠ ⎝ K =0 ( 6K ±1) π K

α

(13.11)

in particular ia1 = fundamental component of ia =

2 3 I0 cos ( ωt - α ) π

From Fig. 13.2

v an =

(13.12)

2VL cos ωt 3

(13.13)

∴ displacement angle φ = α. ∴ displacement factor = cosα ⎛ 6⎞ I distortion factor = a1 = ⎜ ⎟ Ia ⎝ π ⎠

I0

2 3 I0 = 3 π

(13.15)

∴ Power factor = Displacement factor × Distortion factor =

The closed form expression for i0 in the interval α ≤ ωt ≤ α +

Where

∴

(13.16)

(13.17)

( ωt - α )

2VL π ⎞ E ⎛ sin ⎜ ωt + - φ ⎟ Z 3 ⎠ R ⎝ ωL Z = R 2 + ω2 L2 , tanφ = R R = Zcosφ, E = 2VLsinθ (from Fig. 13.2) -

3 cosα π

π can be found as follows 3

in this interval di π⎞ ⎛ Ri 0 + L 0 + E = v0 = 2VLsin ⎜ ωt + ⎟ dt 3⎠ ⎝ i 0 = I1e

(13.14)

tanφ

+

(13.18)

(13.19)


( ωt - α )

2VL Z Since i0 is periodic over π/3

∴

i 0 = I1e

-

tanφ

+

⎡ ⎛ π ⎞ sinθ ⎤ ⎢sin ⎜ ωt + 3 - φ ⎟ - cosφ ⎥ ⎠ ⎣ ⎝ ⎦

(13.20)

i 0 ωt=α = i 0 ωt =α+ π

(13.21)

3

∴

2VL Z

I1 + = I1e

-

π 3tanφ

⎡ ⎛ π ⎞ sinθ ⎤ ⎢sin ⎜ α + 3 - φ ⎟ - cosφ ⎥ ⎠ ⎣ ⎝ ⎦

+

2VL Z

⎡ ⎛ 2π ⎞ sinθ ⎤ ⎢sin ⎜ α + 3 - φ ⎟ - cosφ ⎥ ⎠ ⎣ ⎝ ⎦

2VL sin ( φ - α ) π Z 1- e 3tanφ

OR

I1 =

(13.22)

∴

(ω t - α ) ⎡ ⎤ 2VL ⎢ sin ( φ - α ) - tanφ π ⎞ sinθ ⎥ ⎛ ω i0 = e + sin t + φ ⎜ ⎟ π Z ⎢ 3 ⎠ cosφ ⎥ ⎝ 3tanφ ⎣ 1- e ⎦

(13.23)

To find out the condition for continuous conduction it is noted that in the limiting case of continuous conduction. π then i0 is minimum at ωt = α. ∴ Condition i 0 min=0 , Now if θ ≤ α + 3 for continuous conduction is i0 ωt=α ≥ 0 . However discontinuous conduction is rare in these conversions and will not be discussed any further.

13.2.2 Analysis of the converter in the inverting mode. In all the analysis presented so far it has been assumed that α < 90°. It follows from equation 13.2 that the output dc voltage will be positive in this case and power will be flowing from the three phase ac side to the dc side. This is the rectifier mode of operation of the converter. However if α is made larger than 90° the direction of power flow through the converter will reverse provided there exists a power source in the dc side of suitable polarity. The converter in that case is said to be operating in the inverter mode. It has been explained in connection with single phase converters that the polarity of EMF source on the dc side [Fig. 13.1(a)] would have to be reversed for inverter mode of operator. Fig. 13.3 shows the circuit connection and wave forms in the inverting mode of operation where the load current has been assumed to be continuous and ripple free.



Analysis of the converter in the inverting mode is similar to its rectifier mode of operation. The same expressions hold for the dc and harmonic compounds in the output voltage and current. The input supply current Fourier series is also identical to Equation 13.8. In particular 3 2 VL cosα π 2 3 i a1 = I0 cos(ωt - α) π V0 =

(13.24) (13.25)


For values of α in the range 90° < α < 180° it is observed from Fig. 13.3(b) that the average dc voltage is negative and the displacement angle φ of the fundamental component of the input ac line current is equal to α > 90°. Therefore, power in the ac side flows from the converter to the source. It is observed form Fig. 13.3(b) that an outgoing thyristor (thyristor T6 in Fig. 13.3(b)) after commutation is impressed with a negative voltage of duration β = π – α. For successful commutation of the outgoing thyristor it is essential that this interval is larger than the turn off time of the thyristor i.e, β ≥ ωtq , tq is the thyristor turn off time

π - α ≥ ωtq or α ≤ π - ωtq .

Therefore

Which imposes an upper limit on the value of α. In practice this upper value of α is further reduced due to commutation overlap.

Exercise 13.2 1. A three phase fully controlled bridge converter operating from a 3 phase 220 V, 50 Hz supply is used to charge a battery bank with nominal voltage of 240 V. The battery bank has an internal resistance of 0.01 Ω and the battery bank voltage varies by ± 10% around its nominal value between fully charged and uncharged condition. Assuming continuous conduction find out. (i) (ii) (iii)

The range of firing angle of the converter. The range of ac input power factor. The range of charging efficiency.

When the battery bank is charged with a constant average charging current of 100 Amps through a 250 mH lossless inductor. Answer: The maximum and minimum battery voltages are, VB Min = 0.9 × VB Nom = 216 volts and VB Max = 1.1 × VB Nom = 264 volts respectively.

Since the average charging current is constant at 100 A. V0 Max = VB Max + 100 × RB = 264 + 100 × 0.01 = 265 volts V0 Min = VB Min + 100 × RB = 216 + 100 × 0.01 = 217 volts. (i)

(ii)

But

V0 Max = 3 2 VL cos α Min π V0 Min = 3 2 VL cos α Max π

∴

α Min = 26.88º

∴

α Max = 43.08º

Input power factor is maximum at minimum α and vice versa


∴ p.f. max = Distortion factor × Displacement factor

Max

= 3 × cos α min = 0.85 π

p.f. Min = 3 × cos α Max = 0.697 π

(iii)

2 Power loss during charging = I0RMs RB

But I

2 0RMs

2 2 VAK + VBK VK = = I + I + I + ........ and I K ≈ 6KωL 6 2KωL 2 0

2 1

2 2

For α = α Min VA1 = 0.439 V,

VB1 = 48.48 V,

I1 = 0.073 Amps

VA2 = 10.76,

VB2 = 20.15 V,

I2 = 0.017 Amps.

∴ ∴

2 J 0RMs ≈ 1002 + (0.073) 2 + (0.017) 2 = 10000.00562 Ploss = 100 watts.

At α Min, ∴

P0 = I0 × VB Max = 26400 watts.

Charging efficiency =

Similarly for α Max, ∴

26400 = 99.6% 26400 + 100

2 I0RMs ≈ I 02

Ploss = 100 watts P0 = I0 × VB Min = 21600 watts.

∴

Charging efficiency =

21600 = 99.54% 21600 + 100

2. A three phase fully controlled converter operates from a 3 phase 230 V, 50 Hz supply through a Y/Δ transformer to supply a 220 V, 600 rpm, 500 A separately excited dc motor. The motor has an armature resistance of 0.02 Ω. What should be the transformer turns ratio such that the converter produces rated motor terminal voltage at 0º firing angle. Assume continuous conduction. The same converter is now used to brake the motor regeneratively in the reverse direction. If the thyristors are to be provided with a minimum turn off time of 100 μs, what is the maximum reverse speed at which rated braking torque can be produced. Answer: From the given question 3 2 V = 220 ∴ VL = 162.9 V π L Where VL is the secondary side line and also the phase voltage since the secondary side is Δ connected.


Primary side phase voltage = 230 V = 132.79 V 3 132.79 ∴ Turns ratio = = 1:1.2267 . 162.9 During regenerative braking in the reverse direction the converter operates in the inverting mode.

tq

Min

= 100μS

∴

β Min = ωtq

Min

= 1.8o

∴ α Max = 180 – β Min = 178.2º ∴ Maximum negative voltage that can be generated by the converter is 3 2 V cos 178.2o = - 219.89 V π L For rated braking torque Ia = 500 A

∴ Eb = Va – Iara = - 229.89 V. At 600 RPM Eb = 220 – 500 × 0.02 = 210 V. ∴ Max reverse speed is 229.89 × 600 = 656.83 RPM . 210

13.3 Higher pulse number converters and dual converter The three phase fully controlled converter is widely used in the medium to moderately high power applications. However in very large power applications (such as HV DC transmission systems) the device ratings become impractically large. Also the relatively low frequency (6th in the dc side, 5th and 7th in the ac side) harmonic voltages and currents produced by this converter become unacceptable. Therefore several such converters are connected in series parallel combination in order to increase the voltage / current rating of the resulting converter. Furthermore if the component converters are controlled properly some lower order harmonics can be eliminated both from the input and output resulting in a higher pulse converter.


Fig. 13.4(a) schematically represents series connection of two six pulse converters where as Fig. 13.4(b) can be considered to be a parallel connection. The inductance in between the converters has been included to limit circulating harmonic current. In both these figures CONV – I and CONV – II have identical construction and are also fired at the same firing angle α. Their input supplies also have same magnitude but displaced in phase by an angle φ. Then one can write ∞ α 3 2 v 01 = VL cosα + ∑ VAK cos 6 Kωt + ∑ VBK sin 6 Kωt (13.26) π K=1 K=1


v02 =

α α 3 2 VL cosα + ∑ VAK cos 6 K ( ωt - φ ) + ∑ VBK sin 6 K ( ωt - φ ) π K=1 K=1

(13.27)

Therefore for Fig 13.4(a) v 0 = v01 + v02 =

6 2 VL cosα + π

(13.28)

α

2∑ cos3Kφ ⎡⎣ VAK cos3K ( 2ωt - φ ) + VBK sin3K ( 2ωt - φ ) ⎤⎦ K=1

Now if cos 3Kφ = 0 for some K then the corresponding harmonic disappear from the fourier series expression of v0. In particular if φ = 30° then cos 3Kφ = 0 for K = 1, 2, 3, 5……. This phase difference can be obtained by the arrangement shown in Fig. 13.4(c). Then

v0 =

α 6 2 VL cosα + 2∑ [ VAm cos 12mωt + VBm sin 12mωt ] π m=1

(13.29)

It can be seen that the frequency of the harmonics present in the output voltage has the form 12ω, 24ω, 36ω ……….. Similarly it can be shown that the input side line current iABC have harmonic frequency of the form 11ω, 13ω, 23ω, 25ω, 35ω, 37ω, …………. Which is the characteristic of a 12 pulse converter. In a similar manner more number of 3 phase 6 pulse converters can be connected in series / parallel and the φ angle can be adjusted to obtain 18 and 24 pulse converters. One of the shortcomings of a three phase fully controlled converter is that although it can produce both positive and negative voltage it can not supply current in both directions. However, some applications such as a four quadrant dc motor drive require this capability from the dc source. This problem is easily mitigated by connecting another three phase fully controlled converter in anti parallel as shown in Fig. 13.5 (a). In this figure converter-I supplies positive load current while converter-II supplies negative load current. In other words converterI operates in the first and fourth quadrant of the output v – i plane whereas converter-II operates in the third and fourth quadrant. Thus the two converters taken together can operate in all four quadrants and is capable of supplying a four quadrant dc motor drive. The combined converter is called the Dual converter.


Obviously since converter-I and converter-II are connected in antiparallel they must produce the same dc voltage. This requires that the firing angles of these two converters be related as α2 = π – α 1

(13.30)


Although Equations 13.30 ensures that the dc voltages produced by these converters are equal the output voltages do not match on an instantaneous basis. Therefore to avoid a direct short circuit between two different supply lines the two converters must never be gated simultaneously. Converter-I receives gate pulses when the load current is positive. Gate pulses to converter-II are blocked at that time. For negative load current converter-II thyristors are fired while converter-I gate pulses are blocked. Thus there is no circulating current flowing through the converters and therefore it is called the non-circulating current type dual converter. It requires precise sensing of the zero crossing of the output current which may pose a problem particularly at light load due to possible discontinuous conduction. To overcome this problem an interphase reactor may be incorporated between the two converters. With the interphase reactor in place both the converters can be gated simultaneously with α2 = π – α1. The resulting converter is called the circulating current type dual converter.

13.4 Gate Drive circuit for three phase fully controlled converter Several schemes exist to generate gate drive pulses for single phase or three phase converters. In many application it is required that the output of the converter be proportional to a control voltage. This can be achieved as follows. In either single or three phase converters V0 ∝ cosα or α = cos-1 V0 K1 To get

V0 ∝ v c

(13.31)

α = cos -1 Vc K

(13.32)

The following circuit can be used to generate “α” according to equation 13.32.


In the circuit of Fig. 13.6(a) a phase shift network is used to obtain a waveform leading vi by 90º. The phasor diagram of the phase shift circuit is shown in Fig. 13.6(b). The output of the phase shift waveform (and its inverse) is compared with vc. The firing pulse is generated at the point when these two waveforms are equal. Obviously at-this instant

vc ∝ Vs cosα

or

α = cos-1 vc Vs

(13.33)

Therefore this method of generation of converter firing pulses is called “inverse cosine” control. The output of the phase shift network is called carrier waveform. Similar technique can be used for three phase converters. However the phase shift network here consists of a three phase signal transformer with special connections as shown in Fig. 13.7.



The signal transformer uses three single phase transformer each of which has two secondary windings. The primary windings are connected in delta while the secondary windings are connected in zigzag. From Fig. 13.1 (c) T2 is fired α angle after the positive going zero crossing of vbc. Therefore, to implement inverse cosine the carrier wave for T2 must lead vbc by 90º. This waveform is obtained from zigzag connection of the winding segments a1a2 and c1c2 as shown in Fig. 13.7(a). The same figure also shows the zigzag connection for other phase. The voltage across each zigzag phase can be used to fire two thyristors belonging to the same phase leg using a circuit similar to Fig. 13.6 (a). The phase shift network will not be required in this case.


Exercise 13.3 1. Fill in the blank(s) with the appropriate word(s) i) Higher pulse number converters can be realized by __________ and _______ connection of six pulse converters. ii) Constituent six pulse converters of a 12 pulse converter have _________ firing angles. iii) The input supply voltages to the converters of a 12 pulse converter have ________ magnitudes and are phase shifted from one another by _________ degrees. iv) The input supply to a 12 pulse converter can be obtained through a _________ connected transformer. v) Dual converters are used for supplying ________ quadrant dc motor drives. vi) In a dual converter if one converter is fired at an angle ‘α’ the other has to be fired at _________. vii) In ___________ current dual converter only one converter conducts at any time. viii) In a circulating current type dual converter an __________ is used between the converters to limit the circulating current. ix) To obtain a linear control relation between the control voltage and the output dc voltage of a converter ___________ control logic is used. x) In a three phase fully controlled converter the carrier waves for firing pulse generation are obtained using three ___________ connected single phase transformers. Answers: (i) Series, parallel; (ii) same, (iii) equal, 30, (iv) star – star – delta; (v) four; (vi) π - α, (vii) non-circulating ; (viii) inductor, (ix) inverse-cosine; (x) delta-zigzag.

2. A 220V, 750 RPM, 200A separately excited dc motor has an armature resistance of 0.05 Ω. The armature is fed from a three phase non circulating current dual converter. If the forward converter operates at a firing angle of 70º i) At what speed will the motor deliver rated torque. ii) What should be the firing angle in the regenerative braking mode when the motor delivers half the rated torque at 600 rpm. Assume continuous conduction. Supply voltage is 400 V. Answer:

i) The output voltage = 3 2 × 400 cos 70o = 184.7 V π Version 2 EE IIT, Kharagpur 24

∴

Eb = Va – Iara = 184.7 – 200 × 0.05 = 174.75 V.

∴

Operating speed =

ii) E b ∴

600RPM

174.75 × 750 = 624 RPM . 220 - 0.05 × 200

= - 600 × 210 = -168V1 Ia = 100A 750 Va = - Eb + Iara = – 173 r.

Va = - 173 = 3 2 400 cos α π

∴

α = 108.67º

3. What will happen if the signal transformers generating the carrier wave have delta – double star connection instead of delta-zigzag connection. Answer: With delta-double star connection of the signal transformers the carrier wave forms will be in phase with the line voltage waveforms. Therefore, without a phase shift network it will not be possible to generate carrier waveforms which are in quadrature with the line voltages. Hence inverse casine control law cannot be implemented.

References 1. “Power Electronics”; P.C. Sen; Tata-McGrawhill publishing company limited; 1995. 2. “Power Electronics, Converters, Applications and Design”, Mohan, Undeland, Robbins; John Willey and Sons Inc; Third Edition, 2003.


Lesson Summary •

A three phase fully controlled converter is realized by replacing the diodes of an uncontrolled converter with thyristors.

•

A three phase fully controlled converter can operate either as a rectifier or as an inverter.

•

The output voltage of a three phase fully controlled converter contains multiple of sixth harmonic of the input frequency in addition to the dc component.

•

The input current of a three phase fully controlled converter contains only odd harmonics other than tripler harmonics.

•

The input current displacement factor of a three phase fully controlled converter is cos α. α being the firing angle.

•

In the continuous conduction mode a three phase fully controlled converter may operate in the inverting mode by increasing α beyond 90º.

•

In the inverting mode the firing angle should be less than 180º for safe commutation of the thyristors.

•

Several units of three phase fully controlled converters can be connected in series parallel to form higher pulse number (12, 18, 24 etc) converters.

•

In higher pulse number converters all component converters are fired at the same firing angle while their input supplies are phase shifted from one another by a predetermined angle.

•

Two three phase fully controlled converter can be connected in anti parallel to form a dual converter which can operate in all four quadrants of the V-I plane.

•

Dual converters can be of circulating and non circulating current type.

•

Fully controlled converters employ “inverse casine control” strategy for generating firing pulses which gives linear relationship between the output voltage and the control voltage. In a three phase fully controlled converter, a three phase delta/zig-zag connected signal transformer is used to generate the required carrier waves for this purpose.


Practice problems and answers 1. A three phase fully controlled converter operates from a 3 phase 230 V, 50 Hz supply and supplies a resistive load of 25 Ω at a firing angle 90º. Find out the power supplied to the load. 2. A three phase fully controlled converter supplies a 220 V 1500 RPM, 50 A separately excited dc motor from a 230 V, 3 phase, 50 Hz supply. The motor holds an overhauling load at 1000 RPM while producing full load torque. The motor has an armature resistance of 0.2 Ω. What should be the firing angle? Assume continuous conduction. 3. What precaution should be taken in the gate drive circuit so that a three phase fully controlled converter can continue to operate even when the load current becomes discontinuous. Answers

1.

The figure above shows the output voltage with α = 90º and a resistive load. Since the load is resistive the load current becomes zero when the voltage becomes zero. Both the voltage and amount remains zero thereafter till the next thyristor is fired. Therefore for 5π ≤ ωt ≤ π 6 Version 2 EE IIT, Kharagpur 27

v0 = Vbc = 2VL sinωt π ≤ ωt ≤ 7π 6 v0 = 0 π ∴ V0 RMS = 3 ∫5π 2VL2 sin 2 ωt dωt π 6 π = VL 3 ∫5π (1 - cos2ωt ) dωt π 6

∴ P0 =

V0

2 RMS

R

π = VL 1 − 3 ∫5π cos2ωt dωt 2 π 6

= 183 Watts = VL 1 − 3 3 2 4π = 67.65 V

2. To hold the overhauling load the motor must operate in the regenerative braking mode. At 1000 RPM Eb = 220 - 50× 0.2 ×1000 = 140 volts 1500 To supply full load torque, the motor armature current = 50 A. ∴ Supply voltage = Va = Eb + Iara = 140 + 50 × 0.2 = 150 V in the reverse direction. ∴ 3 2 VL cosα = - 150V π

∴ α = 118.9º.

3. With reference to the conduction diagram of problem – 1 it can be seen that the load current becomes zero 30º after a new thyristor is fired (for example, T2). Therefore, both the conducting thyristor (T1 and T2 in this case) turns off. However, when T3 is fired the converter will be unable to resume operation from T2T3 mode unless T2 is fired simultaneously. Similar explanation holds for all other thyristor firing. Therefore, to ensure that the converter operates properly even under discontinuous load current condition the final gate pulse for a particular thyristors must be generated by logically “ANDing” the outputs of its own firing circuit with the output of the firing circuit of the thyristor in the commutation sequence as shown in the table next below To generate the gate pulse of : T1 T2 T3 T4 T5 T6 AND the outputs of

: T1 & T2 T2 & T3 T3 & T4 T4 & T5 T5 & T6 T6 & T1




Lesson 14 Operation and Analysis of Three Phase Half Controlled Converter Version 2 EE IIT, Kharagpur 2


Draw the circuit diagram and waveforms of different variables associated with a three phase half controlled converter.

•

Identify the constructional and operational difference between a three phase fully controlled and half controlled converter.

•

Calculate the average and RMS value of the output dc voltage.

•

Calculate the displacement factor, distortion factor and power factor of the input ac line current.

•

Calculate the Fourier series components of the output voltage and input current waveforms.

•

Derive the closed form expression for output dc current and hence identify continuous or discontinuous conduction mode of the converter.


14.1 Introduction Three phase fully controlled converters are very popular in many industrial applications particularly in situations where power regeneration from the dc side is essential. It can handle reasonably high power and has acceptable input and output harmonic distortion. The configuration also lends itself to easy series and parallel connection for increasing voltage and current rating or improvement in harmonic behavior. However, this versatility of a three phase fully controlled converters are obtained at the cost of increased circuit complexity due to the use of six thyristors and their associated control circuit. This complexity can be considerably reduced in applications where power regeneration is not necessary. In that case three thyristors of the top group or the bottom group of a three phase fully controlled converter can be replaced by three diodes. The resulting converter is called a three phase half controlled converter. Replacing three thyristors by three diodes reduces circuit complexity but at the same time prevents negative voltage appearing at the output at any time. Therefore the converter cannot operate in the inverting mode. The three phase half controlled converter has several other advantages over a three phase fully controlled converter. For the same firing angle it has lower input side displacement factor compared to a fully controlled converter. It also extends the range of continuous conduction of the converter. It has one serious disadvantage however. The output voltage is periodic over one third of the input cycle rather than one sixth as is the case with fully controlled converters. This implies both input and output harmonics are of lower frequency and require heavier filtering. For this reason half controlled three phase converters are not as popular as their fully controlled counterpart. Although, from the point of view of construction and circuit complexity the half controlled converter is simpler compared to the fully controlled converter, its analysis is considerably more difficult. In this lesson the operating principle and analysis of a three phase half controlled converter operating in the continuous conduction mode will be presented.

14.2 Operating principle of three phase half controlled converter Fig. 14.1(a) shows the circuit diagram of three phase half controlled converter supplying an R-LE load. In the continuous conduction mode only one thyristor from top group and only one diode from the bottom group conduct at a time. However, unlike fully controlled converter here both devices from the same phase leg can conduct at the same time. Hence, there are nine conducting modes as shown in Fig. 14.1(b).


Now consider the conducting and blocking state of D2. In the blocking state the voltage across D2 is either vac or vbc. Hence, D2 can block only when these voltages are negative. Taking vbc as the reference phasor (i.e., v bc = 2VL sinωt ) D2 will block during 2π/3 ≤ ωt ≤ 2π and will conduct in the interval 0 ≤ ωt ≤ 2π/3 . Similarly it can be shown that D4 and D6 will conduct during 2π/3 ≤ ωt ≤ 4π/3 and 4π/3 ≤ ωt ≤ 2π respectively. Next consider conduction of T1. The firing sequence of the thyristor is T1 → T3 → T5. Therefore before T1 comes into conduction T5 conducts and voltage across T1 is v ac = 2VL sin (ωt + π/3) . If the firing angle of T1 is α then T1 starts conduction at ωt = α - π/3 and conducts upto α + π/3 . Similarly T3 and T5 conducts during α + π/3 ≤ ωt ≤ α + π and α + π ≤ ωt ≤ 2π + α - π/3 . From this discussion the following conduction diagrams can be drawn for continuous conduction mode.


Exercise 14.1 Fill in the blanks(s) with appropriate word(s). i. A three phase half controlled converter has ________________ thyristors and ________________ diodes. ii. A three phase half controlled converter has ________________ conduction modes as compared to ________________ of a fully controlled converter. iii. A three phase half controlled converter can not operate in the ________________ mode. iv. Unlike a three phase fully controlled converter the devices in the ________________ phase leg of a half controlled converter can conduct at a given time. These conduction modes are called ________________ modes. v. In a three phase half controlled converter only ________________ conduction modes appear at the same time. Version 2 EE IIT, Kharagpur 6

vi. ________________ modes appear only when the firing angle of the converter is greater than ________________ degrees. vii. In a three phase half controlled converter the diodes conduct in a manner similar to a ________________ converter where as the thyristors conducts similar to a ________________ converter. viii. The input current of a three phase half controlled converter does not have ________________ cycle symmetry. Answer: (i) three, three; (ii) nine, six; (iii) inverter; (iv) same, free wheeling; (v) six; (vi) free wheeling, 60; (vii) uncontrolled, controlled; (viii) quarter.

14.3 Analysis of three phase half controlled converters Fig. 14.2 (a) and (b) also shows the waveforms of v0 and i0 (for α < π/3 and α > π/3 ) both of which are periodic over one third of the input voltage time period. Therefore examining v0 for the conduction period of any one thyristor (for example T1) will be sufficient to deduce information regarding output voltage. For example the average value of v0 can be found as follows. With T1 conducting there can be three conduction modes namely, T1D6, T1D2 and T1D4. Now

T1 conducts in the interval α - π ≤ ω t ≤ α + π 3 3 D2 conducts in the interval 0 ≤ ωt ≤ 2 π 3 D4 conducts in the interval 2 π ≤ ωt ≤ 4 π 3 3 D6 conducts in the interval 4 π ≤ ωt ≤ 2π 3

∴Conduction interval T1D6 exists only if α ≤ π 3 Conduction interval T1D4 exists only if α > π 3 So for α ≤ π 3 In the interval α - π ≤ ωt ≤ 0 3 v0 = vab = 2VL sin ωt + 2π 3 0 ≤ ωt ≤ α + π 3 v0 = vac = 2VL sin ωt + π 3 π α+ ⎤ 3 2VL ⎡ 0 π⎞ π⎞ ⎛ ⎛ 3 V0 = sin ωt + 2 dωt+ sin ωt + dωt ⎢ ∫α - π ⎜ ⎥ ⎟ ⎜ ⎟ ∫0 2π ⎣ 3 ⎝ 3⎠ 3⎠ ⎝ ⎦

(

(

)

)

(14.1)

(14.2)


= or, For

(

)

(

for

∴

(

)

3 2VL ⎡ cos α + π - cos 2π + cos π - cos α + 2π ⎤ 2π ⎢⎣ 3 3 3 3 ⎥⎦ 3 2 V0 = VL (1 + cosα) 2π In the interval α - π ≤ ωt ≤ 2π α> π, 3 3 3 v0 = vac = 2VL sin ωt + π 3 2π ≤ ωt ≤ α + π 3 3 v0 = 0

)

(14.3) (14.4)

(14.5)

(14.6)

⎤ 3 2VL ⎡ 2π π⎞ ⎛ dωt ⎥ π sin ⎜ ωt + ⎟ ⎢ ∫ 2π ⎣ α - 3 ⎝ 3⎠ ⎦ 3 2 = VL (1 + cosα) 2π

V0 =

RMS value of v0 can be found in a similar manner and is left as an exercise. From the waveforms of Fig. 14.2, v0 is periodic over one third of the input cycle. Therefore one can write α

v 0 = V0 + ∑ [ VAn cos 3nωt + VBn sin 3nωt ] n=1 π α+ 3 π α3 π α+ 3 π α3

(14.8)

VAn =

3 π∫

v0 cos 3nωt dωt

(14.9)

VBn =

3 π∫

v0 sin 3nωt dωt

(14.10)

For α ≤ π From equations 14.1 and 14.2 3 π 0 α+ ⎤ 3⎡ π⎞ π⎞ ⎛ ⎛ VAn = ⎢ 2VL ∫ π sin ⎜ ωt + 2 ⎟ cos3nωtdωt + 2VL ∫ 3 sin ⎜ ωt + ⎟ cos3nωtdωt ⎥ α 0 π⎣ 3⎠ 3⎠ ⎝ ⎝ 3 ⎦ ⎡ 0 ⎧ ⎛ π⎞ π⎞ ⎫⎤ ⎛ ⎢ ∫α - π ⎨sin ⎜ (3n + 1)ωt + 2 ⎟ + sin ⎜ (1 - 3n)ωt + 2 ⎟ dωt ⎬⎥ 3⎠ 3⎠ ⎝ 3 2VL ⎢ 3 ⎩ ⎝ ⎭⎥ = π 2π ⎢ α + 3 ⎧ ⎛ ⎫ ⎥ π⎞ π⎞ ⎛ sin ⎜ (3n + 1)ωt + ⎟ - sin ⎜ (3n -1)ωt - ⎟ dωt ⎬ ⎥ ⎢+ ∫ ⎨ 3⎠ 3⎠ ⎢⎣ 0 ⎩ ⎝ ⎝ ⎭ ⎥⎦


π α0 ⎡ ⎤ 3 cos (3n + 1)ωt + 2π/3 cos {(3n - 1)ωt - 2π/3} { } ⎢ ⎥ + ⎢ 3n + 1 3n - 1 π ⎥ 0 α3 2VL ⎢ 3 ⎥ = ⎢ π⎥ 2π 0 α+ ⎢ cos {(3n + 1)ωt + π/3} cos {(3n - 1)ωt - π/3} 3 ⎥ + ⎢+ ⎥ 3n + 1 3n - 1 π ⎢⎣ ⎥⎦ α+ 0 3

(14.11)

Therefore

⎡1 + cos [ (3n + 1)(α - π/3) + 2π/3] - cos [ (3n + 1)(α + π/3) + π/3] ⎤ ⎥ 3 2VL ⎢ 3n + 1 ⎢ ⎥ VAn = 2π ⎢ cos [ (3n - 1)(α + π/3) - π/3] - cos [ (3n - 1)(α - π/3) - 2π/3] -1 ⎥ ⎢+ ⎥ 3n - 1 ⎣ ⎦ ⎡1 - 2sin [ (3n + 1)α + π/2] sin [ π/6 - (3n + 1) π/3] ⎤ ⎥ 3 2VL ⎢ 3n + 1 ⎢ ⎥ = 2π ⎢ 1 + 2sin [ (3n - 1)α - π/2] sin [ π/6 + (3n - 1) π/3] ⎥ ⎢⎥ 3n - 1 ⎣ ⎦ 3 2VL ⎡1+ 2sin(6n + 1)π/6 cos(3n + 1)α 1- 2sin(6n - 1)π/6 cos(3n - 1)α ⎤ = ⎥⎦ 2π ⎢⎣ 3n + 1 3n - 1

3 2VL ⎡1+ (-1) n cos(3n + 1)α 1+ (-1) n cos(3n - 1)α ⎤ ⎥ 2π ⎢⎣ 3n + 1 3n - 1 ⎦

(14.12)

π α+ ⎤ 3 2VL ⎡ 0 π⎞ π⎞ ⎛ ⎛ 3 sin ωt + 2 sin3nωtdωt + sin ⎜ ωt + ⎟ sin3nωtdωt ⎥ ⎢ ∫α - π ⎜ ⎟ ∫ 0 π ⎣ 3 ⎝ 3⎠ 3⎠ ⎝ ⎦

(14.13)

= Similarly,

VBn =

or,

⎡ 0 ⎧ ⎡ ⎤ π⎤ π ⎤⎫ ⎡ ⎢ ∫α - π ⎨cos ⎢ (3n - 1)ωt - 2 ⎥ - cos ⎢ (3n + 1)ωt + 2 ⎥ ⎬ dωt ⎥ 3⎦ 3 ⎦⎭ ⎣ 3 2VL ⎢ 3 ⎩ ⎣ ⎥ VBn = π ⎥ 2π ⎢ α + 3 ⎧ ⎡ π⎤ π ⎤⎫ ⎡ cos ⎢ (3n - 1)ωt - ⎥ - cos ⎢ (3n + 1)ωt + ⎥ ⎬ dωt ⎥ ⎢+ ∫ ⎨ 0 3⎦ 3 ⎦⎭ ⎣ ⎩ ⎣ ⎣⎢ ⎦⎥ 0 ⎡ sin {(3n - 1)ωt - 2π/3} 0 ⎤ sin {(3n + 1)ωt + 2π/3} ⎢ ⎥ 3n - 1 3n + 1 π π ⎥ ⎢ αα3 2VL ⎢ 3 3 ⎥ = π π 2π ⎢ α+ α+ ⎥ ⎢ + sin {(3n - 1)ωt - π/3} 3 - sin {(3n + 1)ωt + π/3} 3 ⎥ ⎢ ⎥ 3n - 1 3n + 1 0 0 ⎣ ⎦


⎡ sin [ (3n - 1)(α + π/3) - π/3] - sin [ (3n - 1)(α - π/3) - 2π/3] ⎤ ⎢ ⎥ 3 2VL 3n - 1 ⎢ ⎥ = 2π ⎢ sin [ (3n + 1)(α + π/3) + π/3] - sin [ (3n + 1)(α - π/3) + 2π/3] ⎥ ⎢⎥ 3n + 1 ⎣ ⎦ ⎡ cos [ (3n - 1)α - π/2] sin [ π/6 + (3n - 1) π/6] ⎤ ⎥ 3 2VL ⎢ 3n - 1 ⎢ ⎥ = π ⎢ cos [ (3n + 1)α + π/2] sin [ (3n + 1)π/6 - π/6] ⎥ ⎢⎥ 3n + 1 ⎣ ⎦ 3 2VL ⎡ sin(3n + 1)α sin(3n - 1)α ⎤ nπ = + sin ⎢ ⎥ π ⎣ 3n + 1 3n - 1 ⎦ 2 ∴ VBn =

3 2 nπ ⎡ sin(3n + 1)α sin(3n - 1)α ⎤ VL sin ⎢ + π 2 ⎣ 3n + 1 3n - 1 ⎥⎦

(14.14)

Similar analysis can be done for α > π 3 To find out the Fourier series of the input ac line current the load may be replaced by a constant current source having the same value as the average load current. This approximation will be valid provided the load current ripple is relatively small. With this assumption the last waveform of Fig. 14.2(b) can be redrawn as follows.

∴

α - π ≤ ωt ≤ 2π 3 3 α + π ≤ ωt ≤ 4π 3 3 otherwise

ia = I0 ia = - I0 ia = 0


α

i a = ∑ [ I an cos nωt + I bn sin nωt ]

(14.15)

n=1

2π I an = 1 ∫ i a cos nωt dωt π 0 ⎡ 2π = 1 ⎢ ∫ 3 π I 0 cos nωt dωt π ⎣ α- 3

⎤ I0 cos nωt dωt ⎥ ⎦ π 4π ⎤ I0 ⎡ sin nωt 2 3 3 sin nωt ⎢ ⎥ = π ⎢ n α- π n α+ π ⎥ 3 3 ⎣ ⎦ I0 ⎡ 2nπ = sin - sin n α - π + sin n α + π - sin 4nπ ⎤ nπ ⎢⎣ 3 3 3 3 ⎥⎦ 2I = 0 ⎡sin 2nπ + cos nα sin nπ ⎤ nπ ⎢⎣ 3 3 ⎥⎦

∫

4π 3

α+ π 3

( )

or,

Ian =

(

)

2I0 ⎡⎣cos nα - (- 1) n ⎤⎦ sin nπ nπ 3

2π I bn = 1 ∫ i a sin nωt dωt π 0 ⎡ 2π = 1 ⎢ ∫ 3 π I 0 sin nωt dωt π ⎣ α- 3

(14.16)

⎤ I0 sin nωt dωt ⎥ ⎦ α- π 4π ⎤ I ⎡ = 0 ⎢ cos nωt π 3 + cos nωt 3 π ⎥ 2 α + nπ ⎣ 3 3⎦ I = 0 ⎡⎢sin 4nπ - cos 2nπ + cos n α - π - cos n α + π ⎤⎥ nπ ⎣ 3 3 3 3 ⎦ 2I = 0 sin nα sin nπ nπ 3

∫

4π 3

α+ π 3

( )

(

)

(14.17)

For the fundamental component n = 1 3I 0 [ cosωt + cosα cosωt + sinα sinωt ] π 3I0 = [cosωt + cos(ωt - α)] π 2 3I0 = cos α cos ωt - α π 2 2

i a1 =

(

)

(14.18)

∴ Displacement factor = cos α 2 I Distortion factor = a1 = Ia

(14.19) 6 I cos α π 0 2= I0 π - α π

6 cos α 2 π (π - α)

(14.20)


∴ Power factor = Distortion factor × Displacement factor 3 (1 + cosα) 2(π - α) π

6 cos 2 α = 2 π (π - α)

(14.21)

A closed form expression for i0 can be found as follows v0 = vac In the interval 0 < ωt ≤ α + π 3 di π ∴ L 0 + Ri0 + E = vac = 2VL sin ωt + dt 3 ωt 2VL ⎡ ⎤ ∴ i 0 = Ie tanφ + sin ωt + π - φ - sinθ ⎥ ⎢ cosφ ⎦ Z ⎣ 3 Where tanφ = ωL , Z = R 2 + ω 2 L2 and E = 2VL sinθ R At ωt = α + π 3 ( α + π/3) 2VL ⎡ ⎤ i 0 = I1 = Ie tanφ + sin α - φ + 2π - sinθ ⎥ ⎢ cosφ ⎦ Z ⎣ 3

(

(

)

)

(

In the interval α + π ≤ ωt ≤ 2π 3 3

)

(14.22) (14.23) (14.24)

(14.25)

v0 = vbc

di 0 + Ri 0 + E = v bc = 2VL sinωt dt ( ωt - α - π/3) 2VL ⎡ ⎤ ∴ i 0 = I 2 e tanφ + sin ( ωt - φ ) - sinθ ⎥ cosφ ⎦ Z ⎢⎣

∴ L

(14.26) (14.27)

ωt = α + π 3 2VL ⎡ ⎤ i0 = I2 + sin α + π - φ - sinθ ⎥ = I1 ⎢ Z ⎣ 3 cosφ ⎦

At

(

)

(14.28)

( α + π/3)

2VL sin ( α - φ ) Z ( ωt ) ( ωt - α - π/3) 2VL ⎡ sinθ ⎤ tanφ ∴ i 0 = Ie + ⎢sin ( φ - α ) e tanφ + sin ( ωt - φ ) ⎥ Z ⎢ cosφ ⎥ ⎣ ⎦ ∴ I2 = Ie

i0

i0

ωt = 2π 3

ωt =

2π 3

-

tanφ

= Ie

= i0

-

-

2π 3tanφ

ωt = 0

+

2VL Z

= I+

(

)

( α - π/3) ⎡ ⎤ sin φ α e - sinθ ⎥ ⎢ ( ) tanφ - sin φ - 2π 3 cosφ ⎥ ⎢⎣ ⎦ 2VL ⎡ ⎤ sin π - φ - sinθ ⎥ Z ⎢⎣ 3 cosφ ⎦

(

)

(14.29) (14.30) (14.31) (14.32)


( α - π/3) ⎤ 2VL ⎡ ⎢sin ( φ - α ) e tanφ + sinφ ⎥ Z ⎢ ⎥⎦ ⎣ ∴ for 0 < ωt ≤ α + π 3 ( ωt - α - π/3) - ωt ⎡ ⎤ tanφ 2VL ⎢ sinφ e tanφ e π sinθ ⎥ i0 = sin ( φ - α ) + + sin ωt + - φ ⎥ - 2π - 2π cos Z ⎢ 3 φ 1- e 3tanφ 1- e 3tanφ ⎢⎣ ⎥⎦ (14.33)

- 2π ⎞ ⎛ ∴ I ⎜1 - e 3tanφ ⎟ = ⎝ ⎠

(

for

i0 =

)

α + π ≤ ωt ≤ 2π 3 3

α - π/3 - ωt ⎡ ⎧ - ( ωt - α - π/3) tanφ 2VL ⎢ ⎪ e tanφ sin ( φ - α ) ⎨e + - 2π Z ⎢ ⎪ 1- e 3tanφ ⎩ ⎣⎢

- ωt ⎤ ⎫ ⎪ sinφ e tanφ s θ in ⎥ + sin ( ωt - φ ) ⎬+ ⎥ - 2π c φ os ⎪⎭ 1- e 3tanφ ⎦⎥

(14.34)

Exercise 14.2 1. Fill in the blank(s) with the appropriate word(s).

i. In a three phase half controlled converter each thyristor and diode conduct for ________________ degrees. ii. The output voltage waveform of a three phase half controlled converter is periodic over ________________ of the input voltage cycle. iii. The output voltage waveform of a three phase half controlled converter operating with α > π/3 and α ≤ π/3 are ________________ and have ________________ formula for the average voltage. iv. The output voltage and current of a three phase half controlled converter contain ________________ harmonics of the input ac frequency. v. The ac input current of a half controlled three phase converter can be zero for larger than ________________ of the input ac cycle provided the value of α is ________________ than 60°. vi. The input ac current of a three phase half controlled converter contain ________________ harmonics but no ________________ harmonics. vii. For the same output load current and firing angle the three phase half controlled converter has better ________________ factor but poorer ________________ factor compared to a fully controlled converter. Answer: (i) 120°; (ii) one third; (iii) different, same; (iv) triplen; (v) one third, greater; (vi) even, triplen; (vii) displacement, distortion.


2. A 200V, 1450 RPM, 100A separately excited dc machine has an armature resistance of 0.04Ω. The machine is driven by a three phase half controlled converter operating from a three phase 220V, 50Hz supply. The motor operates at the rated speed and rated load torque. Assuming continuous conduction find out (i) the firing angle of the converter; (ii) RMS fundamental component of the input current, (iii) Input current displacement factor and distortion factors. Answer: (i) Under rated operating condition the motor must be supplied with rated voltage. 3 2 Therefore Vo = VL (1+ cosα ) = 200V 2π

Where VL = 230V ∴ α ≈ 70o (ii) Io = 100A From equation (14.18) 6 Ii1 = I o cos α = 63.87 amps 2 π (iii) From equation (14.19) Input displacement factor = cos α = 0.819 2 From equation (14.20) 6 cos α = 0.712 Input distortion factor = 2 π(π − α)

References 1. “Power Electronics”’ P.C. Sen, Tata McGrawhill publishing company limited, 1995. 2. “Power Electronics, Converters, Applications and Design”; Mohan, Undeland, Robins; John Willey and Sons Inc, Third Edition, 2003.


Lesson Summary •

Three phase half controlled converters are obtained by replacing three thyristors of either the top group or the bottom group of fully controlled converters by three diodes.

•

Three phase half controlled converters can not operate in the inverting mode.

•

Three phase half controlled converters have nine operating modes as compared to six of a fully controlled converter.

•

The three free wheeling modes of a half controlled converters appears only when the firing angle is larger than 60º.

•

The output voltage and current waveforms of a three phase half controlled converter consist of a dc component and triplen harmonics of the input voltage frequency.

•

For the same input ac voltage and firing angle a half controlled converter has higher output average dc voltage compared to a fully controlled converter.

•

The input ac line current of a three phase half controlled converter contains harmonics of all (odd and even) order except triplen harmonics.

•

For the same average dc load current and firing angle the half controlled converter has better input current displacement factor but poorer distortion factor compared to a fully controlled converter.

•

The triggering circuit of a three phase half controlled converter is similar to that of a fully controlled converter. However, only three are required.


Practice Problems and Answers 1. If a free wheeling diode is connected across the output terminals of a three phase fully controlled converter will the performance of converter will be similar to a half controlled converter? Justify your answer. 2. A 220V, 1500 rpm, 50A, separately excited dc motor with armature resistance of 0.5Ω if fed from a 3 phase half controlled rectifier. The available ac source is 440V, 50Hz. A star delta connected transformer is used to feed the armature so that the motor terminal voltage equals rated voltage when converter firing angle is zero. (i) Calculate the transformer turns ratio (ii) Firing angle when (a) motor is running at 1200 rpm and rated torque; (b) 1500 rpm and half the rated torque. 3. A battery with a nominal voltage of 200V and internal resistance of 10mΩ has to be charged at a constant current of 20 amps from a 3 phase 220V 50 Hz power supply. Which of the following converters will give better performance with respect to input current displacement factor, distortion factor and power factor? (i) 3 phase fully controlled converter; (ii) 3 phase half controlled converter.


Answers to Practice Problems 1)

2)

Connecting a diode at the output of a three phase fully controlled converter will not make it performs as a half controlled converter. For example i)

When α ≤ π/3 the free wheeling diode will not come into conduction and therefore, the converter will continue to perform like a fully controlled converter which is very different from that of a half controlled converter for this range of α.

ii)

For α > π/3 the output voltage will be clamped to zero for certain part of the input cycle. However, the output voltage will still have “six pulse” characteristics unlike a half controlled converter. Similarly the input current waveform will retain its quarter cycle symmetry which is not the case with a half controlled converter.

For a half controlled converter

3 2 VL (1 + cosα) 2π V0 = 220 V, ∴ VL = 163 V, V0 =

i) at α = 0,

supply voltage = 440 V,

∴ Primary phase voltage = 254 V

∴ Turns ratio = 1 : 0.64. ii)

(a) E b 1500 = 220 - 0.5 × 50 = 195V

12 = 156 V ∴ E b 1200 = 195 × 15 Torque is rated, ∴ Ia = 50 A, V1200 = 156 + 0.5 × 50 = 181 volts ∴ α = 49.87º ∴ 181 = 3 2 × 163(1 + cosα) 2π

3)

(b) V1500 at half rated torque = 195 + 0.5 × 25 = 207.5V ∴ α = 27.7º 207.5 = 3 2 × 163(1 + cosα) 2π The output voltage of the converter should be V0 = 200 + 20 × 10 × 10-3 = 200.2 V (i)

with a fully controlled converter ∴ α = 47.64º 200.2 = 3 2 × 220 cosα π ∴ Displacement factor = cos α = 0.674 Distortion factor = 3 = 0.955 π ∴ Power factor = Displacement factor × Distortion factor = 0.6436 Version 2 EE IIT, Kharagpur 17

(ii)

with a half controlled converter ∴ α = 69.65º 200.2 = 3 2 × 220 (1 + cosα) 2π ∴ Displacement factor = cos α = 0.82 2 6 cos α = 0.8166 Distortion factor = π(π-α) 2 ∴ Power factor = 0.6695 ∴ Displacement factor and power factor of a half controlled converter are better compared to a fully controlled converter while the distortion factor is poorer.



Lesson 15 Effect of Source Inductance on the Performance of AC to DC Converters Version 2 EE IIT, Kharagpur 2


Draw the voltage and current waveforms associated with a converter taking into account the effect of source inductance.

•

Find the average output voltage of the converter as a function of the firing angle and overlap angle.

•

Estimate overlap angles under a given operating condition and hence determine the turn off time available for the thyristors.

•

Draw the dc equivalent circuit of a converter and parameterize it.

•

Find out the voltage stress on the thyristors due to commutation overlap.


15.1 Introduction In the previous lessons the input ac power sources supplying an ac to dc power converter have been assumed to be ideal with no source impedance. Although this assumption simplifies the analysis of the converters, in most practical situations, they are not fully justified. Most ac dc converters are supplied from transformers. The series impedance of the transformer can not always be neglected. Even if no transformer is used, the impedance of the feeder line comes in series with the source. In most cases this impedance is predominantly inductive with negligible resistive component. The presence of source inductance does have significant effect on the performance of the converter. With source inductance present the output voltage of a converter does not remain constant for a given firing angle. Instead it drops gradually with load current. The converter output voltage and input current waveforms also change significantly. In this lesson a quantitative analysis of these effects will be taken up in some detail.

15.2 Single phase inductance

fully

controlled

converter

with

source

Fig. 15.1(a) shows a single phase fully controlled converter with source inductance. For simplicity it has been assumed that the converter operates in the continuous conduction mode. Further, it has been assumed that the load current ripple is negligible and the load can be replaced by a dc current source the magnitude of which equals the average load current. Fig. 15.1(b) shows the corresponding waveforms. It is assumed that the thyristors T3 and T4 were conducting at t = 0. T1 and T2 are fired at ωt = α. If there were no source inductance T3 and T4 would have commutated as soon as T1 and T2 are turned ON. The input current polarity would have changed instantaneously. However, if a source inductance is present the commutation and change of input current polarity can not be instantaneous. Therefore, when T1 and T2 are turned ON T3 T4 does not commutate immediately. Instead, for some interval all four thyristors continue to conduct as shown in Fig. 15.1(b). This interval is called “overlap” interval.


During this period the load current freewheels through the thyristors and the output voltage is clamped to zero. On the other hand, the input current starts changing polarity as the current through T1 and T2 increases and T3 T4 current decreases. At the end of the overlap interval the current through T3 and T4 becomes zero and they commutate, T1 and T2 starts conducting the full load current. The same process repeats during commutation from T1 T2 to T3T4 at ωt = π + α. Version 2 EE IIT, Kharagpur 5

From Fig. 15.1(b) it is clear that, commutation overlap not only reduces average output dc voltage but also reduces the extinction angle γ which may cause commutation failure in the inverting mode of operation if α is very close to 180º. In the following analysis an expression of the overlap angle “μ” will be determined.

From the equivalent circuit of the converter during overlap period L

∴

dii = vi dt

for

α ≤ ωt ≤ α + μ

(15.1)

ii(ωt = α) = - I0

(15.2)

2Vi ii = I cosωt ωL

(15.3)

ii

=I-

ωt = α

2Vi cosα = - I0 ωL

2Vi cosα - I0 ωL

∴

I=

∴

ii =

(15.4) (15.5)

2Vi (cosα - cosωt) - I0 ωL

(15.6)

at ωt = α + μ ii = I0 2Vi (cosα - cos(α + μ)) - I0 ωL

∴

I0 =

∴

cosα - cos(α + μ) =

or

∴

V0 = I π V0 = I π

∫

α+π

∫

α+π

α

α+μ

2ωL I Vi 0

vi dωt

(15.7) (15.8) (15.9)

2vi sinωt dωt

=

2vi [cos(α + μ) − cos(π + α)] π

=

2vi [cosα + cos(α + μ)] π

vi 2vi cosα [ cosα − cos(α + μ)] π π = 2 2 vi cosα - 2 ωL I0 π π

(15.10)

V0 = 2 2


Equation 15.11 can be represented by the following equivalent circuit

The simple equivalent circuit of Fig. 15.3 represents the single phase fully controlled converter with source inductance as a practical dc source as far as its average behaviour is concerned. The open circuit voltage of this practical source equals the average dc output voltage of an ideal converter (without source inductance) operating at a firing angle of α. The voltage drop across the internal resistance “RC” represents the voltage lost due to overlap shown in Fig. 15.1(b) by the hatched portion of the v0 waveform. Therefore, this is called the “Commutation resistance”. Although this resistance accounts for the voltage drop correctly there is no power loss associated with this resistance since the physical process of overlap does not involve any power loss. Therefore this resistance should be used carefully where power calculation is involved.

15.3 Three phase inductance

fully

controlled

converter

with

source

In lesson 13 the three phase fully controlled converter was analyzed with ideal source with no internal impedance. When the source inductance is taken into account, the qualitative effects on the performance of the converter is similar to that in the case of a single phase converter. Fig. 15.4(a) shows such a converter. As in the case of a single phase converter the load is assumed to be highly inductive such that the load can be replaced by a current source.


As in the case of a single phase converter, commutations are not instantaneous due to the presence of source inductances. It takes place over an overlap period of “μ1” instead. During the overlap period three thyristors instead of two conducts. Current in the outgoing thyristor gradually decreases to zero while the incoming thyristor current increases and equals the total load current at the end of the overlap period. If the duration of the overlap period is greater than 60º four thyristors may also conduct clamping the output voltage to zero for sometime. However, this situation is not very common and will not be discussed any further in this lesson. Due to the conduction of two devices during commutation either from the top group or the bottom group the instantaneous output voltage during the overlap period drops (shown by the hatched portion of Fig. 15.4 (b)) resulting in reduced average voltage. The exact amount of this reduction can be calculated as follows. In the time interval α < ωt ≤ α + μ, T6 and T2 from the bottom group and T1 from the top group conducts. The equivalent circuit of the converter during this period is given by the circuit diagram of Fig. 15.5.


Therefore, in the interval α < ωt ≤ α + μ di b di - L c + vc dt dt d v bc = L (i b - ic ) or, dt di b di =- c ib + ic + Io = 0 ∴ dt dt 2L d i b = vbc = 2VL sinωt ∴ dt

(15.12)

vb = L

but

∴ at ωt = α, ∴

(15.15) (15.16)

2VL cosα - I0 2ωL

∴ C= ib =

(15.14)

2VL cosωt 2ωL

ib = C -

ib = - I0

(15.13)

(15.17)

2VL (cosα - cosωt) - I0 2ωL

(15.18)

at ωt = α + μ, ib = 0 ∴

2VL (cosα - cos(α + μ)) = I0 2ωL

Or,

cosα - cos(α + μ) =

(15.19)

2ωL I VL 0

(15.20)

Equation 15.20 holds for μ ≤ 60º. It can be shown that for this condition to be satisfied I0 ≤

(

)

(15.21)

di b = 3 va dt 2

(15.22)

cos α - π 3 2ωL

VL

To calculate the dc voltage For α ≤ ωt ≤ α + μ v0 = va - v b + L

for α + μ ≤ ωt ≤ α + π

v0 = vac

3

∴

⎡ α+μ V0 = 3 ⎢ ∫ 3 va dωt + π⎣ α 2

π 3 α+μ

∫

α+

⎤ vac dωt ⎥ ⎦


(

)

π α+ ⎡ α+μ ⎤ = 3 ⎢∫ vac + 3 va - vac + ∫ 3 vac dωt ⎥ α+μ π⎣ α 2 ⎦ π α+μ ⎛ v ⎡ α+ ⎤ ⎞ = 3 ⎢ ∫ 3 vac dωt + ∫ ⎜ a + vc ⎟ dωt ⎥ α α π⎣ ⎝ 2 ⎠ ⎦ α+μ = 3 2 VL cosα - 3 ∫ v bc dωt π 2π α

or

3 2VL V0 = 3 2 VL cosα π 2π

α+μ

∫α

(15.23)

sinωt dωt

3 2VL = 3 2 VL cosα [cosα - cos(α + μ)] π 2π

(15.24)

Substituting Equation 15.20 into 15.24 V0 = 3 2 VL cosα - 3 ωL I0 π π

(15.25)

Equation 15.25 suggests the same dc equivalent circuit for the three phase converter with source inductance as shown in Fig. 15.3 with VOC = 3 2 VL cosα π

and commutation resistance R C = 3 ωL . π

It should be noted that RC is a “loss less” resistance, since the overlap process does not involve any active power loss. Exercise 15.1 1.

Fill in the blank(s) with appropriate word(s) i.

The internal impedance of an ac source supplying a converter is largely ______________ in nature.

ii.

Due to the presence of source ______________ commutation in a converter is not ______________.

iii.

The period over which the commutation process continues is called the ______________ period.

iv.

Length of the overlap period depends on the valve of the source inductance and load ______________.

v.

In a single phase converter ______________ thyristors conduct during the overlap period.

vi.

In a three phase converter ______________ thryistors conduct during the overlap period provided the overlap angle is less than ______________ degrees.

vii.

The average output voltage of a ac-dc converter ______________ as a result of commutation overlap.


viii.

In the dc equivalent circuit of a converter the input ac source inductor appears as a loss less resistance called the ______________ resistance.

ix.

Commutation overlap decreases the ______________ angle of a converter and may cause commutation failure during ______________ mode of operation.

x.

Commutation overlap introduces ______________ in the supply voltage waveform.

Answer: (i) inductive; (ii) inductance, instantaneous; (iii) overlap; (iv) current ; (v) four; (vi) three, sixty; (vii) decreases; (viii) commutation; (ix) inverter, (x) notches. 2.

A 220V, 1450 RPM, 100A separately excited dc motor has an armature resistance to 0.1Ω. It is supplied from a 3 phase fully controlled converter connected to a 3 phase 50 Hz ac source. The ac source has an inductive reactance of 0.5Ω at 50 Hz. The line voltage is adjusted such that at α = 0; the motor operates at rated speed and torque. The motor is to be braked regeneratively in the reverse direction at rated speed using the converter. What is the maximum braking torque the motor will be able to produce under this condition without causing commutation failure?

Answer: Under rated operating condition, the motor terminal voltage is 220V and it draws 100 Amps current. Therefore from eqn. 15.25. 3 2 3 VL - × .5×100 π π VL = 198 volts 220 =

or

Eb

rated speed

= 220 − 100 × 0.1 = 210V

Under regenerative braking in the reverse direction at rated speed 3 2 ⎛3 ⎞ ×198cos α − ⎜ × 0.5 + 0.1⎟ Io = −210V π ⎝π ⎠ Also from equation 15.20 2 × 0.5 Io cos α − cos ( α + μ ) = 198 At the limiting condition of commutation failure

α + μ ≈ 180o ∴ cos α =

∴

Io −1 198 2

3 3 2 ⎛3 ⎞ × 198 − ⎜ × 0.5 + 0.1⎟ I o = −210 Io − π π ⎝π ⎠ or 0.377 Io = 57.4

∴ Io = 152.24 Amps

∴ Maximum braking torque will be approximately 150% of the rated motor torque. Version 2 EE IIT, Kharagpur 11

References 1. Muhammad H. Rashid; “Power Electronics, Circuits, Devices and Applications” Second Edition, Prentice – Hall of India, New Delhi, 1994. 2. P.C. Sen; “Power Electronics”, Tata McGrawhill publishing company limited, 1995. 3. “Power Electronics, Converters, Applications and Design”; Mohan, Undeland, Robbins; John Willey and Sons Inc, Third Edition, 2003.

Lesson Summary •

Ac power sources supplying an ac-dc converter have internal impedances which are not always negligible.

•

The internal impedance of an ac source is predominantly inductive with negligible resistive component.

•

Due to the presence of the source inductance in the ac line the thyristors in a ac-dc converter can not commutate instantaneously.

•

The period over which the commutation process continuous is called the overlap period.

•

The length of the overlap period increases with increasing source inductance and load current.

•

In a single phase converter all four thyristors conduct during the overlap period.

•

In a three phase converter, three thyristors conduct during the overlap period provided it is less than 60º.

•

The average output voltage of a converter decreases as a result of commutation overlap.

•

The voltage drop due to commutation overlap can be represented as a drop across a commutation resistance the value of which is proportional to the ac line reactance per phase.

•

The commutation resistance is “loss less” since the actual process of overlap does not involve any real power loss.

•

Commutation overlap reduces the margin angle (γ) of a converter and may cause commutation failure.

•

Commutation overlap introduces “notches” in the ac supply voltage waveform which may affect other equipment connect to the same power source.



Lesson 16 Power Factor Improvement, Harmonic Reduction, Filter Version 2 EE IIT, Kharagpur 2

Instructional Objectives Study of the following: •

Schemes for the improvement of power factor in AC-DC converters.

•

Methods for harmonic reduction in the current waveforms of the converters.

•

Types of filters used to obtain ripple free (dc) output voltage and currents, reducing the harmonics.

2.8.1 Introduction After the discussion of various types of ac to dc converters (rectifiers), both single- and threephase, in the lessons (#2.1-2.6) of this module (# 2), the drop in the output voltage due to the commutation overlap in the converter, was presented, the inductance on the source (ac) side being taken into account, in the previous lesson (#2.7). In this (last) lesson (#2.8), three important points – power factor improvement, harmonic reduction, and filters, as applicable to converters, are described. The three schemes for power factor improvement are discussed. Then, the use of various filters to reduce the harmonics in the output voltage and current waveforms, are presented. Lastly, the harmonic reduction techniques are taken up, in brief. In all these cases, the circuit of a single phase full wave half (semi) controlled bridge converter (ac-dc) is used mostly as an example.

Power Factor Improvement For phase-controlled operation in both single phase full wave half and full controlled bridge converters as discussed in this module (#2), the displacement factor (or power factor, which is lagging) decreases, as the average value of output voltage (Vdc) decreases, with the increase in firing angle delay, α. This is also applicable for both three phase half wave and full wave (bridge) converters. The three schemes used for power factor (pf) improvement are: • • •

Extinction angle control Symmetrical angle control Pulse width modulation (PWM) control

Extinction Angle Control The circuit diagram of a single phase full wave half-controlled (semi) force-commutated bridge converter is shown in Fig. 16.1(a). The thyristors, T1 & T2, are replaced by the switches, self-commutated devices, such as power transistor or equivalent. The power transistor is turned on by applying a signal at the base, and turned off by withdrawing the signal at the base. A gate turn-off thyristor (GTO) also may be used, in which case, it may be turned off by applying a short negative pulse to its gate, but is turned on by a short positive pulse, like a thyristor. In extinction angle control, switch, S1 is turned on at ωt = 0 , and then turned off by forced commutation at ωt = ( π − β ) . The switch, S2 is turned on at ωt = π , and then turned off at

ωt = ( 2π − β ) . The output voltage is controlled by varying the extinction angle, β. Fig. 16.1(b) shows the waveforms for input voltage, output voltage, input current, and the current through thyristor switches. The fundamental component of input current leads the input voltage, and the Version 2 EE IIT, Kharagpur 3

displacement factor (and power factor) is leading. This feature may be desirable to simulate a capacitive load, thus compensating the line voltage drops. iT1 + S1 + -

i 0 = Ia

S2

is

v0 iT2 DF

vs D2

L O A D

D1 iDF (a) Circuit


vs

vs = Vmsinωt

Vm

π

0 v0 0 Ia

iT1

0

Ia

ωt

2π

iT2

β π-β

π

π-β

π

0

2π - β

2π

π

2π - β

iDF 0 is

π-β

π

2π - β

ωt

2π

3π - β

ωt Ia ωt

2π

is1

Ia 2π - β 0 - Ia Ia

ωt

π-β

π

2π

3π - β

ωt

io Load current ωt

0

(b) Waveforms for extinction angle control Fig. 16.1 Single-phase forced-commutated semi-converter. The average output voltage is 2 π-β 2 Vdc = 2Vsin ωt d ( ωt ) = ⋅ V (1 + cos β ) ∫ 2π 0 π The value of Vdc is varied from (2 2 / π)V to 0, as β varies from 0 to π . The rms value of output voltage is 1

2 ⎡1 ⎛ 1 ⎡ 2 π-β ⎤ ⎞⎤ Vo = ⎢ ∫ 2V 2 sin 2 ωt d ( ωt ) ⎥ = V ⎢ ⎜ ( π − β ) + sin 2β ⎟ ⎥ 2 ⎣ 2π 0 ⎦ ⎠⎦ ⎣π ⎝ Here also, Vo varies from V to 0.

1

2

This scheme of extinction angle control can also be used for single phase full wave full controlled bridge converter with four switches, instead of two needed in the earlier case. The students are requested-to study this matter form text books, but details are not included here.


Symmetrical Angle Control This control can be applied for the same half-controlled force commutated bridge converter with two switches, S1 and S2 as shown in Fig. 16.1(a). The switch, S1 is turned on at ωt = ( π − β ) 2 and then turned off at ωt = ( π + β ) 2 . The other switch, S2 is turned on at

ωt = ( 3π − β ) 2 and then turned off at ωt = ( 3π + β ) 2 . The output voltage is varied by varying conduction angle, β. The gate signals are generated by comparing half-sine waves with a dc signal as shown in Fig. 16.2(b). The half-sine waves can be obtained using a full wave diode (uncontrolled) bridge converter. The gate signals can also be generated by comparing triangular waves with a dc signal as shown in Fig. 16.2(c). In the second case, the conduction angle varies linearly with the dc signals, but in inverse ratio, i.e., when the dc signal is zero, full conduction (β = π ) takes place, and the dc signal being same as the peak of the triangular reference signal, no conduction ( β = 0 ) takes place. Fig. 16.2(a) shows the waveforms for input voltage, output voltage, input current and the current through the switches. The fundamental component of input current is in phase with input voltage, and the displacement factor is unity (1.0). Therefore, the power factor is improved.


vs vs = Vmsinωt

Vm

π

0

ωt

v0 Vm

β

0 is1 Ia 0 is2 Ia

π /2

0 is Ia

π

2π

π

2π

π

3π /2

ωt

3π

ωt

5π /2

ωt

2π is1

π 0 - Ia i0 Ia

π-β 2

2π

π+β 2

ωt

Load current

0

ωt

(a) v

vr

vc

Ar -Ar π

0 vg 0

S1

2π

3π

ωt

3π

ωt

S1

S2

β π

2π (b)

Fig. 16.2 Symmetrical angle control.


The average output voltage is ⎛2 2 2 ( π+β ) / 2 ⎛ β ⎞⎞ Vdc = ∫ 2V sin ωt d ( ωt ) = ⎜⎜ V sin ⎜ ⎟ ⎟⎟ π ( π−β ) / 2 ⎝ 2 ⎠⎠ ⎝ π

(

)

The value of Vdc varies from 2 2π V to 0 as β varies from π to 0. The rms value of output voltage is 1

2 ⎡ 2 ( π+β ) / 2 2 2 ⎤ ⎡1 ⎤ Vo = ⎢ ∫ 2V sin ( ωt ) d ( ωt ) ⎥ = V ⎢ ( β + sin β ) ⎥ π-β / 2 ( ) ⎣ 2π ⎦ ⎣π ⎦

1

2

Pulse Width Modulation (PWM) Control If the output voltage of single phase half-controlled converter is controlled by delay angle, extinction angle or symmetrical, there is only one pulse per half cycle in the input current of the converter, and as a result, the lowest order harmonic is third. It is difficult to filter out the lower order harmonic current. In Pulse Width Modulation (PWM) control, the converter switches are turned on and off several times during a half cycle, and the output voltage is controlled by varying the width of pulses. The gate signals are generated by comparing a triangular wave with a dc signal as shown in Fig. 16.3c. In this case, all the pulse widths obtained are equal. Fig. 16.3a shows the input voltage, output voltage, and input current. The lowest order harmonic can be eliminated or reduced by selecting the number of pulses per half cycle. However, increasing the number of pulses would also increase the magnitude of higher order harmonics, which could easily be filtered out. The earlier case of symmetrical angle control can be considered as single pulse PWM. For more details of PWM methods used, the students are requested to study the two lessons (#5.4-5.5) in module 5 (DC-AC converter, or inverter).


v

0

π

2π

3π

ωt

π

2π

3π

ωt

2π

3π

ωt

2π

3π

ωt

3π

ωt

v0 δm 0 is1 Ia

αm δm

δm

0

π

is3 Ia 0 is Ia 0 i0 - Ia

π + αm

π δm

π + αm π

αm

2π

Ia

Load current

0

ωt

(a) v vr

Ar -Ac

vc

π

0 vg2

S1

S1 δm

δm α1

S1

ωt

αm

π

(b)


v

vr

vc

Ar -Ac

vg2

S1

S1

π

ωt

π

ωt

S1

δm αm

0

(c) Fig. 16.3 Pulse-width-modulation control. The details of output voltage and current waveforms of the converter are given. The output voltage (i.e., performance parameters) can be obtained in two steps: (i) by considering only one pair of pulses such that, if one pulse starts at ωt = α1 , and ends at ωt = α1 + δ1 , the other pulse starts at ωt = π + α1 , and ends at ωt = ( π + α1 + δ1 ) , and (2) then by combining the effects of all

pairs of pulse. If mth pulse starts at ωt = α m and its width is δm , the average output voltage due to p number of pulses is found as p 2V p ⎡ 2 α m +δm ⎤ Vdc = ∑ ⎢ ∫ 2V sin ωt d ( ωt ) ⎥ = ∑ ⎡cos α m − cos ( α m + δm )⎤⎦ αm π m =1 ⎣ ⎦ m =1 ⎣ π If the load current with an average value of Ia is continuous and has negligible ripple, the instantaneous input current is expressed in a Fourier series as

is ( t ) = Idc +

α

∑ (a

n =1,3,5,...

n

cos nωt + b n sin nωt )

Due to symmetry of the input current waveform, even harmonics are absent, and Idc is zero. The Fourier coefficients are obtained as 1 2π a n = ∫ is ( t ) cos nωt d ( ωt ) π 0 p 1 π+αm +δm ⎡ 1 α m +δm ⎤ I a cos nωt d ( ωt ) − ∫ I a cos nωt d ( ωt ) ⎥ = 0 = ∑⎢ ∫ α π+α m m π ⎦ m =1 ⎣ π 1 2π is ( t ) sin nωt d ( ωt ) π ∫0 p 1 π+α m +δm ⎡ 1 α m +δm ⎤ Ia sin nωt d ( ωt ) − ∫ I a sin nωt d ( ωt ) ⎥ = ∑⎢ ∫ α π+α m m π ⎦ m =1 ⎣ π p 2I = a ∑ ⎡⎣ cos nα m − cos n ( α m + δ m ) ⎤⎦ nπ m =1

bn =


So, the equation for is(t) is written as is ( t ) =

α

∑

n =1,3,...

2 I n sin ( nωt + φn )

where φn = tan −1 ( a n b n ) = 0 , and I n = ( a 2n + b 2n )

1

2

2 = bn

2

Sinusoidal Pulse Width Modulation (SPWM) Control Various types of modifications in PWM techniques have been proposed. One important method is sinusoidal pulse width modulation (SPWM) control, the pulse widths are generated by comparing a triangular reference voltage vr of amplitude Ar and frequency fr, with a carrier half sinusoidal voltage vc of variable amplitude Ac and frequency 2fs. The sinusoidal voltage vc is in phase with the input phase voltage vs and has twice the supply frequency fs. The widths of the pulses (and the output voltage) are varied by changing the amplitude Ar or the modulation index M from 0 to 1. The modulation index, M is Ac/Ar. It may be noted that the width of the pulses obtained are variable. The width are smaller at the centre of the carrier signal (sinusoidal), and increases as one goes to the start and end of the above signal. Fig. 16.4 shows the various waveforms, including the currents through thyristors and the input current and load current (assumed to be continuous). It may be noted that, in the earlier case (multiple PWM control), the pulse widths are uniform (equal). In this type of control, the displacement factor is unity, and the power factor is improved. The lower order harmonics one eliminated or reduced. For example, width four pulses per half cycle, the lowest order harmonic is the fifth, and so on. Different modifications have been suggested to take one such example, as the pulse width one small in the centre as shown in Fig. 16.4, the carrier signal is modified to care of this. The triangular waveforms are kept same, upto some point from the start and end of the cycle, and then the pulse widths can be made uniform. For more on the matter as given earlier, the students can, either study lesson #5.5 (module 5), or text books on various PWM methods applied for inverters (dc-ac converters). So, the power factor is improved with various control methods discussed. For different PWM methods used, the harmonic components of the voltage waveforms are also decreased or eliminated.


Reference signal

v Ar

Carrier signal vr

Ac vc ωt

0 iT1 +Ia 0

αm

iT2

δm

π

2π

3π

2π

3π

ωt

+Ia 0 is

π

- Ia io Ia

ωt

δm

+Ia 0

π + αm

π + αm π + αm + δ m αm

π

2π

3π

ωt

Load current ωt

0 Fig. 16.4 Sinusoidal pulse-width modulation control.

Filters It is known that the output voltage waveform of a single phase full wave diode (uncontrolled) bridge converter (rectifier) fed from f = 50 Hz (fundamental) supply, contains harmonics of 2f = 100 Hz. So, it is necessary to filter out this and other harmonics from the output voltage to obtain dc component only. The harmonic frequency present in the output voltage waveforms of threephase half-wave and full wave (bridge) diode converters, are 150 Hz (3f) and 300 Hz (6f) respectively. The higher the harmonic frequency, it is easier to filter it. For phase-controlled thyristor converters, the harmonic frequency remains same, but magnitudes vary, as the firing angle delay, α is changed. It may also be noted that the harmonics present in the output current waveforms of the converters with resistive (R) load, remain same. . For simple filter, a capacitor (C) is connected in parallel across the output of the diode converters with resistive (R) load. The reactance of the capacitor should be low, such that harmonics currents pass through it. So, the harmonics in the output voltage decrease. The value of the capacitor chosen varies with the predominant harmonic frequency present. Thus, the capacitor of higher value is needed to filter lower harmonic frequency, say 100 Hz, whereas a lower value of C could be chosen for say, three phase converters. The function of the capacitor Version 2 EE IIT, Kharagpur 12

may also be explained in the following way. The voltage across the capacitor changes as per the input voltage, which is the output voltage of the converter, fed to it, and the capacitor voltage tries to stabilize at the overage value of the output voltage, as the capacitor voltage decreases, load resistance being connected across it. Same is the case with the filter used to reduce the harmonic content of the output current waveform for the above converters with resistive (R) load. Instead of a capacitor in parallel, an inductor (L) is connected in series with the load. The reactance of the inductor increases, thus reducing the harmonic component in the current waveform. Here, a smaller value of the inductor is needed to filter higher harmonics, for example a three-phase bridge converter. These are all simple cases, known to those, who have studied the circuit (network) theory. Also, by Faraday’s laws, induced voltage (emf) appears across the inductor, L, when the current through it changes, and the sign of it opposes the cause, thus opposing the changes in current. So, the current is not allowed to change much, as an inductor is placed in series with the load. In actual practice, a combination of L, C & R is needed to get an optimum filter needed to reduce or eliminate the harmonics in both output voltage and current waveforms.

Low Pass (L-C) Filter A passive low pass filter is the ideal choice. But two problems arise; one is the voltage level, the other is the power or current level. All the elements used, L C or R must be properly rated for the voltage or current level as needed. A single stage filter (L-C) is used to reduce the harmonic components in both voltage and current waveforms of a single phase full wave diode bridge converter with resistive (RL) load as shown in Fig. 16.5(a). It may be noted that, for the lowest harmonic frequency of 100 Hz, the value of the inductor needed is high, needing an iron-cored coil. The size also may be large, if the power or current level is high. As stated earlier, such that nth harmonic ripple content passes through the filter capacitor (C), the impedance of the series path must be much greater than that of the capacitance, i.e., 1 2 2 ZL = ( R L ) + ( n ω L ) >> n ωC The condition to be satisfied is 10 ZL = or ZL 10 = 1 ( n ω C ) n ωC and the effect of load is negligible. As shown, the capacitive reactance chosen is total load impedance divided by a factor of 10 The advantages are small ripple factor with just a single stage (L-C) used, with higher dc output voltage. The main advantage is poor voltage regulation, also resulting in higher peak anode current and peak inverse voltage rating.


+ A

iL

D L

D1

1-φ + Supply (50Hz) -

D2 L O A D

G C

is

H D4

RL

D3 -

B (a)

+

A

E RL, L

R C1 B

C2

L O A D

(b)

Fig. 16.5 (a) Low pass (L-C) filter, (b) Two-stage filter

Two Stage Filter A two-stage filter (Fig. 16.5(b)) may be used, instead of a single stage one given earlier. In this case, the first one is only capacitive (C1) to reduce the harmonic content in voltage waveform, followed by second stage (R-C), instead of L-C. The size may be reduced as the size of R is smaller than that of L, as given earlier. This circuit offers satisfactory operation at light loads, but considerably poor voltage regulation due to drop in R, resulting in higher ripple content, at heavy load. If a single capacitor (C1) is used as a single stage one, the ripple factor (RF) is RF = 1 ⎡⎣ 2 ( 4fR L C1 − 1) ⎤⎦ For a chosen ripple factor, the value of C1 may be computed, if the values of rated output voltage and current for the converter are known or given. These filters may also be used at the output of the dc-dc converter circuits described in module 3 (lessons $3.1-3.2). Only a single stage (L-C) filter may be used, as the frequency in the output voltage in thus case is much higher than the harmonic frequency (100 Hz) for the single phase full wave ac-dc converter (rectifier) circuit described here.


Harmonic Reduction The harmonic reduction schemes are presented in brief. The important point to be noted is that, recently due to increasing use of power electronic units, utility or electricity supply agencies (boards), have restricted that the power is drawn by the consumers, so as to decrease the harmonic content in the input current, or make it sinusoidal, and at the same time, improved load power factor is achieved. Two schemes – (a) passive (filter) circuits and (b) Active shaping of input line current, are presented, in brief.

Low pass (L-C) filter circuit on ac side Before going into the aspect, let us take a rebook at the input current drawn in the circuit shown in Fig. 16.5a. Assuming that output (load) current is constant (dc) without any ripple, the ac input (source) current is square wave in nature (Fig. 16.6a), as this current changes sign, when the input voltage changes sign. If a Fourier analysis of the above current is done, there are harmonic components present in it. Just as filters have been used on the output (dc) side, a low pass (L-C) filter (Fig. 16.6b) is used on the input (source) side to reduce the harmonic components in the input current. The inductors used tend both to improve the power factor and also reduce harmonics as given earlier. The overall energy efficiency remains the same, though additional losses occur in the inductors, but conduction losses in the diodes are reduced. iL Ia

0

is Ia

0

π(T/2)

2π(T)

ωt

-Ia Fig. 16.6(a) Output and input currents.


+ iS

L1

+ -

L2

A

G C

H

B Fig. 16.6 (b) Low pass (L-C) filter on source (AC) side

Active Shaping of Input (line) Current By using a power electronic converter for current shaping, as shown in Fig. 16.7a, it is possible to shape the input current drawn by the single phase bridge converter (rectifier) to be sinusoidal and also in phase with the input voltage. The choice of the power electronic converter is based on the following considerations: • No need for electrical isolation between the input (dc) and output (dc) sides • the power flow is always unidirectional from the utility side to the equipment • the cost, power losses and size of the circuit used should be small. Based on the above, a step-up (boost) dc-dc converter as described in next module (#3), lesson 3.1, is used as the current shaping circuit. The basic principle of operation is as follows. At the input side, the current, is, is desired to be sinusoidal, and also in phase with the voltage, vs, as shown in Fig. 16.7b. Therefore, at the full wave bridge converter output, iL and vs have the same waveform as shown in Fig. 16.7c.


Step-up converter iL id + + vs -

Iload

Ld

ic

│vs│

Cd

-

+ vd (Vd > Vˆ s ) -

(a) vs is ωt

0

(b) │vs│ iL 0

ωt (c)

Fig. 16.7 Active harmonic filtering: (a) step-up converter for current shaping; (b) line waveforms; (c) │vs│ and iL.

The control used is constant tolerance-band one. Here, the current. iL, is controlled, such that peak-to-peak ripple Irip in iL remains constant. The reference input, i*L , is made sinusoidal having same (line) frequency. With a pre-selected value of Irip, iL is forced to be in tolerance band (iL + Irip/2) and (iL – Irip/2) by controlling the status of the switch, S. So, the input current, iL, follows the reference input, i*L , which is sinusoidal. As described later (module #3), the switch, S may be a self-commutated switching device, power transistor or MOSFET. For detail, any text book may be used by the student, as only a brief discussion is presented here. In this lesson, last one in this module, three important points – power factor (pf) improvement, harmonic reduction and filters, are presented. Firstly, three methods, viz extinction angle control, symmetrical angle control and pulse width modulation (PWM) control, are described in detail with relevant waveforms. Then, various types of filters (C, L-C & R-C) used for the reduction in harmonic content of output voltage and current waveforms of the ac-dc Version 2 EE IIT, Kharagpur 17

converters, are discussed, with the equations for the value of the filter components needed. Lastly, in brief, harmonic reduction aspect is taken up. In this module of ac-dc converter consisting of eight lessons, all types of single-phase and three-phase converters, with other relevant points, have been thoroughly discussed.


Module 3 DC to DC Converters Version 2 EE IIT, Kharagpur 1

Lesson 17 Types of Basic DC-DC Converters Version 2 EE IIT, Kharagpur 2

Instructional Objectives Study of the following: •

Three basic types of dc-dc converter circuits − buck, boost and buck-boost

•

The expressions for the output voltage in the above circuits, with inductive (R-L) and battery (or back emf = E) load

Introduction In the last module (#2) consisting of eight lessons, the various types of circuits used in both single-phase and three-phase ac-dc converters, were discussed in detail. This includes half-wave and full-wave, and also half-controlled and full-controlled ones. In this lesson − the first one in this module (#3), firstly, three basic types of dc-dc converter circuits − buck, boost and buck-boost, are presented. Then, the expressions for the output voltage in the above circuits, with inductive (R-L) and battery (or back emf = E), i.e., R-L-E, load, are derived, assuming continuous conduction. The different control strategies employed are briefly described. Keywords: DC-DC converter circuits, Thyristor choppers, Buck, boost and buck-boost converters (dc-dc), Step-down (buck) and step-up (boost) choppers, Output voltage and current.

DC-DC Converters There are three basic types of dc-dc converter circuits, termed as buck, boost and buck-boost. In all of these circuits, a power device is used as a switch. This device earlier used was a thyristor, which is turned on by a pulse fed at its gate. In all these circuits, the thyristor is connected in series with load to a dc supply, or a positive (forward) voltage is applied between anode and cathode terminals. The thyristor turns off, when the current decreases below the holding current, or a reverse (negative) voltage is applied between anode and cathode terminals. So, a thyristor is to be force-commutated, for which additional circuit is to be used, where another thyristor is often used. Later, GTO’s came into the market, which can also be turned off by a negative current fed at its gate, unlike thyristors, requiring proper control circuit. The turnon and turn-off times of GTOs are lower than those of thyristors. So, the frequency used in GTObased choppers can be increased, thus reducing the size of filters. Earlier, dc-dc converters were called ‘choppers’, where thyristors or GTOs are used. It may be noted here that buck converter (dc-dc) is called as ‘step-down chopper’, whereas boost converter (dc-dc) is a ‘step-up chopper’. In the case of chopper, no buck-boost type was used. With the advent of bipolar junction transistor (BJT), which is termed as self-commutated device, it is used as a switch, instead of thyristor, in dc-dc converters. This device (NPN transistor) is switched on by a positive current through the base and emitter, and then switched off by withdrawing the above signal. The collector is connected to a positive voltage. Now-adays, MOSFETs are used as a switching device in low voltage and high current applications. It may be noted that, as the turn-on and turn-off time of MOSFETs are lower as compared to other switching devices, the frequency used for the dc-dc converters using it (MOSFET) is high, thus, reducing the size of filters as stated earlier. These converters are now being used for applications, one of the most important being Switched Mode Power Supply (SMPS). Similarly, when application requires high voltage, Insulated Gate Bi-polar Transistors (IGBT) are preferred over Version 2 EE IIT, Kharagpur 3

BJTs, as the turn-on and turn-off times of IGBTs are lower than those of power transistors (BJT), thus the frequency can be increased in the converters using them. So, mostly self-commutated devices of transistor family as described are being increasingly used in dc-dc converters.

Buck Converters (dc-dc) A buck converter (dc-dc) is shown in Fig. 17.1a. Only a switch is shown, for which a device as described earlier belonging to transistor family is used. Also a diode (termed as free wheeling) is used to allow the load current to flow through it, when the switch (i.e., a device) is turned off. The load is inductive (R-L) one. In some cases, a battery (or back emf) is connected in series with the load (inductive). Due to the load inductance, the load current must be allowed a path, which is provided by the diode; otherwise, i.e., in the absence of the above diode, the high induced emf of the inductance, as the load current tends to decrease, may cause damage to the switching device. If the switching device used is a thyristor, this circuit is called as a step-down chopper, as the output voltage is normally lower than the input voltage. Similarly, this dc-dc converter is termed as buck one, due to reason given later. S

+

Switch

L I0

+ Vs

L O A D

V0 DF -

Fig. 17.1(a): Buck converter (dc-dc) v0

Vs V0 TON t T

TOFF

i0

t Fig. 17.1(b): Output voltage and current waveforms The output voltage and current waveforms of the circuit (Fig. 17.1a) are shown in Fig. 17.1b. The output voltage is same as the input voltage, i.e., v0 = Vs , when the switch is ON, during the period, TON ≥ t ≥ 0 . The switch is turned on at t = 0 , and then turned off at t = TON . This is Version 2 EE IIT, Kharagpur 4

called ON period. During the next time interval, T ≥ t ≥ TON , the output voltage is zero, i.e.,

v0 = 0 , as the diode, D F now conducts. The OFF period is TOFF = T − TON , with the time period being T = TON + TOFF . The frequency is f = 1 / T . With T kept as constant, the average value of the output voltage is, T

V0 =

1 1 v0 dt = ∫ T 0 T

TON

∫V 0

s

⎛T ⎞ dt = Vs ⎜ ON ⎟ = k Vs ⎝ T ⎠

The duty ratio is k = (TON / T ) = [TON / (TON + TOFF )] , its range being 1.0 ≥ k ≥ 0.0 . Normally, due to turn-on delay of the device used, the duty ratio (k) is not zero, but has some positive value. Similarly, due to requirement of turn-off time of the device, the duty ratio (k) is less than 1.0. So, the range of duty ratio is reduced. It may be noted that the output voltage is lower than the input voltage. Also, the average output voltage increases, as the duty ratio is increased. So, a variable dc output voltage is obtained from a constant dc input voltage. The load current is assumed to be continuous as shown in Fig. 17.1b. The load current increases in the ON period, as the input voltage appears across the load, and it (load current) decreases in the OFF period, as it flows in the diode, but is positive at the end of the time period, T.

Boost Converters (dc-dc) A boost converter (dc-dc) is shown in Fig. 17.2a. Only a switch is shown, for which a device belonging to transistor family is generally used. Also, a diode is used in series with the load. The load is of the same type as given earlier. The inductance of the load is small. An inductance, L is assumed in series with the input supply. The position of the switch and diode in this circuit may be noted, as compared to their position in the buck converter (Fig. 17.1a). +

Is

D

L

I0

+

S

Vs

L O A D

V0

Switch -

Fig. 17.2(a): Boost converter (dc-dc)

I2 I1

0

TON

T

2T

TOFF Fig. 17.2(b): Waveforms of source current (iS) Version 2 EE IIT, Kharagpur 5

The operation of the circuit is explained. Firstly, the switch, S (i.e., the device) is put ON (or turned ON) during the period, TON ≥ t ≥ 0 , the ON period being TON . The output voltage is zero ( v0 = 0 ), if no battery (back emf) is connected in series with the load, and also as stated earlier, the load inductance is small. The current from the source ( i s ) flows in the inductance L. The value of current increases linearly with time in this interval, with ( d i d t ) being positive. As the current through L increases, the polarity of the induced emf is taken as say, positive, the left hand side of L being +ve. The equation for the circuit is, di d i s Vs = Vs = L s or, dt dt L The switch, S is put OFF during the period, T ≥ t ≥ TON , the OFF period being

TOFF = T − TON . ( T = TON + TOFF ) is the time period. As the current through L decreases, with its direction being in the same direction as shown (same as in the earlier case), the induced emf reverses, the left hand side of L being -ve. So, the induced emf (taken as –ve in the equation given later) is added with the supply voltage, being of the same polarity, thus, keeping the current ( is = i0 ) in the same direction. The current ( is = i0 ) decreases linearly in the time interval, TOFF , as the output voltage is assumed to be nearly constant at v0 ≈ V0 , with ( d i s d t ) being negative, as Vs < V0 , which is derived later. The equation for the circuit is, di d i s (Vs − V0 ) Vs = V0 + L s = or, dt dt L The source current waveform is shown in Fig. 17.2b. As stated earlier, the current varies linearly from I 1 ( I min ) to I 2 ( I max ) during the time interval, TON . So, using the expression for d i s d t during this time interval, I 2 − I 1 = I max − I min = (Vs / L ) TON . Similarly, the current varies linearly from I 2 ( I max ) to I 1 ( I min ) during the time interval, TOFF . So, using the expression for d i s d t during this time interval, I 2 − I1 = I max − I min = [(V0 − Vs ) / L] TOFF . Equating the two equations, (V s / L ) T ON = [(V 0 − V s ) / L ] T OFF , from which the average value of the output voltage is, ⎛ T ⎞ ⎛ T ⎞ ⎛ ⎞ 1 1 ⎞ ⎟⎟ = Vs ⎜⎜ ⎟⎟ = Vs ⎜⎜ ⎟⎟ = Vs ⎛⎜ V0 = Vs ⎜⎜ ⎟ ⎝1− k ⎠ ⎝ TOFF ⎠ ⎝ T − TON ⎠ ⎝ 1 − (TON / T ) ⎠ The time period is T = TON + TOFF , and the duty ratio is, k = (TON / T ) = [TON / (TON + TOFF )] , with its range as 1.0 ≥ k ≥ 0.0 . The ON time interval is TON = k T . As stated in the previous case, the range of k is reduced. This is, because the minimum value is higher than the minimum (0.0), and the maximum value is lower than the maximum (1.0), for reasons given there, which are also valid here. As shown, the source current is assumed to be continuous. The expression for the output voltage can be obtained by using other procedures. In this case, the output voltage is higher than the input voltage, as contrasted with the previous case of buck converter (dc-dc). So, this is called boost converter (dc-dc), when a selfVersion 2 EE IIT, Kharagpur 6

commutated device is used as a switch. Instead, if thyristor is used in its place, this is termed as step-up chopper. The variation (range) of the output voltage can be easily computed.

Buck-Boost Converters (dc-dc) A buck-boost converter (dc-dc) is shown in Fig. 17.3. Only a switch is shown, for which a device belonging to transistor family is generally used. Also, a diode is used in series with the load. The connection of the diode may be noted, as compared with its connection in a boost converter (Fig. 17.2a). The inductor, L is connected in parallel after the switch and before the diode. The load is of the same type as given earlier. A capacitor, C is connected in parallel with the load. The polarity of the output voltage is opposite to that of input voltage here. When the switch, S is put ON, the supply current ( is ) flows through the path, Vs , S and L, during the time interval, TON . The currents through both source and inductor ( i L ) increase and are same, with ( d i L d t ) being positive. The polarity of the induced voltage is same as that of the input voltage. The equation for the circuit is, di d i L Vs = Vs = L L or, dt dt L

+

Is

I0

Switch

S

Vs

-

L

IL

L O A D

V0

-

C

+ Fig. 17.3(a): Buck-boost converter (dc-dc)

IL2 IL1

TON

T

2T

TOFF Fig. 17.3(b): Inductor current (iL) waveform Then, the switch, S is put OFF. The inductor current tends to decrease, with the polarity of the induced emf reversing. ( d i L d t ) is negative now, the polarity of the output voltage, V0 being opposite to that of the input voltage, Vs . The path of the current is through L, parallel combination of load & C, and diode D, during the time interval, TOFF . The output voltage remains nearly constant, as the capacitor is connected across the load. Version 2 EE IIT, Kharagpur 7

The equation for the circuit is, di d i L V0 L L = V0 = or, dt dt L The inductor current waveform is shown in Fig. 17.3b. As stated earlier, the current varies linearly from I L1 to I L 2 during the time interval, TON . Note that I L1 and I L 2 are the minimum and maximum values of the inductor current respectively. So, using the expression for d i L d t during this time interval, I L 2 − I L1 = (Vs / L ) TON . Similarly, the current varies linearly from I L 2 to I L1 during the time interval, TOFF . So, using

the expression for d i L d t during this time interval, I L 2 − I L1 = (V0 / L ) TOFF . Equating the two equations, the output voltage is, ⎛T ⎞ ⎛ T V0 = Vs ⎜⎜ ON ⎟⎟ = Vs ⎜⎜ ON ⎝ TOFF ⎠ ⎝ T − TON The time period is T = TON

(V s

/ L ) T ON = (V 0 / L ) T OFF , from which the average value of

⎞ ⎛ (TON / T ) ⎞ k ⎞ ⎟⎟ = Vs ⎜⎜ ⎟⎟ = Vs ⎛⎜ ⎟ ⎝1− k ⎠ ⎠ ⎝ 1 − (TON / T ) ⎠ + TOFF , and the duty ratio is,

k = (TON / T ) = [TON / (TON + TOFF )] . The ON time interval is TON = k T . It may be observed that, for the range 0 ≥ k > 0.5 , the output voltage is lower than the input voltage, thus, making it a buck converter (dc-dc). For the range 0.5 > k ≥ 1.0 , the output voltage is higher than the input voltage, thus, making it a boost converter (dc-dc). For k = 0.5 , the output voltage is equal to the input voltage. So, this circuit can be termed as a buck-boost converter. Also it may be called as step-up/down chopper. It may be noted that the inductor current is assumed to be continuous. The range of k is somewhat reduced due to the reasons given earlier. The expression for the output voltage can be obtained by using other procedures.

Control Strategies In all cases, it is shown that the average value of the output voltage can be varied. The two types of control strategies (schemes) are employed in all cases. These are: (a) Time-ratio control, and (b) Current limit control.

Time-ratio Control In the time ratio control the value of the duty ratio, k = TON / T is varied. There are two ways, which are constant frequency operation, and variable frequency operation.

Constant Frequency Operation In this control strategy, the ON time, TON is varied, keeping the frequency ( f = 1 / T ), or time period T constant. This is also called as pulse width modulation control (PWM). Two cases with duty ratios, k as (a) 0.25 (25%), and (b) 0.75 (75%) are shown in Fig. 17.4. Hence, the output voltage can be varied by varying ON time, TON .


Load-voltage v0

TON TOFF V0

k = 0.25

t

T

V0 v0 TON

k = 0.75

TOFF

T

t

Fig. 17.4: Pulse-width modulation control (constant frequency)

Variable Frequency Operation In this control strategy, the frequency ( f = 1 / T ), or time period T is varied, keeping either (a) the ON time, TON constant, or (b) the OFF time, TOFF constant. This is also called as frequency modulation control. Two cases with (a) the ON time, TON constant, and (b) the OFF time, TOFF constant, with variable frequency or time period ( T ), are shown in Fig. 17.5. The output voltage can be varied in both cases, with the change in duty ratio, k = TON / T .


v0 TON

k = 0.25 t

v0

TON

k = 0.75

TOFF

t

T (a) Constant TON v0

TOFF

k = 0.25

TON

t

T Load voltage

v0 TOFF

TON

k = 0.75 t

T (b) Constant TOFF Fig. 17.5: Output voltage waveforms for variable frequency system There are major disadvantages in this control strategy. These are:

(a) The frequency has to be varied over a wide range for the control of output voltage in frequency modulation. Filter design for such wide frequency variation is, therefore, quite difficult. (b) For the control of a duty ratio, frequency variation would be wide. As such, there is a possibly of interference with systems using certain frequencies, such as signaling and telephone line, in frequency modulation technique. (c) The large OFF time in frequency modulation technique, may make the load current discontinuous, which is undesirable. Thus, the constant frequency system using PWM is the preferred scheme for dc-dc converters (choppers).


Current Limit Control As can be observed from the current waveforms for the types of dc-dc converters described earlier, the current changes between the maximum and minimum values, if it (current) is continuous. In the current limit control strategy, the switch in dc-dc converter (chopper) is turned ON and OFF, so that the current is maintained between two (upper and lower) limits. When the current exceed upper (maximum) limit, the switch is turned OFF. During OFF period, the current freewheels in say, buck converter (dc-dc) through the diode, D F , and decreases exponentially. When it reaches lower (minimum) limit, the switch is turned ON. This type of control is possible, either with constant frequency, or constant ON time, TON . This is used only, when the load has energy storage elements, i.e. inductance, L. The reference values are load current or load voltage. This is shown in Fig. 17.6. In this case, the current is continuous, varying between I max and I min , which decides the frequency used for switching. The ripple in the load current can be reduced, if the difference between the upper and lower limits is reduced, thereby making it minimum. This in turn increases the frequency, thereby increasing the switching losses.

I max

i0

I min

t v0 TON

TOFF

t

T Fig. 17.6: Current limit control

In this lesson, first one in this module (#3), the three basic circuits − buck, boost and buckboost, of dc-dc converters (choppers) are presented, along with the operation and the derivation of the expressions for the output voltage in each case, assuming continuous conduction. The different strategies employed for their control are discussed. In the next lesson − second one, the expression for the maximum and currents for continuous conduction in buck dc-dc converter will be derived.


Module 3 DC to DC Converters Version 2 EE IIT, Kharagpur 1

Lesson 19 Commutation of Thyristor-Based Circuits Part-I Version 2 EE IIT, Kharagpur 2

This lesson provides the reader the following: (i)

Requirements to be satisfied for the successful turn-off of a SCR

(ii)

The turn-off groups as per the General Electric classification

(iii)

The operation of the turn-off circuits

(iv)

Design of a SCR commutation circuit

A thyristor can be turned ON by applying a positive voltage of about a volt or a current of a few tens of milliamps at the gate-cathode terminals. However, the amplifying gain of this regenerative device being in the order of the 108, the SCR cannot be turned OFF via the gate terminal. It will turn-off only after the anode current is annulled either naturally or using forced commutation techniques. These methods of turn-off do not refer to those cases where the anode current is gradually reduced below Holding Current level manually or through a slow process. Once the SCR is turned ON, it remains ON even after removal of the gate signal, as long as a minimum current, the Holding Current, Ih, is maintained in the main or rectifier circuit.

Fig. 3.1 Turn-off dynamics of the SCR In all practical cases, a negative current flows through the device. This current returns to zero only after the reverse recovery time trr, when the SCR is said to have regained its reverse blocking capability. The device can block a forward voltage only after a further tfr, the forward recovery time has elapsed. Consequently, the SCR must continue to be reverse-biased for a minimum of tfr + trr = tq, the rated turn-off time of the device. The external circuit must therefore reverse bias the SCR for a time toff > tq. Subsequently, the reapplied forward biasing voltage must rise at a dv/dt < dv/dt (reapplied) rated. This dv/dt is less than the static counterpart. General Electric has suggested six classification methods for the turn-off techniques generally adopted for the SCR. Others have chosen different classification rules. SCRs have turn-off times rated between 8 - 50 μsecs. The faster ones are popularly known as 'Inverter grade' and the slower ones as 'Converter grade' SCRs. The latter are available at higher current levels while the faster ones are expectedly costlier.

Classification of forced commutation methods The six distinct classes by which the SCR can be turned off are: Class A Class B Class C Class D

Self commutated by a resonating load Self commutated by an L-C circuit C or L-C switched by another load carrying SCR C or L-C switched by an auxiliary SCR Version 2 EE IIT, Kharagpur 3

Class E An external pulse source for commutation Class F AC line commutation These examples show the classes as choppers. The commutation classes may be used in practice in configurations other than choppers.

Class A, Self commutated by resonating the load

Fig. 3.2 A resonant load commutated SCR and the corresponding waveforms When the SCR is triggered, anode current flows and charges up C with the dot as positive. The L-C-R form a second order under-damped circuit. The current through the SCR builds up and completes a half cycle. The inductor current will then attempt to flow through the SCR in the reverse direction and the SCR will be turned off.

The current may be expressed as I ( s) = V

1 1 + RCs =V LRCs 3 + Ls 2 + Rs s ( Ls + R ) 1 + RCs

The solution of the above equation is of the form ⎤ ω n2 −t RC V⎡ 1 e i (t ) = ⎢1 + sin( wt + φ )⎥ R⎢ ⎥⎦ 1−ξ 2 ξ ⎣ where,

ξ=

1 L , ω n = L , ω = ω n 1 − ξ 2 , φ = tan −1 2 RCω C 2R C

and ⎡ ω2 ⎤ n v(t ) = V ⎢ e −t 2 RC sin(ωt ) + 1⎥ ⎢⎣ 1 − ξ 2 ⎥⎦


The capacitor voltage is at its peak when the SCR turns off and the capacitor discharges into the resistance in an exponential manner. The SCR is reverse-biased till the capacitor voltages returns to the level of the supply voltage V.

Class B, Self commutated by an L-C circuit The Capacitor C charges up in the dot as positive before a gate pulse is applied to the SCR. When SCR is triggered, the resulting current has two components. The constant load current Iload flows through R - L load. This is ensured by the large reactance in series with the load and the freewheeling diode clamping it. A sinusoidal current flows through the resonant L-C circuit to charge-up C with the dot as negative at the end of the half cycle. This current will then reverse and flow through the SCR in opposition to the load current for a small fraction of the negative swing till the total current through the SCR becomes zero. The SCR will turn off when the resonant–circuit (reverse) current is just greater than the load current. The SCR is turned off if the SCR remains reversed biased for tq > toff, and the rate of rise of the reapplied voltage < the rated value.

Fig. 3.3 Class B, L-C turn-off

Problem #1 A Class B turn-off circuit commutates an SCR. The load current is constant at 10 Amps. Dimension the commutating components L and C. The supply voltage is 100VDC.

Soln # 1 The commutating capacitor is charged to the supply voltage = 100 V The peak resonant current is, i peak = V C L Assuming,

i peak ~1.5.I load


= (15 ) 2 = 0.0225 L 100 The SCR commutates when the total current through it reaches zero.This corresponds to 0.73 rads after the zero crossing of the resonant current. The capacitor voltage at that instant is 75 volts. After the SCR turns off, the capacitor is charged linearly by the load current. C

If the SCR is to commutate at twice this load current, for a rated "Inverter grade' SCR turnoff time of 20 μsecs, (2.I load ).t = 75.C

20.20 μF 75 = 15.33 ≈ 15 C=

L=

μF

C = 667 ≈ 700 0.0225

μH

20 = = 1.33 volts/sec rise. dt 15 It can be observed that if the peak of the commutating current is just equal to the load current, the turn-off time would be zero as the capacitor would not be able to impress any negative voltage on the SCR. The reapplied forward voltage has a dV

Class C, C or L-C switched by another load–carrying SCR This configuration has two SCRs. One of them may be the main SCR and the other auxiliary. Both may be load current carrying main SCRs. The configuration may have four SCRs with the load across the capacitor, with the integral converter supplied from a current source. Assume SCR2 is conducting. C then charges up in the polarity shown. When SCR1 is triggered, C is switched across SCR2 via SCR1 and the discharge current of C opposes the flow of load current in SCR2.

Fig. 3.4 Class C turn-off, SCR switched off by another load-carring SCR


Class D, L-C or C switched by an auxiliary SCR Example 1

The circuit shown in Figure 3.3 (Class C) can be converted to Class D if the load current is carried by only one of the SCR’s, the other acting as an auxiliary turn-off SCR. The auxiliary SCR would have a resistor in its anode lead of say ten times the load resistance.

Fig. 3.5 Class D turn-off. Class D commutation by a C (or LC) switched by an Auxiliary SCR. Example 2

SCRA must be triggered first in order to charge the upper terminal of the capacitor as positive. As soon as C is charged to the supply voltage, SCRA will turn off. If there is substantial inductance in the input lines, the capacitor may charge to voltages in excess of the supply voltage. This extra voltage would discharge through the diode-inductor-load circuit. When SCRM is triggered the current flows in two paths: Load current flows through the load and the commutating current flows through C- SCRM -L-D network. The charge on C is reversed and held at that level by the diode D. When SCRA is re-triggered, the voltage across C appears across SCRM via SCRA and SCRM is turned off. If the load carries a constant current as in Fig. 3.4, the capacitor again charges linearly to the dot as positive.

Problem # 2 A Class D turn-off circuit has a commutating capacitor of 10 μF. The load consists of a clamped inductive load such that the load current is reasonably constant at 25 amperes. The 'Inverter grade' SCR has a turn-off time of 12 μsecs. Determine whether the SCR will be satisfactorily commutated. Also dimension the commutating inductor. The supply voltage is 220 VDC.


Soln # 2 The capacitor is initially charged to the supply voltage 220 V at the end of the conduction period of SCRA. When SCRM is triggered, the 25 Amps load current and the L-C ringing current flows through it. Peak current through SCR is i peak = 25 + 220 C

Amps L Selecting L such that ipeak ~ 1.5 . load current, C

25 = 0.0568 2.220 L = 3.1 mH L

=

Assuming that the capacitor charges to 70% of its original charge because of losses in the C- SCRM -L-D network, and it charges linearly when SCRA is again triggered, I load .t q = 10(0.7.220)10 −6 = 1540.10 −6 tq

= 1540 / 25 = 61.6

μ sec s

The SCR can therefore be successfully commutated. The maximum current that can be commutated with the given Capacitor at the 220 V supply voltage is I load = 1540 / 12 = 128 Amps For the 25 Amps load current the capacitor just enough would have a rating of C = I load .t q /(0.7.220) = (25.12) / 154 = 1.95 ≈ 2.0

μF

If the supply voltage is reduced by a factor K, the required capacitor rating increases by the same factor K for the same load current.

Class E – External pulse source for commutation The transformer is designed with sufficient iron and air gap so as not to saturate. It is capable of carrying the load current with a small voltage drop compared with the supply voltage. When SCR1 is triggered, current flows through the load and pulse transformer. To turn SCR1 off a positive pulse is applied to the cathode of the SCR from an external pulse generator via the pulse transformer. The capacitor C is only charged to about 1 volt and for the duration of the turn-off pulse it can be considered to have zero impedance. Thus the pulse from the transformer reverses the voltage across the SCR, and it supplies the reverse recovery current and holds the voltage negative for the required turn-off time.


SCR

LOAD

Fig. 3.6 Class E, External pulse commutation


Class F, AC line commutated If the supply is an alternating voltage, load current will flow during the positive half cycle. With a highly inductive load, the current may remain continuous for some time till the

Fig. 3.7 Class F, natural commutation by supply voltage

energy trapped in the load inductance is dissipated. During the negative half cycle, therefore, the SCR will turn off when the load current becomes zero 'naturally'. The negative polarity of the voltage appearing across the outgoing SCR turns it off if the voltage persists for the rated turnoff period of the device. The duration of the half cycle must be definitely longer than the turnoff time of the SCR. The rectifier in Fig.3.6 is supplied from an single phase AC supply. The commutation process involved here is representative of that in a three phase converter. The converter has an input inductance Ls arising manly out of the leakage reactance of the supply transformer. Initially, SCRs Th1 and Th1' are considered to be conducting. The triggering angle for the converter is around 600. The converter is operating in the continuous conduction mode aided by the highly-inductive load. When the incoming SCRs, Th2 and Th2' are triggered, the current through the incoming devices cannot rise instantaneously to the load current level. A circulating current Isc builds up in the short-circuited path including the supply voltage, Vs-Ls-Th1'- Th2 and Vs- Ls-Th2'-Th1 paths. This current can be described by: I sc =

Vs sin(ωt − 90 0 ) Vs V cos(ωt ) Vs + cos α = s + cos α ωL s ωLs ωLs ωL s

where α the triggering angle and Isc and Vs as shown in Fig. 3.6.

This expression is obtained with the simplifying assumption that the input inductance contains no resistances. When the current rises in the incoming SCRs, which in the outgoing Version 2 EE IIT, Kharagpur 10

ones fall such that the total current remains constant at the load current level. When the current in the incoming ones reach load current level, the turn-off process of the outgoing ones is initiated. The reverse biasing voltage of these SCRs must continue till they reach their forward blocking state. As is evident from the above expression, the overlap period is a function of the triggering angle. It is lowest when α ~ 900. These SCRs being 'Converter grade', they have a larger turn-off time requirement of about 30-50 μsecs. The period when both the devices conduct is known as the 'overlap period'. Since all SCRs are in conduction, the output voltage for this period is zero. If the 'fully-controlled' converter in Fig. 3.7 is used as an inverter with triggering angles > 900, the converter triggering can be delayed till the 'margin angle' which includes the overlap angle and the turn-off time of the SCR - both dependent on the supply voltages.

Rate of rise of forward voltage, dv/dt The junctions of any semiconductor exhibit some unavoidable capacitance. A changing voltage impressed on this junction capacitance results in a current, I = C dv/dt. If this current is sufficiently large a regenerative action may occur causing the SCR to switch to the on state. This regenerative action is similar to that which occurs when gate current is injected. The critical rate of rise of off-state voltage is defined as the maximum value of rate of rise of forward voltage which may cause switching from the off-state to the on-state. Since dv/dt turn-on is non-destructive, this phenomenon creates no problem in applications in which occasional false turn-on does not result in a harmful affect at the load. Heater application is one such case. However, at large currents where dv/dt turn-on is accompanied by partial turnon of the device area a high di/dt occurs which then may be destructive. The majority of inverter applications, however, would result in circuit malfunction due to dv/dt turn-on. One solution to this problem is to reduce the dv/dt imposed by the circuit to a value less than the critical dv/dt of the SCR being used. This is accomplished by the use of a circuit similar to those in Figure 3.8 to suppress excessive rate of rise of anode voltage. Z represents load impedance and circuit impedance. Variations of the basic circuit is also shown where the section of the network shown replaces the SCR and the R-C basic snubber. Since circuit impedances are not usually well defined for a particular application, the values of R and C are often determined by experimental optimization. A technique can be used to simplify snubber circuit design by the use of nomographs which enable the circuit designer to select an optimized R-C snubber for a particular set of circuit operating conditions. Another solution to the dv/dt turn-on problem is to use an SCR with higher dv/dt turn-on problem is to use an SCR with higher dv/dt capability. This can be done by selecting an SCR designed specially for high dv/dt applications, as indicated by the specification sheet. Emitter shorting is a manufacturing technique used to accomplish high dv/dt capability.


Fig. 3.8 dv/dt supression circuits

Questions #1

For a Class D turn-off SCR, the load consists of a resistance only. If the supply voltage and SCR turn-off ratings are as in Problem # 1 calculate the required value of the commutating capacitor.

Ans: (Hints): The capacitor would now charge in an exponential manner. The time it takes to discharge from its reverse charged state once SCRA is triggered is the circuit turn-off time which must be in excess of the rated 12 μsecs. #2

For a Class F converter, will the overlap period rise with the leakage inductance of the converter? What happens to the output voltage?

Ans: Yes. The overlap time is directly related to the commutating inductance. The output voltage decreases. In fact, this inductor limits the maximum output current of the converter. The input current maximum would be as for a shorted network with the leakage inductance only present. #3

Can the output DC voltage be controlled in the above circuits?

Ans: Yes. Most of the above circuits are also called 'forced commutated' DC-DC chopper circuits.



Lesson 2 Constructional Features, Operating Principle, Characteristics and Specification of Power Semiconductor Diode Version 2 EE IIT, Kharagpur 2

Instructional Objective On Completion the student will be able to 1. Draw the spatial distribution of charge density, electric field and electric potential in a step junction p-n diode. 2. Calculate the voltage drop across a forward biased diode for a given forward current and vice-verse. 3. Identify the constructional features that distinguish a power diode from a signal level diode. 4. Differentiate between different reverse voltage ratings found in a Power Diode speciation sheet. 5. Identify the difference between the forward characteristic of a power diode and a signal level diode and explain it. 6. Evaluate the forward current specifications of a diode for a given application. 7. Draw the “Turn On” and “Turn Off” characteristics of a power diode. 8. Define “Forward recovery voltage”, “Reverse recovery current” “Reverse Recovery charge” as applicable to a power diode.


Power Semiconductor Diodes 2.1 Introduction Power semiconductor diode is the “power level” counter part of the “low power signal diodes” with which most of us have some degree of familiarity. These power devices, however, are required to carry up to several KA of current under forward bias condition and block up to several KV under reverse biased condition. These extreme requirements call for important structural changes in a power diode which significantly affect their operating characteristics. These structural modifications are generic in the sense that the same basic modifications are applied to all other low power semiconductor devices (all of which have one or more p-n junctions) to scale up their power capabilities. It is, therefore, important to understand the nature and implication of these modifications in relation to the simplest of the power devices, i.e., a power semiconductor diode.

2.2 Review of Basic p-n Diode Characteristics A p-n junction diode is formed by placing p and n type semiconductor materials in intimate contact on an atomic scale. This may be achieved by diffusing acceptor impurities in to an n type silicon crystal or by the opposite sequence. In an open circuit p-n junction diode, majority carriers from either side will defuse across the junction to the opposite side where they are in minority. These diffusing carriers will leave behind a region of ionized atoms at the immediate vicinity of the metallurgical junction. This region of immobile ionized atoms is called the space charge region. This process continues till the resultant electric field (created by the space charge density) and the potential barrier at the junction builds up to sufficient level to prevent any further migration of carriers. At this point the p-n junction is said to be in thermal equilibrium condition. Variation of the space charge density, the electric field and the potential along the device is shown in Fig 2.1 (a).


(a)

(b)

(c)

Fig 2.1: Space change density the electric field and the electric potential in side a p-n junction under (a) thermal equilibrium condition, (b) reverse biased condition, (c) forward biased condition. When an external voltage is applied with p side move negative then the n side the junction is said to be under reverse bias condition. This reverse bias adds to the height of the potential barrier. The electric field strength at the junction and the width of the space change region (also called “the depletion region” because of the absence of free carriers) also increases. On the other hand, free minority carrier densities (np in the p side and pn in the n side) will be zero at the edge of the depletion region on either side (Fig 2.1 (b)). This gradient in minority carrier density causes a small flux of minority carriers to defuse towards the deletion layer where they are swept immediately by the large electric field into the electrical neutral region of the opposite side. This will constitute a small leakage current across the junction from the n side to the p side. There will also be a contribution to the leakage current by the electron hole pairs generated in the space change layer by the thermal ionization process. These two components of current together is called the “reverse saturation current Is” of the diode. Value of Is is independent of the reverse voltage magnitude (up to a certain level) but extremely sensitive to temperature variation. When the applied reverse voltage exceeds some threshold value (for a given diode) the reverse current increases rapidly. The diode is said to have undergone “reverse break down”. Reverse break down is caused by "impact ionization" as explained below. Electrons accelerated by the large depletion layer electric field due to the applied reverse voltage may attain sufficient knick energy to liberate another electron from the covalent bonds when it strikes a silicon atom. The liberated electron in turn may repeat the process. This cascading effect (avalanche) may produce a large number of free electrons very quickly resulting in a large reverse current. The power dissipated in the device increases manifold and may cause its destruction. Therefore, operation of a diode in the reverse breakdown region must be avoided.


When the diode is forward biased (i.e., p side more positive than n side) the potential barrier is lowered and a very large number of minority carriers are injected to both sides of the junction. The injected minority carriers eventually recombines with the majority carries as they defuse further into the electrically neutral drift region. The excess free carrier density in both p and n side follows exponential decay characteristics. The characteristic decay length is called the "minority carrier diffusion length" Carrier density gradients on either side of the junction are supported by a forward current IF (flowing from p side to n side) which can be expressed as IF = IS ( exp ( qv/kT ) ) -1

(2.1)

Where Is = Reverse saturation current ( Amps) v = Applied forward voltage across the device (volts) q = Change of an electron k = Boltzman’s constant T = Temperature in Kelvin From the foregoing discussion the i-v characteristics of a p-n junction diode can be drawn as shown in Fig 2.2. While drawing this characteristics the ohmic drop in the bulk of the semiconductor body has been neglected.

Fig 2.2: Volt-Ampere ( i-v ) characteristics of a p-n junction diode Exercise 2.1 (1) Fill in the blanks with the appropriate word(s). (i)

The width of the space charge region increases as the applied ______________ voltage increases. (ii) The maximum electric field strength at the center of the depletion layer increases with _______________ in the reverse voltage. (iii) Reverse saturation current in a power diode is extremely sensitive to ___________ variation. Version 2 EE IIT, Kharagpur 6

(iv) Donor atoms are _____________________ carrier providers in the p type and _________________ carrier providers in the n type semiconductor materials. (v) Forward current density in a diode is __________________________ proportional to the life time of carriers. Answer: (i) Reverse, (ii) increase, (iii) temperature, (iv) Minority Majority, (v) inversely (2) A p-n junction diode has a reverse saturation current rating of 50 nA at 32°C. What should be the value of the forward current for a forward voltage drop of 0.5V. Assume VT = KT/q at 32°C = 26 mv. Answer

⎛ V ⎞ I F = I s ⎜ e VT - 1 ⎟ , Is = 5×10-8 A, VT = 26×10-3 V V = 0.5V ⎝ ⎠ ∴ I F = 11.24 Am ps. di (3) For the diode of Problem-2 calculate the dynamic ac resistance ra c = F d v F at 32°C and a forward voltage drop of 0.5V.

Answer:

⎛ VF VT ⎞ iF = Is ⎜ e -1⎟ ∴ ⎝ ⎠

VF Is diF = e dVF VT

VT

N ow I s = 5 × 10 -8 A , V F = 0.5V , VT = 26 ×10

∴

-3

V

at 32o C

V - F dVF V = ra c = T e V T = 2 .3 1 3 m Ω diF Is

2.3 Construction and Characteristics of Power Diodes As mention in the introduction Power Diodes of largest power rating are required to conduct several kilo amps of current in the forward direction with very little power loss while blocking several kilo volts in the reverse direction. Large blocking voltage requires wide depletion layer in order to restrict the maximum electric field strength below the “impact ionization” level. Space charge density in the depletion layer should also be low in order to yield a wide depletion layer for a given maximum Electric fields strength. These two requirements will be satisfied in a lightly doped p-n junction diode of sufficient width to accommodate the required depletion layer. Such a construction, however, will result in a device with high resistively in the forward direction. Consequently, the power loss at the required rated current will be unacceptably high. On the other hand if forward resistance (and hence power loss) is reduced by increasing the doping level, reverse break down voltage will reduce. This apparent contradiction in the requirements of a power diode is resolved by introducing a lightly doped “drift layer” of required


thickness between two heavily doped p and n layers as shown in Fig 2.3(c). Fig 2.3 (a) and (b) shows the circuit symbol and the photograph of a typical power diode respectively.

(b)

Fig. 2.3: Diagram of a power; (a) circuit symbol (b) photograph; (c) schematic cross section. To arrive at the structure shown in Fig 2.3 (c) a lightly doped n- epitaxial layer of specified width (depending on the required break down voltage) and donor atom density (NdD) is grown on a heavily doped n+ substrate (NdK donor atoms.Cm -3) which acts as the cathode. Finally the p-n junction is formed by defusing a heavily doped (NaA acceptor atoms.Cm-3) p+ region into the epitaxial layer. This p type region acts as the anode. Impurity atom densities in the heavily doped cathode (Ndk .Cm -3) and anode (NaA.Cm -3) are approximately of the same order of magnitude (10 19 Cm -3) while that of the epitaxial layer (also called the drift region) is lower by several orders of magnitude (NdD ≈ 10 14 Cm-3). In a low power diode this drift region is absent. The Implication of introducing this drift region in a power diode is explained next.

2.3.1 Power Diode under Reverse Bias Conditions

Back

As in the case of a low power diode the applied reverse voltage is supported by the depletion layer formed at the p+ n- metallurgical junction. Overall neutrality of the space change region dictates that the number of ionized atoms in the p+ region should be same as that in the n- region. However, since NdD VSUS. B

The rating VCBO is the maximum allowable voltage between C & E terminals when the transistor is in cut off with iB < 0 and iC less than a specified value. With iB = 0 the EB junction is still forward biased and there is small injection of minority carriers from the emitter to the CB junction. However, with iB < 0 base emitter junction is reverse biased and there is no supply of minority carriers to the CB junction from the emitter. Thus avalanche B

B

B


break down of this junction occurs at a relatively higher voltage making the rating VCBO largest of the three. Therefore, in general for a power transistor.

VCBO > VCEO > VSUS In an inductive switching circuit using snubber the collector voltage falls considerably before iC builds up to any significant level. This can be utilized to increase the usable steady state blocking voltage of the transistor up to VCEO. Since VCE will go below VSUS before iC can build up to the level where the rating VSUS becomes applicable. Similarly during turn off, the overshoot in the VCE voltage can be accommodated in the difference between VCBO and VCEO. Since during turn off iB < 0 and the voltage. overshoot occurs with iC = 0 the applicable voltage limit will be VCBO and not VCEO. However, precaution must be taken such that the voltage over shoot decays before iB becomes equal to zero. B

B

However, if a snubber circuit is not used the applicable voltage limit will always be VSUS since in this case VCE does not fall till iC rises to its full value during turn ON. Similarly during turn off iC does not fall till VCE rises to steady state blocking voltage level. log iC

ICM

BP

Pulsed

CP CD

O

DC

BD

AD AP

log vCE

7. The main difference between the DC and pulsed FBOSA is in the boundary corresponding to maximum power dissipation and second break down. With only DC FBSOA the switching trajectory has to be restricted to something similar to AD BD CD. However, with pulsed FBSOA applicable limits of power dissipation and second break down increases considerably. Both these limits require simultaneous existence of nonzero VCE & iC which for a power transistor occurs only during switching. Therefore, the increases FBSOA can be utilized and the switching trajectory improved to AP BP CP provided total switching time is less than the pulse period for which the increased FBSOA is applicable.


In addition pulsed FBSOA s are usually specified for a very low duty ratio. This condition can be easily satisfied provided total turn on and turn off times of the transistor expressed as a percentage of total “ON” and “OFF” periods of the transistor is less than this duty ratio since during ON or OFF period the transistor remain well within DC FBSOA. In practice this condition is satisfied by specifying a minimum ON and OFF period of the transistor.



Lesson 4 Thyristors and Triacs Version 2 EE IIT, Kharagpur 2

Instructional objects On completion the student will be able to •

Explain the operating principle of a thyristor in terms of the “two transistor analogy”.

•

Draw and explain the i-v characteristics of a thyristor.

•

Draw and explain the gate characteristics of a thyristor.

•

Interpret data sheet rating of a thyristor.

•

Draw and explain the switching characteristics of a thyristor.

•

Explain the operating principle of a Triac.


4.1 Introduction Although the large semiconductor diode was a predecessor to thyristors, the modern power electronics area truly began with advent of thyristors. One of the first developments was the publication of the P-N-P-N transistor switch concept in 1956 by J.L. Moll and others at Bell Laboratories, probably for use in Bell’s Signal application. However, engineers at General Electric quickly recognized its significance to power conversion and control and within nine months announced the first commercial Silicon Controlled Rectifier in 1957. This had a continuous current carrying capacity of 25A and a blocking voltage of 300V. Thyristors (also known as the Silicon Controlled Rectifiers or SCRs) have come a long way from this modest beginning and now high power light triggered thyristors with blocking voltage in excess of 6kv and continuous current rating in excess of 4kA are available. They have reigned supreme for two entire decades in the history of power electronics. Along the way a large number of other devices with broad similarity with the basic thyristor (invented originally as a phase control type device) have been developed. They include, inverter grade fast thyristor, Silicon Controlled Switch (SCS), light activated SCR (LASCR), Asymmetrical Thyristor (ASCR) Reverse Conducting Thyristor (RCT), Diac, Triac and the Gate turn off thyristor (GTO). From the construction and operational point of view a thyristor is a four layer, three terminal, minority carrier semi-controlled device. It can be turned on by a current signal but can not be turned off without interrupting the main current. It can block voltage in both directions but can conduct current only in one direction. During conduction it offers very low forward voltage drop due to an internal latch-up mechanism. Thyristors have longer switching times (measured in tens of μs) compared to a BJT. This, coupled with the fact that a thyristor can not be turned off using a control input, have all but eliminated thyristors in high frequency switching applications involving a DC input (i.e, choppers, inverters). However in power frequency ac applications where the current naturally goes through zero, thyristor remain popular due to its low conduction loss its reverse voltage blocking capability and very low control power requirement. In fact, in very high power (in excess of 50 MW) AC – DC (phase controlled converters) or AC – AC (cyclo-converters) converters, thyristors still remain the device of choice.

4.2 Constructional Features of a Thyristor Fig 4.1 shows the circuit symbol, schematic construction and the photograph of a typical thyristor.


A A

p np

G

(a)

n+

n+

K G

K

(c)

(b) Fig. 4.1: Constructional features of a thysistor (a) Circuit Symbol, (b) Schematic Construction, (c) Photograph As shown in Fig 4.1 (b) the primary crystal is of lightly doped n- type on either side of which two p type layers with doping levels higher by two orders of magnitude are grown. As in the case of power diodes and transistors depletion layer spreads mainly into the lightly doped nregion. The thickness of this layer is therefore determined by the required blocking voltage of the device. However, due to conductivity modulation by carriers from the heavily doped p regions on both side during ON condition the “ON state” voltage drop is less. The outer n+ layers are formed with doping levels higher then both the p type layers. The top p layer acls as the “Anode” terminal while the bottom n+ layers acts as the “Cathode”. The “Gate” terminal connections are made to the bottom p layer. As it will be shown later, that for better switching performance it is required to maximize the peripheral contact area of the gate and the cathode regions. Therefore, the cathode regions are finely distributed between gate contacts of the p type layer. An “Involute” structure for both the gate and the cathode regions is a preferred design structure.

4.3 Basic operating principle of a thyristor The underlying operating principle of a thyristor is best understood in terms of the “two transistor analogy” as explained below.


A

A IA

A

p

Q1 (α1)

p

J1

iC2

-

-

iC1

n

n

J2

p n+

n+

G

J3

n-

p p

G

G

J2 J3

n+

IG

(α2) Q2 IK K

K K (a)

(b)

(c)

Fig. 4.2: Two transistor analogy of a thyristor construction. (a) Schematic Construction, (b) Schematic division in component transistor (c) Equivalent circuit in terms of two transistors. a) Schematic construction, b) Schematic division in component transistor c) Equivalent circuit in terms of two transistors. Let us consider the behavior of this p n p n device with forward voltage applied, i.e anode positive with respect to the cathode and the gate terminal open. With this voltage polarity J1 & J3 are forward biased while J2 reverse biased. Under this condition.

ic1 = ∝1 I A + I co1 ic 2 = ∝ 2 I K + I co2

( 4.1) ( 4.2 )

Where ∝1 & ∝2 are current gains of Q1 & Q2 respectively while Ico1 & Ico2 are reverse saturation currents of the CB junctions of Q1 & Q2 respectively. Now from Fig 4.2 (c). i c1 + i c2 = I A

& IA = IK Combining Eq 4.1 & 4.4 IA =

( 4.3) ( 4.4 ) (∵ I G = 0 )

I co1 + I co2 I co = 1- ( ∝1 + ∝ 2 ) 1- ( ∝1 + ∝ 2 )

( 4.5 ) Version 2 EE IIT, Kharagpur 6

Where I co I co1 + I co2 is the total reverse leakage current of J2 Now as long as VAK is small Ico is very low and both ∝1 & ∝2 are much lower than unity. Therefore, total anode current IA is only slightly greater than Ico. However, as VAK is increased up to the avalanche break down voltage of J2, Ico starts increasing rapidly due to avalanche multiplication process. As Ico increases both ∝1 & ∝2 increase and ∝1 + ∝2 approaches unity. Under this condition large anode current starts flowing, restricted only by the external load resistance. However, voltage drop in the external resistance causes a collapse of voltage across the thyristor. The CB junctions of both Q1 & Q2 become forward biased and the total voltage drop across the device settles down to approximately equivalent to a diode drop. The thyristor is said to be in “ON” state. Just after turn ON if Ia is larger than a specified current called the Latching Current IL, ∝1 and ∝2 remain high enough to keep the thyristor in ON state. The only way the thyristor can be turned OFF is by bringing IA below a specified current called the holding current (IH) where upon ∝1 & ∝2 starts reducing. The thyristor can regain forward blocking capacity once excess stored charge at J2 is removed by application of a reverse voltage across A & K (ie, K positive with respect A). It is possible to turn ON a thyristor by application of a positive gate current (flowing from gate to cathode) without increasing the forward voltage across the device up to the forward break-over level. With a positive gate current equation 4.4 can be written as

IK = IA + IG

( 4.6 )

Combining with Eqns. 4.1 to 4.3 I A =

∝ 2 I G + I co 1- ( ∝1 + ∝ 2 )

( 4.7 )

Obviously with sufficiently large IG the thyristor can be turned on for any value of Ico (and hence VAK). This is called gate assisted turn on of a Thyristor. This is the usual method by which a thyristor is turned ON. When a reverse voltage is applied across a thyristor (i.e, cathode positive with respect to anose.) junctions J1 and J3 are reverse biased while J2 is forward biased. Of these, the junction J3 has a very low reverse break down voltage since both the n+ and p regions on either side of this junction are heavily doped. Therefore, the applied reverse voltage is almost entirely supported by junction J1. The maximum value of the reverse voltage is restricted by a) The maximum field strength at junction J1 (avalanche break down) b) Punch through of the lightly doped n- layer. Since the p layers on either side of the n- region have almost equal doping levels the avalanche break down voltage of J1 & J2 are almost same. Therefore, the forward and the reverse break down voltage of a thyristor are almost equal.Up to the break down voltage of J1 the reverse current of the thyristor remains practically constant and increases sharply after this voltage. Thus, the reverse characteristics of a thyristor is similar to that of a single diode. Version 2 EE IIT, Kharagpur 7

If a positive gate current is applied during reverse bias condition, the junction J3 becomes forward biased. In fact, the transistors Q1 & Q2 now work in the reverse direction with the roles of their respective emitters and collectors interchanged. However, the reverse ∝1 & ∝2 being significantly smaller than their forward counterparts latching of the thyristor does not occur. However, reverse leakage current of the thyristor increases considerably increasing the OFF state power loss of the device. If a forward voltage is suddenly applied across a reverse biased thyristor, there will be considerable redistribution of charges across all three junctions. The resulting current can become large enough to satisfy the condition ∝1 + ∝2 = 1 and consequently turn on the thyristor. This is called dv turn on of a thyristor and should be avoided. dt Exercise 4.1 1)

Fill in the blank(s) with the appropriate word(s) i. A thyristor is a ________________ carrier semi controlled device.

ii. A thyristor can conduct current in ________________ direction and block voltage in ________________ direction. iii. A thyristor can be turned ON by applying a forward voltage greater than forward ________________ voltage or by injecting a positive ________________ current pulse under forward bias condition. iv. To turn OFF a thyristor the anode current must be brought below ________________ current and a reverse voltage must be applied for a time larger than ________________ time of the device. v. A thyristor may turn ON due to large forward ________________. Answers: (i) minority; (ii) one, both; (iii) break over, gate; (iv) holding, turn off; (v) dv dt 2. Do you expect a thyristor to turn ON if a positive gate pulse is applied under reverse bias condition (i. e cathode positive with respect to anode)? Answer: The two transistor analogy of thyristor shown in Fig 4.2 (c) indicates that when a reverse voltage is applied across the device the roles of the emitters and collectors of the constituent transistors will reverse. With a positive gate pulse applied it may appear that the device should turn ON as in the forward direction. However, the constituent transistors have very low current gain in the reverse direction. Therefore no reasonable value of the gate current will satisfy the turn ON condition (i.e.∝1 + ∝2 = 1). Hence the device will not turn ON.


4.4 Steady State Characteristics of a Thyristor 4.4.1 Static output i-v characteristics of a thyristor IA

+

A

VAK

VBRF

-

IA

K ig

Ig

VBRR Is

IH

VBRF

IL

ig1 ig2 ig3 ig4

VAK VH

ig4 > ig3 > ig2 > ig1 > ig = 0

ig4 > ig3 > ig2 > ig1 > ig = 0

Fig. 4.3: Static output characteristics of a Thyristor The circuit symbol in the left hand side inset defines the polarity conventions of the variables used in this figure. With ig = 0, VAK has to increase up to forward break over voltage VBRF before significant anode current starts flowing. However, at VBRF forward break over takes place and the voltage across the thyristor drops to VH (holding voltage). Beyond this point voltage across the thyristor (VAK) remains almost constant at VH (1-1.5v) while the anode current is determined by the external load. The magnitude of gate current has a very strong effect on the value of the break over voltage as shown in the figure. The right hand side figure in the inset shows a typical plot of the forward break over voltage (VBRF) as a function of the gate current (Ig) After “Turn ON” the thyristor is no more affected by the gate current. Hence, any current pulse (of required magnitude) which is longer than the minimum needed for “Turn ON” is sufficient to effect control. The minimum gate pulse width is decided by the external circuit and should be long enough to allow the anode current to rise above the latching current (IL) level.


The left hand side of Fig 4.3 shows the reverse i-v characteristics of the thyristor. Once the thyristor is ON the only way to turn it OFF is by bringing the thyristor current below holding current (IH). The gate terminal has no control over the turn OFF process. In ac circuits with resistive load this happens automatically during negative zero crossing of the supply voltage. This is called “natural commutation” or “line commutation”. However, in dc circuits some arrangement has to be made to ensure this condition. This process is called “forced commutation.” During reverse blocking if ig = 0 then only reverse saturation current (Is) flows until the reverse voltage reaches reverse break down voltage (VBRR). At this point current starts rising sharply. Large reverse voltage and current generates excessive heat and destroys the device. If ig > 0 during reverse bias condition the reverse saturation current rises as explained in the previous section. This can be avoided by removing the gate current while the thyristor is reverse biased. The static output i-v characteristics of a thyristor depends strongly on the junction temperature as shown in Fig 4.4. VBRF

IA

Tj = 150° 135°

25° 75° 125°

25° 75° 125° 150° Tj

VAK

Tj = 125° 75° 25°

135° 150°

Fig. 4.4: Effect of junction temperature (Tj) on the output i – v characteristics of a thyristor.

4.4.2 Thyristor Gate Characteristics The gate circuit of a thyristor behaves like a poor quality diode with high on state voltage drop and low reverse break down voltage. This characteristic usually is not unique even within the same family of devices and shows considerable variation from device to device. Therefore, manufacturer’s data sheet provides the upper and lower limit of this characteristic as shown in Fig 4.5.


Vg

A

Vg max d

c

E

Rg

b

Vg

Pgav ⎜Max Load line

Vg min

ig

E

• S2

Pgm

K

e

h

•

Vng

S1

g

f

Ig max Ig

Ig min Fig. 4.5: Gate characteristics of a thyristor.

Each thyristor has maximum gate voltage limit (Vgmax), gate current limit (Igmax) and maximum average gate power dissipation limit ( Pgav Max ) . These limits should not be exceeded in order to avoid permanent damage to the gate cathode junction. There are also minimum limits of Vg (Vgmin) and Ig (Igmin) for reliable turn on of the thyristor. A gate non triggering voltage (Vng) is also specified by the manufacturers of thyristors. All spurious noise signals should be less than this voltage Vng in order to prevent unwanted turn on of the thyristor. The useful gate drive area of a thyristor is then b c d e f g h. Referring to the gate drive circuit in the inset the equation of the load line is given by Vg = E - Rgig A typical load line is shown in Fig 4.5 by the line S1 S2. The actual operating point will be some where between S1 & S2 depending on the particular device. For optimum utilization of the gate ratings the load line should be shifted forwards the Pgav curve without violating Vg

Max

Max

or IgMax ratings. Therefore, for a dc source E c f represents the

optimum load line from which optimum values of E & Rg can be determined. It is however customary to trigger a thyristor using pulsed voltage & current. Maximum power dissipation curves for pulsed operation (Pgm) allows higher gate current to flow which in turn reduces the turn on time of the thyristor. The value of Pgm depends on the pulse width (TON) of the gate current pulse. TON should be larger than the turn on time of the thyristor. For TON larger Version 2 EE IIT, Kharagpur 11

than 100 μs, average power dissipation curve should be used. For TON less than 100 μs the following relationship should be maintained.

δ Pgm ≤ Pgav

Max

( 4.9 )

Where δ = TON f p, f p = pulse frequency. The magnitude of the gate voltage and current required for triggering a thyristor is inversely proportional to the junction temperature. The gate cathode junction also has a maximum reverse (i.e, gate negative with respect to the cathode) voltage specification. If there is a possibility of the reverse gate cathode voltage exceeding this limit a reverse voltage protection using diode as shown in Fig 4.6 should be used. A

A

Rg G E

E K

(a)

K

(b)

Fig. 4.6: Gate Cathode reverse voltage protection circuit. Exercise 4.2 1)

Fill in the blank(s) with the appropriate word(s) i.

Forward break over voltage of a thyristor decreases with increase in the ________________ current.

ii.

Reverse ________________ voltage of a thyristor is ________________ of the gate current.

iii.

Reverse saturation current of a thyristor ________________ with gate current.

iv.

In the pulsed gate current triggering of a thyristor the gate current pulse width should be larger than the ________________ time of the device.

v.

To prevent unwanted turn ON of a thyristor all spurious noise signals between the gate and the cathode must be less than the gate ________________ voltage.


Answer: (i) gate; (ii) break down, independent; (iii) increases; (iv) Turn ON; (v) nontrigger. 2) A thyristor has a maximum average gate power dissipation limit of 0.2 watts. It is triggered with pulsed gate current at a pulse frequency of 10 KHZ and duly ratio of 0.4. Assuming the gate cathode voltage drop to be 1 volt. Find out the allowable peak gate current magnitude. Answer: On period of the gate current pulse is

TON = δ TS = δ

fs

=

0.4 sec = 40 μs < 100 μs. 10 4

Therefore, pulsed gate power dissipation limit Pgm can be used. From Equation 4.9

δ Pgm ≤ Pgav ( Max ) 0.2 watts = .5watts δ .5 = 0.5Amps. ∴ I g Max = 1

or Pgm ≤ But Pgm = Ig Vg; Vg = 1V

4.5 Thyristor ratings Some useful specifications of a thyristor related to its steady state characteristics as found in a typical “manufacturer’s data sheet” will be discussed in this section.

4.5.1 Voltage ratings Peak Working Forward OFF state voltage (VDWM): It specifics the maximum forward (i.e, anode positive with respect to the cathode) blocking state voltage that a thyristor can withstand during working. It is useful for calculating the maximum RMS voltage of the ac network in which the thyristor can be used. A margin for 10% increase in the ac network voltage should be considered during calculation. Peak repetitive off state forward voltage (VDRM): It refers to the peak forward transient voltage that a thyristor can block repeatedly in the OFF state. This rating is specified at a maximum allowable junction temperature with gate circuit open or with a specified biasing resistance between gate and cathode. This type of repetitive transient voltage may appear across a thyristor due to “commutation” of other thyristors or diodes in a converter circuit. Peak non-repetitive off state forward voltage (VDSM): It refers to the allowable peak value of the forward transient voltage that does not repeat. This type of over voltage may be caused due to switching operation (i.e, circuit breaker opening or closing or lightning surge) in a supply network. Its value is about 130% of VDRM. However, VDSM is less than the forward break over voltage VBRF.


Peak working reverse voltage (VDWM): It is the maximum reverse voltage (i.e, anode negative with respect to cathode) that a thyristor can with stand continuously. Normally, it is equal to the peak negative value of the ac supply voltage. Peak repetitive reverse voltage (VRRM): It specifies the peak reverse transient voltage that may occur repeatedly during reverse bias condition of the thyristor at the maximum junction temperature. Peak non-repetitive reverse voltage (VRSM): It represents the peak value of the reverse transient voltage that does not repeat. Its value is about 130% of VRRM. However, VRSM is less than reverse break down voltage VBRR.

Fig 4.7 shows different thyristor voltage ratings on a comparative scale. IA VBRR VRSM VRRM VRWM

VDWM VDRM VDSM

VBRF

VAK

Fig. 4.7: Voltage ratings of a thyristor.

4.5.2 Current ratings Maximum RMS current (Irms): Heating of the resistive elements of a thyristor such as metallic joints, leads and interfaces depends on the forward RMS current Irms. RMS current rating is used as an upper limit for dc as well as pulsed current waveforms. This limit should not be exceeded on a continuous basis.

Maximum average current (Iav): It is the maximum allowable average value of the forward current such that i.

Peak junction temperature is not exceeded

ii.

RMS current limit is not exceeded

Manufacturers usually provide the “forward average current derating characteristics” which shows Iav as a function of the case temperature (Tc ) with the current conduction angle φ as a parameter. The current wave form is assumed to be formed from a half cycle sine wave of power frequency as shown in Fig 4.8. Version 2 EE IIT, Kharagpur 14

Iav Amps

φ = 180°

120 φ = 120°

100 80

φ = 60°

60

φ = 30°

φ

40 20 0

∫∫

60°

80°

100°

120°

140°

TC (°C) Fig. 4.8: Average forward current derating characteristics Maximum Surge current (ISM): It specifies the maximum allowable non repetitive current the device can withstand. The device is assumed to be operating under rated blocking voltage, forward current and junction temperation before the surge current occurs. Following the surge the device should be disconnected from the circuit and allowed to cool down. Surge currents are assumed to be sine waves of power frequency with a minimum duration of ½ cycles. Manufacturers provide at least three different surge current ratings for different durations.

For example

I sM = 3000 A for 1 cycle 2 I sM = 2100 A for 3 cycles I sM = 1800 A for 5 cycles Alternatively a plot of IsM vs. applicable cycle numbers may also be provided. Maximum Squared Current integral (∫i2dt): This rating in terms of A2S is a measure of the energy the device can absorb for a short time (less than one half cycle of power frequency). This rating is used in the choice of the protective fuse connected in series with the device. Latching Current (IL): After Turn ON the gate pulse must be maintained until the anode current reaches this level. Otherwise, upon removal of gate pulse, the device will turn off. Holding Current (IH): The anode current must be reduced below this value to turn off the thyristor. Maximum Forward voltage drop (VF): Usually specified as a function of the instantaneous forward current at a given junction temperature.


Average power dissipation Pav): Specified as a function of the average forward current (Iav) for different conduction angles as shown in the figure 4.9. The current wave form is assumed to be half cycle sine wave (or square wave) for power frequency.

Pav 60°

30°

90°

φ = 180°

iF ωt φ

Iav Fig. 4.9: Average power dissipation vs average forward current in a thyristor.

In the above diagram 1 φ i dθ 2π ∫o F 1 φ Pav = v i dθ 2π ∫o F F I av =

( 4.10 ) ( 4.11)

4.5.3 Gate Specifications Gate current to trigger (IGT): Minimum value of the gate current below which reliable turn on of the thyristor can not be guaranteed. Usually specified at a given forward break over voltage. Gate voltage to trigger (VGT): Minimum value of the gate cathode forward voltage below which reliable turn on of the thyristor can not be guaranteed. It is specified at the same break over voltage as IGT. Non triggering gate voltage (VGNT): Maximum value of the gate-cathode voltage below which the thyristor can be guaranteed to remain OFF. All spurious noise voltage in the gate drive circuit must be below this level. Peak reverse gate voltage (VGRM): Maximum reverse voltage that can appear between the gate and the cathode terminals without damaging the junction.


Average Gate Power dissipation (PGAR): Average power dissipated in the gate-cathode junction should not exceed this value for gate current pulses wider than 100 μs. Peak forward gate current (IGRM): The forward gate current should not exceed this limit even on instantaneous basis. Exercise 4.3

1)

Fill in the blank(s) with the appropriate word(s) i. Peak non-repetitive over voltage may appear across a thyristor due to ________________ or ________________ surges in a supply network.

ii. VRSM rating of a thyristor is greater than the ________________ rating but less than the ________________ rating. iii. Maximum average current a thristor can carry depends on the ________________ of the thyristor and the ________________ of the current wave form. iv. The ISM rating of a thyristor applies to current waveforms of duration ________________ than half cycle of the power frequency where as the ∫i2dt rating applies to current durations ________________ than half cycle of the power frequency. v. The gate non-trigger voltage specification of a thyristor is useful for avoiding unwanted turn on of the thyristor due to ________________ voltage signals at the gate. Answer: (i) switching, lightning; (ii) VRRM, VBRR; (iii) case temperature, conduction angle; (iv) greater, less; (v) noise 2. A thyristor has a maximum average current rating 1200 Amps for a conduction angle of 180°. Find the corresponding rating for Φ = 60°. Assume the current waveforms to be half cycle sine wave. Answer: The form factor of half cycle sine waves for a conduction angle φ is given by I F.F = RMS = Iav

1 2π 1 2π

φ

∫ Sin θ dθ ∫ Sinθ dθ o φ

2

=

(

π φ - 1 Sin 2φ 2 1- Cos φ

)

o

For φ = 180°, F.F = π

2 ∴RMS current rating of the thyristor = 1200 × π

2

= 1885 Amps.

π ⎛⎜ π - 3 ⎞⎟ = 2.778 4⎠ ⎝ 3 Since RMS current rating should not exceeded For φ = 60°, F.F = 2


1200 × π

Maximum Iav for φ = 60° = 4

π ⎛⎜ π ⎝ 3

3 ⎞ 4 ⎟⎠

= 679.00 Amps.

4.6 Switching Characteristics of a Thyristor During Turn on and Turn off process a thyristor is subjected to different voltages across it and different currents through it. The time variations of the voltage across a thyristor and the current through it during Turn on and Turn off constitute the switching characteristics of a thyristor.

4.6.1 Turn on Switching Characteristics A forward biased thyristor is turned on by applying a positive gate voltage between the gate and cathode as shown in Fig 4.10. + vAK ig iA t 0.9 ION

iA

ig Vi

R

ION 0.1 ION

t

vAK

α vAK

0.9 VON VON

td

iA

Expanded scale

0.1 VON tON tr

Firing angle Vi

t tp Fig. 4.10: Turn on characteristics of a thyristor.

Fig 4.10 shows the waveforms of the gate current (ig), anode current (iA) and anode cathode voltage (VAK) in an expanded time scale during Turn on. The reference circuit and the associated waveforms are shown in the inset. The total switching period being much smaller compared to the cycle time, iA and VAK before and after switching will appear flat. As shown in Fig 4.10 there is a transition time “tON” from forward off state to forward on state. This transition time is called the thyristor turn of time and can be divided into three separate intervals namely, (i) delay time (td) (ii) rise time (tr) and (iii) spread time (tp). These times are shown in Fig 4.10 for a resistive load.


Delay time (td): After switching on the gate current the thyristor will start to conduct over the portion of the cathode which is closest to the gate. This conducting area starts spreading at a finite speed until the entire cathode region becomes conductive. Time taken by this process constitute the turn on delay time of a thyristor. It is measured from the instant of application of the gate current to the instant when the anode current rises to 10% of its final value (or VAK falls to 90% of its initial value). Typical value of “td” is a few micro seconds. Rise time (tr): For a resistive load, “rise time” is the time taken by the anode current to rise from 10% of its final value to 90% of its final value. At the same time the voltage VAK falls from 90% of its initial value to 10% of its initial value. However, current rise and voltage fall characteristics are strongly influenced by the type of the load. For inductive load the voltage falls faster than the current. While for a capacitive load VAK falls rapidly in the beginning. However, as the current increases, rate of change of anode voltage substantially decreases.

If the anode current rises too fast it tends to remain confined in a small area. This can give rise to local “hot spots” and damage the device. Therefore, it is necessary to limit the rate of rise of the ⎛ di ⎞ ON state current ⎜ A ⎟ by using an inductor in series with the device. Usual values of maximum ⎝ dt ⎠ allowable di A is in the range of 20-200 A/μs. dt Spread time (tp): It is the time taken by the anode current to rise from 90% of its final value to 100%. During this time conduction spreads over the entire cross section of the cathode of the thyristor. The spreading interval depends on the area of the cathode and on the gate structure of the thyristor.

4.6.2 Turn off Switching Characteristics Once the thyristor is on, and its anode current is above the latching current level the gate loses control. It can be turned off only by reducing the anode current below holding current. The turn off time tq of a thyristor is defined as the time between the instant anode current becomes zero and the instant the thyristor regains forward blocking capability. If forward voltage is applied across the device during this period the thyristor turns on again. During turn off time, excess minority carriers from all the four layers of the thyristor must be removed. Accordingly tq is divided in to two intervals, the reverse recovery time (trr) and the gate recovery time (tqr). Fig 4.11 shows the variation of anode current and anode cathode voltage with time during turn off operation on an expanded scale.


vAK

iA

iA

di A dt

ig Vi t

Qrr

Irr

vi

vAK

iA t Expanded scale

Vrr

trr

tq

t vi

tgr

Fig. 4.11: Turn off characteristics of a thyristor.

The anode current becomes zero at time t1 and starts growing in the negative direction with the same di A till time t2. This negative current removes excess carriers from junctions J1 & J3. At dt time t2 excess carriers densities at these junctions are not sufficient to maintain the reverse current and the anode current starts decreasing. The value of the anode current at time t2 is called the reverse recovery current (Irr). The reverse anode current reduces to the level of reverse saturation current by t3. Total charge removed from the junctions between t1 & t3 is called the reverse recovery charge (Qrr). Fast decaying reverse current during the interval t2 t3 coupled with the di limiting inductor may cause a large reverse voltage spike (Vrr) to appear across the dt device. This voltage must be limited below the VRRM rating of the device. Up to time t2 the voltage across the device (VAK) does not change substantially from its on state value. However, after the reverse recovery time, the thyristor regains reverse blocking capacity and VAK starts following supply voltage vi. At the end of the reverse recovery period (trr) trapped charges still exist at the junction J2 which prevents the device from blocking forward voltage just after trr. These trapped charges are removed only by the process of recombination. The time taken for this recombination process to complete (between t3 & t4) is called the gate recovery time (tgr). The time interval tq = trr + tgr is called “device turn off time” of the thyristor. No forward voltage should appear across the device before the time tq to avoid its inadvertent turn on. A circuit designer must provide a time interval tc (tc > tq) during which a reverse voltage is applied across the device. tc is called the “circuit turn off time”. Version 2 EE IIT, Kharagpur 20

The reverse recovery charge Qrr is a function of the peak forward current before turn off and its di for rate of decrease A . Manufacturers usually provide plots of Qrr as a function of di A dt dt different values of peak forward current. They also provide the value of the reverse recovery current Irr for a given IA and di A . Alternatively Irr can be evaluated from the given Qrr dt characteristics following similar relationships as in the case of a diode. As in the case of a diode the relative magnitudes of the time intervals t1 t2 and t2 t3 depends on the construction of the thyristor. In normal recovery “converter grade” thyristor they are almost equal for a specified forward current and reverse recovery current. However, in a fast recovery “inverter grade” thyristor the interval t2 t3 is negligible compared to the interval t1 t2. This helps reduce the total turn off time tq of the thyristor (and hence allow them to operate at higher switching frequency). However, large voltage spike due to this “snappy recovery” will appear across the device after the device turns off. Typical turn off times of converter and inverter grade thyristors are in the range of 50-100 μs and 5-50 μs respectively. As has been mentioned in the introduction thyristor is the device of choice at the very highest power levels. At these power levels (several hundreds of megawatts) reliability of the thyristor power converter is of prime importance. Therefore, suitable protection arrangement must be made against possible overvoltage, overcurrent and unintended turn on for each thyristor. At the highest power level (HVDC transmission system) thyristor converters operate from network voltage levels in excess of several hundreds of kilo volts and conduct several tens of kilo amps of current. They usually employ a large number of thyristors connected in series parallel combination. For maximum utilization of the device capacity it is important that each device in this series parallel combination share the blocking voltage and on state current equally. Special equalizing circuits are used for this purpose. Exercise 4.4

1)


A thyristor is turned on by applying a ________________ gate current pulse when it is ________________ biased.

ii.

Total turn on time of a thyristor can be divided into ________________ time ________________ time and ________________ time.

iii.

During rise time the rate of rise of anode current should be limited to avoid creating local ________________.

iv.

A thyristor can be turned off by bringing its anode current below ________________ current and applying a reverse voltage across the device for duration larger than the ________________ time of the device.

v.

Reverse recovery charge of a thyristor depends on the ________________ of the forward current just before turn off and its ________________. Version 2 EE IIT, Kharagpur 21

vi.

Inverter grade thyristors have ________________ turn off time compared to a converter grade thyristor.

Answer: (i) positive, forward; (ii) delay, rise, spread; (iii) hot spots (iv) holding, turn off; (v) magnitude, rate of decrease (vi) faster 2. With reference to Fig 4.10 find expressions for (i) turn on power loss and (ii) conduction power loss of the thyristor as a function of the firing angle ∝. Neglect turn on delay time and spread time and assume linear variation of voltage and current during turn on period. Also assume constant on state voltage VH across the thyristor. Answer: (i) For a firing angle ∝ the forward bias voltage across the thyristor just before turn on is VON = 2Vi Sin ∝ ; Vi = RMS value of supply voltage. Current after the thyristor turns on for a resistive load is I ON =

VON

R

=

2

Vi

R

Sin ∝

Neglecting delay and spread time and assuming linear variation of voltage and current during turn on ⎞ . where V has been neglected. Vak = 2 Vi Sin ∝ ⎛⎜1 - t ⎟ H t ON ⎠ ⎝

2 Vi Sin ∝ R ∴ Total switching energy loss ia =

t

t ON

t ON 2Vi 2 ⎛1 - t ⎞ t Sin 2 ∝ ∫ dt ⎜ t ON ⎟⎠ t ON o o R ⎝ 2Vi 2 t 2⎞ Vi 2 ⎛ = Sin 2 ∝ ON ⎜1 - ⎟ = Sin 2 ∝ t ON R 2 ⎝ 3⎠ 3R

E ON = ∫

t ON

v ak i a dt =

EON occurs once every cycle. If the supply frequency is f then average turn on power loss is given by. PON = E ON f =

Vi 2 Sin 2 ∝ t ON f 3R

(ii) If the firing angle is ∝ the thyristor conducts for π-∝ angle. Instantaneous current through the device during this period is 2 Vi Sin ωt ia = R ∝ Ig2 > Ig1 > Ig = 0 -VBO

Ig = 0

VBO

V

-Ig3 < Ig2 < Ig1

Fig. 4.14: Steady state V – I characteristics of a Triac

From a functional point of view a triac is similar to two thyristors connected in anti parallel. Therefore, it is expected that the V-I characteristics of Triac in the 1st and 3rd quadrant of the V-I plane will be similar to the forward characteristics of a thyristors. As shown in Fig. 4.14, with no signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak value is lower than the break over voltage (VBO) of the device. However, the turning on of the triac can be controlled by applying the gate trigger pulse at the desired instance. Mode-1 triggering is used in the first quadrant where as Mode-3 triggering is used in the third quadrant. As such, most of the thyristor characteristics apply to the triac (ie, latching and holding current). However, in a triac the two conducting paths (from MT1 to MT2 or from MT1 to MT1) interact with each other in the structure of the triac. Therefore, the voltage, current and frequency ratings of triacs are considerably lower than thyristors. At present triacs with voltage and current ratings of 1200V and 300A (rms) are available. Triacs also have a larger on state voltage drop compared to a thyristor. Manufacturers usually specify characteristics curves relating rms device current and maximum allowable case temperature as shown in Fig 4.15. Curves relating the device dissipation and RMS on state current are also provided for different conduction angles.


A

Bidirectional ON state current (RMS)

200

150 100 For all conduction angles 50

0 20°

40°

60°

80°

100°

120°

°C

Maximum allowable case temperature (TC) Fig. 4.15: RMS ON state current Vs maximum case temperature.

4.7.3 Triac Switching and gate trigger circuit Unlike a thyristor a triac gets limited time to turn off due to bidirectional conduction. As a result the triacs are operated only at power frequency. Switching characteristics of a triac is similar to that of a thyristor. However, turn off of a triac is extremely sensitive to temperature variation and may not turn off at all if the junction temperature exceeds certain limit. Problem may arise when a triac is used to control a lagging power factor load. At the current zero instant (when the triac turns off) a reverse voltage will appear across the triac since the supply voltage is negative at that instant. The rate of rise of this voltage is restricted by the triac junction capacitance only. The resulting dv may turn on the triac again. Similar problem occurs when a triac is used to dt control the power to a resistive element which has a very low resistance before normal working condition is reached. If such a load (e.g. incandescent filament lamp) is switch on at full supply voltage very large junction capacitance charging current will turn ON the device. To prevent such condition an R-C snubber is generally used across a triac. The triac should be triggered carefully to ensure safe operation. For phase control application, the triac is switched on and off in synchronism with the mains supply so that only a part of each half cycle is applied across the load. To ensure ‘clean turn ON’ the trigger signal must rise rapidly to provide the necessary charge. A rise time of about 1 μs will be desirable. Such a triac gate triggering circuit using a “diac” and an R-C timing network is shown in Fig 4.16.


LOAD

R1

R2

R

D1

V1 C

C1

Fig. 4.16: Triac triggering circuit using a diac.

In this circuit as Vi increases voltage across C1 increases due to current flowing through load, R1, R2 and C1. The voltage drop across diac D1 increases until it reaches its break over point. As D1 conducts a large current pulse is injected into the gate of the triac. By varying R2 the firing can be controlled from zero to virtually 100%. Exercise 4.5

1)


A Triac is a ________________ minority carrier device

ii.

A Triac behaves like two ________________ connected thyristors.

iii.

The gate sensitivity of a triac is maximum when the gate is ________________ with respect to MT1 while MT2 is positive with respect to MT1 or the gate is ________________ with respect to MT1 while MT2 is negative with respect to MT1

iv.

A Triac operates either in the ________________ or the ________________ quadrant of the i-v characteristics.

v.

In the ________________ quadrant the triac is fired with ________________ gate current while in the ________________ quadrant the gate current should be ________________.

vi.

The maximum possible voltage and current rating of a Triac is considerably ________________ compared to thyristor due to ________________ of the two current carrying paths inside the structure of the triac.


vii.

To avoid unwanted turn on of a triac due to large dv

dt

________________ are used

across triacs. viii.

For “clean turn ON” of a triac the ________________ of the gate current pulse should be as ________________ as possible.

Answer: (i) bidirectional; (ii) anti parallel; (iii) positive, negative; (iv) first, third; (v) first, positive, third, negative (vi) lower, interaction; (vii) R-C shubbers; (viii) rise time, small.


References 1. Dr. P.C. Sen, “Power Electronics”; Tata McGrow Hill Publishing Company Limited; New Delhi. 2. Dr. P.S. Bimbhra, “Power Electronics” Khanna Publishers


Lesson Summary •

Thyristor is a four layer, three terminal, minority carrier, semi-controlled device.

•

The three terminals of a thyristor are called the anode, the cathode and the gate.

•

A thyristor can be turned on by increasing the voltage of the anode with respect to the cathode beyond a specified voltage called the forward break over voltage.

•

A thyristor can also be turned on by injecting a current pulse into the gate terminal when the anode voltage is positive with respect to the cathode. This is called gate triggering.

•

A thyristor can block voltage of both polarity but conducts current only from anode to cathode.

•

After a thyristor turns on the gate looses control. It can be turned off only by bringing the anode current below holding current.

•

After turn on the voltage across the thyristor drops to a very low value (around 1 volt). In the reverse direction a thyristor blocks voltage up to reverse break down voltage.

•

A thyristor has a very low conduction voltage drop but large switching times. For this reason thyristors are preferred for high power, low frequency line commutated application.

•

A thyristor is turned off by bringing the anode current below holding current and simultaneously applying a negative voltage (cathode positive with respect to anode) for a minimum time called “turn off time”.

•

A triac is functionally equivalent to two anti parallel connected thyristors. It can block voltages in both directions and conduct current in both directions.

•

A triac has three terminals like a thyristor. It can be turned on in either half cycle by either a positive on a negative current pulse at the gate terminal.

•

Triacs are extensively used at power frequency ac load (eg heater, light, motors) control applications.


Practice Problems and Answers


1. Explain the effect of increasing the magnitude of the gate current and junction temperature on (i) forward and reverse break down voltages, (ii) forward and reverse leakage currents. Th 15 V •

R

•

N1 N2

iB

2. The thyristor Th is triggered using the pulse transformer shown in figure. The pulse transformer operates at 10 KHZ with a duty cycle of 40%. The thyristor has maximum average gate power dissipation limit of 0.5 watts and a maximum allow able gate voltage limit of 10 volts. Assuming ideal pulse transformer, find out the turns ratio N1/N2 and the value of R. Fuse i1 Vi if 220 V 50 HZ

3. A thyristor full bridge converter is used to drive a dc motor as shown in the figure. The thyristors are fired at a firing angle ∝ = 0° when motor runs at rated speed. The motor has on armature resistance of 0.2 Ω and negligible armature inductance. Find out the peak surge current rating of the thyristors such that they are not damaged due to sudden loss of field excitation to the motor. The protective fuse in series with the motor is designed to disconnect the motor within 1 cycle of fault. Find out the ∫ i 2 dt rating of the 2 thyristors. 4. Why is it necessary to maximize the peripheral contact area of the gate and the cathode regions? A thyristor used to control the voltage applied to a load resistance from a 220v, Version 2 EE IIT, Kharagpur 33

50HZ single phase ac supply has a maximum value of the

di a

dt

di a

dt

rating of 50 A / μs. Find out the

limiting inductor to be connected in series with the load resistance. THM

200V

+

C

THA

20 A

200V

5. In a voltage commutated dc – dc thyristor chopper the main thyristor THM is commutated by connecting a pre-charged capacitor directly across it through the auxiliary thyristor THA as shown in the figure. The main thyristor THM has a turn off time off 50μs and maximum dv rating of 500v/ μs. Find out a suitable value of C for safe dt commutation of THM.


Answers to Practice Problems


1. i.

ii.

Forward break down voltage reduces with increasing gate current. It increases with junction temperature up to certain value of the junction temperature and then falls rapidly with any further increase in temperature. Reverse break down voltage is independent of the gate current magnitude but decreases with increasing junction temperature. Forward leakage current is independent of the gate current magnitude but increases with junction temperature. Reverse leakage current increases with both the junction temperature and the magnitude of the gate current. THM

200V

C

+

THA

20 A

200V

2. Figure shows the equivalent gate drive circuit of the thyristor. For this circuit one can write E = R i g + Vg OR Vg = E - R i g The diode D clamps the gate voltage to zero when E goes negative. Now for ig = O,

But E =

N2

Since Vg

Vg = E.

N1

15

∴

N2

N1

Max

= 15

= 10 v 10

E = 10 v

= 1.5

Gate pulse width = 0.4 × 10-4 Sec = 40μs. 2 1556 Amps. The fuse blows within 1

cycle of the fault occurring. Therefore the thyristors must withstand 2 the fault for at least 1 cycle. 2 2 Therefore, the i t rating of the thyristor should be


10-2

∫ (1556 Sin 100 π t )

2 ∫ i dt =

2

0

=

(1556 )

2

2

∫

10-2

0

[1 -

Cos 200 π t ] dt

2 = 1 × 10 -2 (1556 ) = 1.21× 10 4 A 2 Sec 2

4. At the beginning of the turn on process the thyristor starts conducting through the area adjacent to the gate. This area spreads at a finite speed. However, if rate of increase of anode current is lager than the rate of increase of the current conduction are, the current density increases with time. This may lead to thyristor failure due to excessive local heating. However, if the contact area between the gate and the cathode is large a thyristor will be able to handle a di relatively large a without being damaged. dt di a

The maximum

L Since

di a

dt

Max

dt

will occur when the thyristor is triggered at ∝ = 90°. Then

di a = dt

2 × 220 Sin 90 0

= 50 × 10 6 A Sec

L

min

=

2 × 220 = 6.22 × 10 -6 H = 6.22 μH ⎛ di a ⎞ ⎜ dt ⎟ ⎝ ⎠ Max

VC

toff

vTHM

200 V

dv / dt

t

iC 20 Amps. t


5. As soon as THA is turned on the load current transfer from THM to C. the voltage across THM is the negative of the capacitance voltage. Figure shows the waveforms of voltage across the capacitor (vc), voltage across the main thyristor (VTHM) and the capacitor current ic. From dv i = c figure c dt dv = 500 v μs Now ic = 20 Amps & dt Max

∴ C

Min

=

ic

dv dt

= Max

20 -8 F = 0.04 μF 6 = 4 × 10 500×10

The circuit turn off time is the time taken by the capacitor voltage to reach zero from an initial value of 200v. This time must be greater than the turn off time of the device.

dv c = i c = 20 dt 20 × Δt ∴ Δv c = c

Now C

Δv = 200 - 0 = 200 Δt = t off

20 × 50 × 10 -6 C 20 × 50 × 10 -6 ∴C = = 5 μF 200

∴ 200 =

For safe commutation of THM the higher value of C must the chosen ∴ the required value of C = 5 μF.



Lesson 5 Gate Turn Off Thyristor (GTO) Version 2 EE IIT, Kharagpur 2

Instructional objective On completion the student will be able to •

Differentiate between the constructional features of a GTO and a Thyristor.

•

Explain the turn off mechanism of a GTO.

•

Differentiate between the steady state output and gate characteristics of a GTO and a thyristor.

•

Draw and explain the switching characteristics of a GTO.

•

Draw the block diagram of a GTO gate drive unit and explain the functions of different blocks.

•

Interpret the manufacturer’s data sheet of a GTO.


Introduction The thyristor has reigned supreme for well over two decades in the power electronics industry and continues to do so at the very highest level of power. It, however, has always suffered from the disadvantage of being a semi-controlled device. Although it could be turned on by applying a gate pulse but to turn it off the main current had to be interrupted. This proved to be particularly inconvenient in DC to AC and DC to DC conversion circuits, where the main current does not naturally becomes zero. A bulky and expensive “commutation circuit” had to be used to ensure proper turning off of the thyristor. The switching speed of the device was also comparatively slow even with fast inverter grade thyristor. The development of the Gate Turn off thyristor (GTO) has addressed these disadvantages of a thyristor to a large extent. Although it has made a rather late entry (1973) into the thyristor family the technology has matured quickly to produce device comparable in rating (5000V, 4000Amp) with the largest available thyristor. Consequently it has replaced the forced commutated inverter grade thyristor in all DC to AC and DC to DC converter circuits. Like thyristor, the GTO is a current controlled minority carrier (i.e. bipolar) device. GTOs differ from conventional thyristor in that, they are designed to turn off when a negative current is sent through the gate, thereby causing a reversal of the gate current. A relatively high gate current is need to turn off the device with typical turn off gains in the range of 4-5. During conduction, on the other hand, the device behaves just like a thyristor with very low ON state voltage drop. Several different varieties of GTOs have been manufactured. Devices with reverse blocking capability equal to their forward voltage ratings are called “symmetric GTOs”. However, the most poplar variety of the GTO available in the market today has no appreciable reverse voltage (20-25v) blocking capacity. These are called “Asymmetric GTOs”. Reverse conducting GTOs (RC-GTO) constitute the third family of GTOs. Here, a GTO is integrated with an anti-parallel freewheeling diode on to the same silicon wafer. This lesson will describe the construction, operating principle and characteristic of “Asymmetric GTOs” only.

5.2 Constructional Features of a GTO Fig 5.1 shows the circuit symbol and two different schematic cross section of a GTO.


A

p+

n+

Anode Short.

p+

n+

(a)

J1

n-

J2 J3

p

p

n+

n+

K

p+ n

Buffer Layer

n

G

p+

Anode Contact

G

n+

n+

G C (b)

C (c)

Fig. 5.1: Circuit symbol and schematic cross section of a GTO (a) Circuit Symbol, (b) Anode shorted GTO structure, (c) Buffer layer GTO structure. Like a thyristor, a GTO is also a four layer three junction p-n-p-n device. In order to obtain high emitter efficiency at the cathode end, the n+ cathode layer is highly doped. Consequently, the break down voltage of the function J3 is low (typically 20-40V). The p type gate region has conflicting doping requirement. To maintain good emitter efficiency the doping level of this layer should be low, on the other hand, from the point of view of good turn off properties, resistively of this layer should be as low as possible requiring the doping level of this region to be high. Therefore, the doping level of this layer is highly graded. Additionally, in order to optimize current turn off capability, the gate cathode junction must be highly interdigitated. A 3000 Amp GTO may be composed of upto 3000 individual cathode segments which are a accessed via a common contact. The most popular design features multiple segments arranged in concentric rings around the device center. The maximum forward blocking voltage of the device is determined by the doping level and the thickness of the n type base region next. In order to block several kv of forward voltage the doping level of this layer is kept relatively low while its thickness is made considerably higher (a few hundred microns). Byond the maximum allowable forward voltage either the electric field at the main junction (J2) exceeds a critical value (avalanche break down) or the n base fully depletes, allowing its electric field to touch the anode emitter (punch through). The junction between the n base and p+ anode (J1) is called the “anode junction”. For good turn on properties the efficiency of this anode junction should be as high as possible requiring a heavily doped p+ anode region. However, turn off capability of such a GTO will be poor with very low maximum turn off current and high losses. There are two basic approaches to solve this problem. In the first method, heavily doped n+ layers are introduced into the p+ anode layer. They make contact with the same anode metallic contact. Therefore, electrons traveling through the base can directly reach the anode metal contact without causing hole injection from the p+ anode. This is the classic “anode shorted GTO structure” as shown in Fig 5.1 (b). Due to presence of these “anode shorts” the reverse voltage blocking capacity of GTO reduces to the reverse break down Version 2 EE IIT, Kharagpur 5

voltage of junction J3 (20-40 volts maximum). In addition a large number of “anode shorts” reduces the efficiency of the anode junction and degrades the turn on performance of the device. Therefore, the density of the “anode shorts” are to be chosen by a careful compromise between the turn on and turn off performance. In the other method, a moderately doped n type buffer layer is juxtaposed between the n- type base and the anode. As in the case of a power diode and BJT this relatively high density buffer layer changes the shape of the electric field pattern in the n- base region from triangular to trapezoidal and in the process, helps to reduce its width drastically. However, this buffer layer in a conventional “anode shorted” GTO structure would have increased the efficiency of the anode shorts. Therefore, in the new structure the anode shorts are altogether dispensed with and a thin p+ type layer is introduce as the anode. The design of this layer is such that electrons have a high probability of crossing this layer without stimulating hole injection. This is called the “Transparent emitter structure” and is shown in Fig 5.1 (c). Exercise 5.1 Fill in the blank(s) with the appropriate word(s) i.

A GTO is a _______________ controlled _______________ carrier device.

ii.

A GTO has _______________ layers and _______________ terminals.

iii.

A GTO can be turned on by injecting a _______________ gate current and turned off by injecting a _______________ gate current.

iv.

The anode shorts of a GTO improves the _______________ performance but degrades the _______________ performance.

v.

The reverse voltage blocking capacity of a GTO is small due to the presence of _______________.

Answer: (i) current, minority; (ii) four, three; (iii) positive, negative; (iv) turn off, turn on; (v) anode shorts.

5.3 Operating principle of a GTO GTO being a monolithic p-n-p-n structure just like a thryistor its basic operating principle can be explained in a manner similar to that of a thyristor. In particular, the p-n-p-n structure of a GTO can be though of consisting of one p-n-p and one n-p-n transistor connected in the regenerative configuration as shown in Fig 5.2.


A

A

A p n

Hole current Electron G current

αn

n C

IG iB2

n

p

p

n

n

iC1

iC2

p

p

αp

iB

n

G

p

IA

G

p

n

Hole current Electron current

IK C

C

G

p A

(b)

(a) Fig 5.2: Current distribution in a GTO (a) During turn on; (b) During turn off.

From the “two transistor analogy” (Fig 5.2 (a)) of the GTO structure one can write.

i C1 = ∝p I A + ICBO1 i B1 = i C 2 = ∝n I k + ICBO2 I k = I A + IG and IA = i B1 + i C1

Combining I A =

∝n IG + ( iCBO1 + i CBO2 ) 1- ( ∝n + ∝p )

( 5.1) ( 5.2 ) ( 5.3)

( 5.4 )

With applied forward voltage VAK less than the forward break over voltage both ICBO1 and ICBO2 are small. Further if IG is zero IA is only slightly higher than (ICBO1 + ICBO2). Under this condition both ∝n and ∝p are small and (∝p + ∝n) VGS1

+++ ++++++++

Source Electrode

Gate Electrode Si02

n+

p

Ionized acceptor

Free electron

Depletion layer boundary.

n(b)


VGS3

VGS3 > VGS2 > VGS1

+++ ++++++++

Source Electrode

Gate Electrode Si02 Inversion layer with free electrons

n+

Depletion layer boundary.

p Ionized acceptor

n-

(c) Fig. 6.4: Gate control of MOSFET conduction. (a) Depletion layer formation; (b) Free electron accumulation; (c) Formation of inversion layer. The positive charge induced on the gate metallization repels the majority hole carriers from the interface region between the gate oxide and the p type body. This exposes the negatively charged acceptors and a depletion region is created. Further increase in VGS causes the depletion layer to grow in thickness. At the same time the electric field at the oxide-silicon interface gets larger and begins to attract free electrons as shown in Fig 6.4 (b). The immediate source of electron is electron-hole generation by thermal ionization. The holes are repelled into the semiconductor bulk ahead of the depletion region. The extra holes are neutralized by electrons from the source. As VGS increases further the density of free electrons at the interface becomes equal to the free hole density in the bulk of the body region beyond the depletion layer. The layer of free electrons at the interface is called the inversion layer and is shown in Fig 6.4 (c). The inversion layer has all the properties of an n type semiconductor and is a conductive path or “channel” between the drain and the source which permits flow of current between the drain and the source. Since current conduction in this device takes place through an n- type “channel” created by the electric field due to gate source voltage it is called “Enhancement type n-channel MOSFET”. The value of VGS at which the inversion layer is considered to have formed is called the “Gate – Source threshold voltage VGS (th)”. As VGS is increased beyond VGS(th) the inversion layer gets some what thicker and more conductive, since the density of free electrons increases further with increase in VGS. The inversion layer screens the depletion layer adjacent to it from increasing VGS. The depletion layer thickness now remains constant.


Exercise 6.1 (after section 6.3) 1.


A MOSFET is a ________________ controlled ________________ carrier device.

ii.

Enhancement type MOSFETs are normally ________________devices while depletion type MOSFETs are normally ________________ devices.

iii.

The Gate terminal of a MOSFET is isolated from the semiconductor by a thin layer of ________________.

iv.

The MOSFET cell embeds a parasitic ________________ in its structure.

v.

The gate-source voltage at which the ________________ layer in a MOSFET is formed is called the ________________ voltage.

vi.

The thickness of the ________________ layer remains constant as gate source voltage is increased byond the ________________ voltage.

Answer: (i) voltage, majority; (ii) off, on; (iii) SiO2, (iv) BJT, (v) inversion, threshold; (vi) depletion, threshold. 2.

What are the main constructional differences between a MOSFET and a BJT? What effect do they have on the current conduction mechanism of a MOSFET? Answer: A MOSFET like a BJT has alternating layers of p and n type semiconductors. However, unlike BJT the p type body region of a MOSFET does not have an external electrical connection. The gate terminal is insulated for the semiconductor by a thin layer of SiO2. The body itself is shorted with n+ type source by the source metallization. Thus minority carrier injection across the source-body interface is prevented. Conduction in a MOSFET occurs due to formation of a high density n type channel in the p type body region due to the electric field produced by the gate-source voltage. This n type channel connects n+ type source and drain regions. Current conduction takes place between the drain and the source through this channel due to flow of electrons only (majority carriers). Where as in a BJT, current conduction occurs due to minority carrier injection across the Base-Emitter junction. Thus a MOSFET is a voltage controlled majority carrier device while a BJT is a minority carrier bipolar device.

6.4 Steady state output i-v characteristics of a MOSFET The MOSFET, like the BJT is a three terminal device where the voltage on the gate terminal controls the flow of current between the output terminals, Source and Drain. The source terminal is common between the input and the output of a MOSFET. The output characteristics of a MOSFET is then a plot of drain current (iD) as a function of the Drain – Source voltage (vDS) with gate source voltage (vGS) as a parameter. Fig 6.5 (a) shows such a characteristics.


VGS – VGS (th) = VDS iD

ohmic rDS(ON)

Electron Drift Velocity

Increasing VGS VGS6 Active VGS5 [VGS–VGS(th)] (vGS – vGS (th)) the iD – vDS characteristics deviates from the linear relationship of the ohmic region and for a given vGS, iD tends to saturate with increase in vDS. The exact mechanism behind this is rather complex. It will suffice to state that, at higher drain current the voltage drop across the channel resistance tends to decrease the channel width at the drain drift layer end. In addition, at large value of the electric field, produced by the large Drain – Source voltage, the drift velocity of free electrons in the channel tends to saturate as shown in Fig 6.5 (c). As a result the drain current becomes independent of VDS and determined solely by the gate – source voltage vGS. This is the active mode of operation of a MOSFET. Simple, first order theory predicts that in the active region the drain current is given approximately by

i D = K(vGS - vGS (th))2

(6.1)

Where K is a constant determined by the device geometry. At the boundary between the ohmic and the active region vDS = vGS - vGS (th) (6.2) Therefore, i D = KvDS2

(6.3)

Equation (6.3) is shown by a dotted line in Fig 6.5 (a). The relationship of Equation (6.1) applies reasonably well to logic level MOSFETs. However, for power MOSFETs the transfer characteristics (iD vs vGS) is more linear as shown in Fig 6.5 (d). At this point the similarity of the output characteristics of a MOSFET with that of a BJT should be apparent. Both of them have three distinct modes of operation, namely, (i)cut off, (ii) active and (iii) ohmic (saturation for BJT) modes. However, there are some important differences as well. •

Unlike BJT a power MOSFET does not undergo second break down.

•

The primary break down voltage of a MOSFET remains same in the cut off and in the active modes. This should be contrasted with three different break down voltages (VSUS, VCEO & VCBO) of a BJT.

•

The ON state resistance of a MOSFET in the ohmic region has positive temperature coefficient which allows paralleling of MOSFET without any special arrangement for current sharing. On the other hand, vCE (sat) of a BJT has negative temperature coefficient making parallel connection of BJTs more complicated.

As in the case of a BJT the operating limits of a MOSFET are compactly represented in a Safe Operating Area (SOA) diagram as shown in Fig 6.6. As in the case of the FBSOA of a Version 2 EE IIT, Kharagpur 12

BJT the SOA of a MOSFET is plotted on a log-log graph. On the top, the SOA is restricted by the absolute maximum permissible value of the drain current (IDM) which should not be exceeded even under pulsed operating condition. To the left, operating restriction arise due to the non zero value of rDS(ON) corresponding to vGS = vGS(Max). To the right, the first operating restriction is due to the limit on the maximum permissible junction temperature rise which depends on the power dissipation inside the MOSFET. This limit is different for DC (continuous) and pulsed operation of different pulse widths. As in the case of a BJT the pulsed safe operating areas are useful for shaping the switching trajectory of a MOSFET. A MOSFET does not undergo “second break down” and no corresponding operating limit appears on the SOA. The final operation limit to the extreme right of the SOA arises due to the maximum permissible drain source voltage (VDSS) which is decided by the avalanche break down voltage of the drain -body p-n junction. This is an instantaneous limit. There is no distinction between the forward biased and the reverse biased SOAs for the MOSFET. They are identical. Log (iD) IDM 10-5sec rDS(ON) limit 10-4sec (VGS = VGS(max)) Max. 10-3sec Power Dissipation DC Limit (Timax) Primary voltage breakdown limit VDSS Log (vDS) Fig. 6.6: Safe operating area of a MOSFET. Due to the presence of the anti parallel “body diode”, a MOSFET can not block any reverse voltage. The body diode, however, can carry an RMS current equal to IDM. It also has a substantial surge current carrying capacity. When reverse biased it can block a voltage equal to VDSS. For safe operation of a MOSFET, the maximum limit on the gate source voltage (VGS (Max)) must be observed. Exceeding this voltage limit will cause dielectric break down of the thin gate oxide layer and permanent failure of the device. It should be noted that even static charge inadvertently put on the gate oxide by careless handling may destroy it. The device user should ground himself before handling any MOSFET to avoid any static charge related problem. Exercise 6.2 Fill in the blank(s) with the appropriate word(s) i.

A MOSFET operates in the ________________ mode when vGS < vGS(th) Version 2 EE IIT, Kharagpur 13

ii.

In the ohmic region of operation of a MOSFET vGS – vGS (th) is greater than ________________.

iii.

rDS (ON) of a MOSFET ________________ with increasing vGS.

iv.

In the active region of operation the drain current iD is a function of ________________ alone and is independent of ________________.

v.

The primary break down voltage of MOSFET is ________________ of the drain current.

vi.

Unlike BJT a MOSFET does not undergo ________________.

vii.

________________ temperature coefficient of rDS(ON) of MOSFETs facilitates easy ________________ of the devices.

viii.

In a Power MOSFET the relation ship between iD and vGS – vGS(th) is almost ________________ in the active mode of operation.

ix.

The safe operating area of a MOSFET is restricted on the left hand side by the ________________ limit.

Answer: (i) Cut off; (ii) vDS; (iii) decreases; (iv) vGS, vDS; (v) independent; (vi) break down; (vii) Positive, paralleling; (viii) linear; (ix) rDS (ON);

second

6.5 Switching characteristics of a MOSFET 6.5.1 Circuit models of a MOSFET cell Like any other power semiconductor device a MOSFET is used as a switch in all power electronic converters. As a switch a MOSFET operates either in the cut off mode (switch off) or in the ohmic mode (switch on). While making transition between these two states it traverses through the active region. Being a majority carrier device the switching process in a MOSFET does not involve any inherent delay due to redistribution of minority charge carriers. However, formation of the conducting channel in a MOSFET and its disappearance require charging and discharging of the gate-source capacitance which contributes to the switching times. There are several other capacitors in a MOSFET structure which are also involved in the switching process. Unlike bipolar devices, however, these switching times can be controlled completely by the gate drive circuit design.


G

S

Gate oxide +

n

p

CGD

CGD

CGS

Drain body depletion layer

CDS n-

Actual CGD2

n+

(b)

D

D

CGD

D

CGD (cut off)

CGS

CGD

G

iD = f(vGS)

G

(Active)

CGS S

VDS

VGS – VGS (th) = VDS

D

(a)

G

idealized

CGD1

rDS(ON) (Ohmic)

CGS

S

S

(c) Fig. 6.7: Circuit model of a MOSFET (a) MOSFET capacitances (b) Variation of CGD with VDS (c) Circuit models. Fig 6.7 (a) shows three important capacitances inherent in a MOSFET structure. The most prominent capacitor in a MOSFET structure is formed by the gate oxide layer between the gate metallization and the n+ type source region. It has the largest value (a few nano farads) and remains more or less constant for all values of vGS and vDS. The next largest capacitor (a few hundred pico forwards) is formed by the drain – body depletion region directly below the gate metallization in the n- drain drift region. Being a depletion layer capacitance its value is a strong function of the drain source voltage vDS. For low values of vDS (vDS < (vGS – vGS (th))) the value of CGD (CGD2) is considerably higher than its value for large vDS as shown in Fig 6.7 (b). Although variation of CGD between CGD1 and CGD2 is continuous a step change in the value of CGD at vDS = vGS – vGS(th) is assumed for simplicity. The lowest value capacitance is formed between the drain and the source terminals due to the drain – body depletion layer away form the gate metallization and below the source metallization. Although this capacitance is important for some design considerations (such as snubber design, zero voltage switching etc) it does not appreciably affect the “hard switching” performance of a MOSFET. Consequently, it will be neglected in our discussion. From the Version 2 EE IIT, Kharagpur 15

above discussion and the steady state characteristics of a MOSFET the circuit models of a MOSFET in three modes of operation can be drawn as shown in Fig 6.7 (c).

6.5.2 Switching waveforms The switching behavior of a MOSFET will be described in relation to the clamped inductive circuit shown in Fig 6.8. For simplicity the load current is assumed to remain constant over the small switching interval. Also the diode DF is assumed to be ideal with no reverse recovery current. The gate is assumed to be driven by an ideal voltage source giving a step voltage between zero and Vgg in series with an external gate resistance Rg. VD DF

IO if

+ iD

CGD

VDS

Rg Vgg

+ -

ig

-

CGS

Fig. 6.8: Clamped inductive switching circuit using a MOSFET. To turn the MOSFET on, the gate drive voltage changes from zero to Vgg. The gate source voltage which was initially zero starts rising towards Vgg with a time constant τ1 = Rg (CGS + CGD1) as shown in Fig 6.9.


Vgg VGS VGSI0 VGS(th)

Vgg

∫∫

τ2 τ1

τ2 = Rg(CGS+CGD2)

t

∫∫

ig

τ1 = Rg(CGS+CGD1)

R g igI0

−

iD, if

iD I0 if

∫∫ Vgg

igI0

t

Rg

if

∫∫

I0 iD

∫∫

t

VDS I0ros (ON) ∫∫

tdON tri

tfv1 tfv2 tON

t

td(off) trv2 trvi tfi toff

Fig. 6.9: Switching waveforms of a clamped inductive switching circuit using MOSFET Note that during this period the drain voltage vDS is clamped to the supply voltage VD through the free wheeling diode DF. Therefore, CGS and CGD can be assumed to be connected in parallel effectively. A part of the total gate current ig charges CGS while the other part discharges CGD. Till vGS reaches vGS (th) no drain current flows. This time period is called turn on delay time (td(ON)). Note that td(ON) can be controlled by controlling Rg. Byond td(ON) iD increases linearly with vGS and in a further time tri (current rise time) reaches Io. The corresponding value of vGS and ig are marked as VGS Io and ig Io respectively in Fig 6.9. At this point the complete load current has been transferred to the MOSFET from the free wheeling diode DF. iD does not increase byond this point. Since in the active region iD and vGS are linearly related, vGS also becomes clamped at the value vGSIo. The gate current ig now discharges CGD and the drain voltage starts falling. ig V -V I d d d v DS = ( vGS + vGD ) = v GD = = GG GS o dt dt dt CGD CGD R g

( 6.4 )


The fall of vDS occurs in two distinct intervals. When the MOSFET is in the active region (vDS > (vGS – vGS (th)) CGD = CGD1.Since CGD1 > CGD1. Therefore, rate of fall of vDS slows down considerably (tfv2). Once vDS reaches its on state value (rDS(ON) Io) vGS becomes unclamped and increases towards Vgg with a time constant τ2 = Rg (CGS + CGD2). Note that all switching periods can be reduced by increasing Vgg or / and decreasing Rg. The total turn on time is tON = td(ON) + tri + tfv1 + tfv2. To turn the MOSFET OFF, Vgg is reduced to zero triggering the exact reverse process of turn on to take place. The corresponding waveforms and switching intervals are show in Fig 6.9. The total turn off time toff = td(off) + trv1 + trv2 + tfi.

6.5.3 MOSFET Gate Drive MOSFET, being a voltage controlled device, does not require a continuous gate current to keep it in the ON state. However, it is required to charge and discharge the gate-source and the gate-drain capacitors in each switching operation. The switching times of a MOSFET essentially depends on the charging and discharging rate of these capacitors. Therefore, if fast charging and discharging of a MOSFET is desired at fast switching frequency the gate drive power requirement may become significant. Fig 6.10 (a) shows a typical gate drive circuit of a MOSFET.


VGG

VD VGG

RG +

R1 (β1 +1)

R1 Q1

Logic level gate pulse

RG RG

Q2

VGG

Q3

(b)

(a) VD

DF

D

IL

R RG

R

D

S

B G

G

RB (d)

S (c)

Fig. 6.10: MOSFET gate drive circuit. (a) Gate drive circuit; (b) Equivalent circuit during turn on and off; (b) Effect of parasitic BJT; (d) Parallel connection of MOSFET’s. To turn the MOSFET on the logic level input to the inverting buffer is set to high state so that transistor Q3 turns off and Q1 turns on. The top circuit of Fig 6.10 (b) shows the equivalent circuit during turn on. Note that, during turn on Q1 remains in the active region. The effective gate resistance is RG + R1 / (β1 + 1). Where, β1 is the dc current gain of Q1.


To turn off the MOSFET the logic level input is set to low state. Q3 and Q2 turns on whole Q1 turns off. The corresponding equivalent circuit is given by the bottom circuit of Fig 6.10 (b) The switching time of the MOSFET can be adjusted by choosing a proper value of RG. Reducing RG will incase the switching speed of the MOSFET. However, caution should be exercised while increasing the switching speed of the MOSFET in order not to turn on the parasitic BJT in the MOSFET structure inadvertently. The drain-source capacitance (CDS) is actually connected to the base of the parasitic BJT at the p type body region. The body source short has some nonzero resistance. A very fast rising drain-source voltage will send sufficient displacement current through CDS and RB as shown in Fig 6.10 (c). The voltage drop across RB may become sufficient to turn on the parasitic BJT. This problem is largely avoided in a modern MOSFET design by increasing the effectiveness of the body-source short. The devices are now capable of dvDS/dt in excess to 10,000 V/μs. Of course, this problem can also be avoided by slowing down the MOSFET switching speed. Since MOSFET on state resistance has positive temperature coefficient they can be paralleled without taking any special precaution for equal current sharing. To parallel two MOSFETs the drain and source terminals are connected together as shown in Fig 6.10 (d). However, small resistances (R) are connected to individual gates before joining them together. This is because the gate inputs are highly capacitive with almost no losses. Some stray inductance of wiring may however be present. This stray inductance and the MOSFET capacitance can give rise to unwanted high frequency oscillation of the gate voltage that can result in puncture of the gate qxide layer due to voltage increase during oscillations. This is avoided by the damping resistance R. Exercise 6.3 1.


The Gate-Source capacitance of a MOSFET is the ________________ among all three capacitances.

ii.

The Gate-Drain transfer capacitance of a MOSFET has large value in the ________________ region and small value in the ________________ region.

iii.

During the turn on delay time the MOSFET gate source voltage rises from zero to the ________________ voltage.

iv.

The voltage fall time of a MOSFET is ________________ proportional to the gate charging resistance.

v.

Unlike BJT the switching delay times in a MOSFET can be controlled by proper design of the ________________ circuit.

Answer: (i) largest; (ii) ohmic, active; (iii) threshold; (iv) inversely; (v) gate drive. Version 2 EE IIT, Kharagpur 20

2. A Power MOSFET has the following data CGS = 800 pF ; CGD = 150 pF; gf = 4; vGS(th) = 3V; It is used to switch a clamped inductive load (Fig 6.8) of 20 Amps with a supply voltage VD= 200V. The gate drive voltage is vgg = 15V, and gate resistance Rg = 50Ω. Find out maximum dv DS did and during turn ON. value of dt dt Answer: During turn on i D ≈ g f ( v gs - v gs (th) ) dv gs di D = gf dt dt dv V -v But ( CGS + CGD ) gs = gg gs dt Rg ∴

∴

∴

di D dt

dv di D gf = g f gs = ( Vgg - vgs ) dt dt R g ( CGS + CGD )

= Max

gf

R g ( CGS + CGD

since for vgs < vgs (th)

∴

di D dt

= Max

(V )

iD =

gg

- vgs

Min

)=

g f ( Vgg - vgs (th) ) R g ( CGS + CGD )

di D =0 dt

4 15 - 3) = 1.01×109 A sec -12 ( 50×950×10

From equation (6.4) dv DS Vgg - VGS , Io = dt CGD R g

For Io = 20 A, vgs(th) = 3V, and gf = 4 I 20 VGS , Io = o + vgs (th) = + 3 = 8 volts gf 4

∴

dv DS 15 -8 = = 933×106 V sec. dt 150×10-12 ×50

6.6

MOSFET Ratings Steady state operating limits of a MOSFET are usually specified compactly as a safe operating area (SOA) diagram. The following limits are specified. VDSS: This is the drain-source break down voltage. Exceeding this limit will destroy the device due to avalanche break down of the body-drain p-n junction.


IDM: This is the maximum current that should not be exceeded even under pulsed current operating condition in order to avoid permanent damage to the bonding wires. Continuous and Pulsed power dissipation limits: They indicate the maximum allowable value of the VDS, iD product for the pulse durations shown against each limit. Exceeding these limits will cause the junction temperature to rise beyond the acceptable limit.

All safe operating area limits are specified at a given case temperature. In addition, several important parameters regarding the dynamic performance of the device are also specified. These are Gate threshold voltage (VGS (th)): The MOSFET remains in the cut off region when vGS in below this voltage. VGS (th) decreases with junction temperature. Drain Source on state resistance (rDS (ON)): This is the slope of the iD – vDS characteristics in the ohmic region. Its value decreases with increasing vGS and increases with junction temperature. rDS (ON) determines the ON state power loss in the device. Forward Transconductance (gfs): It is the ratio of iD and (vGS – vGS(th)). In a MOSFET switching circuit it determines the clamping voltage level of the gate – source voltage and thus influences dvDS/dt during turn on and turn off. Gate-Source breakdown voltage: Exceeding this limit will destroy the gate structure of the MOSFET due to dielectric break down of the gate oxide layer. It should be noted that this limit may by exceeded even by static charge deposition. Therefore, special precaution should be taken while handing MOSFETs. Input, output and reverse transfer capacitances (CGS, CDS & CGD): Value of these capacitances are specified at a given drain-source and gate-source voltage. They are useful for designing the gate drive circuit of a MOSFET.

In addition to the main MOSFET, specifications pertaining to the “body diode” are also provided. Specifications given are Reverse break down voltage: This is same as VDSS Continuous ON state current (IS): This is the RMS value of the continuous current that can flow through the diode. Pulsed ON state current (ISM): This is the maximum allowable RMS value of the ON state current through the diode given as a function of the pulse duration. Forward voltage drop (vF): Given as an instantaneous function of the diode forward current. Reverse recovery time (trr) and Reverse recovery current (Irr): These are specified as functions of the diode forward current just before reverse recovery and its decreasing slope (diF/dt).


Exercise 6.4


The maximum voltage a MOSFET can with stand is ________________ of drain current.

ii.

The FBSOA and RBSOA of a MOSFET are ________________.

iii.

The gate source threshold voltage of a MOSFET ________________ with junction temperature while the on state resistance ________________ with junction temperature.

iv.

The gate oxide of a MOSFET can be damaged by ________________ electricity.

v.

The reverse break down voltage of the body diode of a MOSFET is equal to ________________ while its RMS forward current rating is equal to ________________.

Answer: (i) independent; (ii) identical; (iii) decreases, increases; (iv) static; (v) VDSS; IDM.

Reference [1] “Evolution of MOS-Bipolar power semiconductor Technology”, B. Jayant Baliga, Proceedings of the IEEE, VOL.76, No-4, April 1988. [2] “Power Electronics ,Converters Application and Design” Third Edition, Mohan, Undeland, Robbins. John Wiley & Sons Publishers 2003. [3] GE – Power MOSFET data sheet.


Lesson Summary •

MOSFET is a voltage controlled majority carrier device.

•

A Power MOSFET has a vertical structure of alternating p and n layers.

•

The main current carrying terminals of an n channel enhancement mode MOSFET are called the Drain and the Source and are made up of n+ type semiconductor.

•

The control terminal is called the Gate and is isolated form the bulk semiconductor by a thin layer of SiO2.

•

p type semiconductor body separates n+ type source and drain regions.

•

A conducting n type channel is produced in the p type body region when a positive voltage greater than a threshold voltage is applied at the gate.

•

Current conduction in a MOSFET occurs by flow of electron from the source to the drain through this channel.

•

When the gate source voltage is below threshold level a MOSFET remains in the “Cut Off” region and does not conduct any current.

•

With vGS > vGS (th) and vDS < (vGS – vGS (th)) the drain current in a MOSFET is proportional to vDS. This is the “Ohmic region” of the MOSFET output characteristics.

•

For larger values of vDS the drain current is a function of vGS alone and does not depend on vDs. This is called the “active region” of the MOSFET.

•

In power electronic applications a MOSFET is operated in the “Cut Off” and Ohmic regions only.

•

The on state resistance of a MOSFET (VDS (ON)) has a positive temperature coefficient. Therefore, MOSFETs can be easily paralleled.

•

A MOSFET does not undergo second break down.

•

The safe operating area (SOA) of a MOSFET is similar to that of a BJT except that it does not have a second break down limit.

•

Unlike BJT the maximum forward voltage withstanding capability of a MOSFET does not depend on the drain current.

•

The safe operating area of a MOSFET does not change under Forward and Reverse bias conditions.

•

The drain – body junction in a MOSFET structure constitute an anti parallel diode connected between the source and the drain. This is called the MOSFET “body – diode.”

•

The body diode of a MOSFET has the same break down voltage and forward current rating as the main MOSFET.

•

The switching delays in a MOSFET are due to finite charging and discharging time of the input and output capacitors.

•

Switching times of a MOSFET can be controlled completely by external gate drive design.


•

The input capacitor along with the gate drive resistance determine the current rise and fall time of a MOSFET during switching.

•

The transfer capacitor (Cgd) determines the drain voltage rise and fall times.

•

rDS (ON) of a MOSFET determines the conduction loss during ON period.

•

rDS (ON) reduces with higher vgs. Therefore, to minimize conduction power loss maximum permissible vgs should be used subject to dielectric break down of the gate oxide layer.

•

The gate oxide layer can be damaged by static charge. Therefore MOSFETs should be handled only after discharging one self through proper grounding.

•

For similar voltage rating, a MOSFET has a relatively higher conduction loss and lower switching loss compared to a BJT. Therefore, MOSFETs are more popular for high frequency (>50 kHz) low voltage (> vGS g fs di Vgg ∴ D ≈ dt R g CGS ∴

∴ t ri = t fi ≈

Io R g CGS g fs Vgg

where Io = load current.

Now From equation (6.4) Vgg - Vg s , Io Vgg d v DS = ≈ dt R g CGD R g CGD


Since Vgg >> Vgs, Io V ∴ t rr = t fv ≈ D R g CGD where VD = Load voltage. Vgg

∴

I t ri t = fi = o t rr t fr VD

CG S g fs CG D

That is current rise and fall times are much shorter than voltage rise and fall times. 4. Referring to Fig 6.9 energy loss during switching occurs during intervals tri , tfv1, tfv2, trv2,trv1, and tfi. For simplicity it will be assumed that tfv2 = trv2 = 0. Also the rise and fall of iD and vDS will be assumed to be linear. During tri i D = g fs (vgs - vgs (th)) ∴

Vgg - v gs di D d = g fs v gs = g fs dt dt (CGS + CGD )R g

∴

g fs Vgg di D ≈ sinceVgg >> v gs during current rise dt (CGS + CGD )R g

Io (CGS + CGD )R g g fs Vgg Energy loss during tri is V I2 1 E ON1 = t ri VD Io = D o (CGS + CGD )R g 2 2g fs Vgg During tfv dVDS Vgg - Vgs, Io = dt CGD R g I But Vgs , Io = o + vgs (th) g fs I Vgg - v gs (th) - o dVDS g fs = ∴ dt R g CGD ∴ t ri =

∴ t fv =

VD Vgg - Vgs (th) -

Io

R g CGD g fs

Energy loss during tfv is E ON2 = 1 t fv Io VD 2 VD 2 Io = R g CGD I 2 ⎛⎜ Vgg - vgs (th) - o ⎞⎟ g fs ⎠ ⎝ ∴ Energy loss during Turn on is Version 2 EE IIT, Kharagpur 29

⎤ VD Io R g ⎡ Io ( CGS + CGD ) VD CGD + ⎢ ⎥ 2 ⎢ g fs Vgg V V (th) ( ) ⎥⎦ gg gs ⎣ From the symmetry of the Turn ON and the Turn OFF operation of MOSFET (i.e. tri = tfi, tfv = trv) E ON = E ON1 + E ON2 =

E ON = EOFF ∴ Total switching energy lass is Esw = EON + EOFF = 2 EON ⎡ ⎢ VD Vgg I g ⎛ C ⎞ ∴ E sw = VD Io R g CGD ⎢ o fs ⎜1+ GS ⎟ + ⎢ Vgg ⎝ CGD ⎠ Vgs (th) Io g fs ⎢ V Vgg gg ⎣

⎤ ⎥ ⎥ ⎥ ⎥ ⎦ ⎡ ⎤ ⎢ ⎥ VD Vgg ⎛ C ⎞I g ⎥ ∴ Psw E sw = VD Io R g CGD f sw ⎢⎜1+ GS ⎟ o fs + v gs (th) Io g fs ⎥ ⎢⎝ CGD ⎠ Vgg 1⎢ ⎥ Vgg v gg ⎦ ⎣ Substituting the values given Psw = 32 mw,



Lesson 7 Insulated Gate Bipolar Transistor (IGBT) Version 2 EE IIT, Kharagpur 2

Constructional features, operating principle and characteristics of Insulated Gate Bipolar Transistors (IGBT)

Instructional objects On completion the student will be able to •

Differentiate between the constructional features of an IGBT and a MOSFET.

•

Draw the operational equivalent circuit of an IGBT and explain its operating principle in terms of the schematic construction and the operational equivalent circuit.

•

Draw and explain the steady state output and transfer characteristics of an IGBT.

•

Draw the switching characteristics of an IGBT and identify its differences with that of a MOSFET.

•

Design a basic gate drive circuit for an IGBT.

•

Interpret the manufacturer’s date sheet of an IGBT.


7.1 Introduction The introduction of Power MOSFET was originally regarded as a major threat to the power bipolar transistor. However, initial claims of infinite current gain for the power MOSFETs were diluted by the need to design the gate drive circuit capable of supplying the charging and discharging current of the device input capacitance. This is especially true in high frequency circuits where the power MOSFET is particularly valuable due to its inherently high switching speed. On the other hand, MOSFETs have a higher on state resistance per unit area and consequently higher on state loss. This is particularly true for higher voltage devices (greater than about 500 volts) which restricted the use of MOSFETs to low voltage high frequency circuits (eg. SMPS). With the discovery that power MOSFETs were not in a strong position to displace the BJT, many researches began to look at the possibility of combining these technologies to achieve a hybrid device which has a high input impedance and a low on state resistance. The obvious first step was to drive an output npn BJT with an input MOSFET connected in the Darlington configuration. However, this approach required the use of a high voltage power MOSFET with considerable current carrying capacity (due to low current gain of the output transistor). Also, since no path for negative base current exists for the output transistor, its turn off time also tends to get somewhat larger. An alternative hybrid approach was investigated at GE Research center where a MOS gate structures was used to trigger the latch up of a four layer thyristor. However, this device was also not a true replacement of a BJT since gate control was lost once the thyristor latched up. After several such attempts it was concluded that for better results MOSFET and BJT technologies are to be integrated at the cell level. This was achieved by the GE Research Laboratory by the introduction of the device IGT and by the RCA research laboratory with the device COMFET. The IGT device has undergone many improvement cycles to result in the modern Insulated Gate Bipolar Transistor (IGBT). These devices have near ideal characteristics for high voltage (> 100V) medium frequency (< 20 kHZ) applications. This device along with the MOSFET (at low voltage high frequency applications) have the potential to replace the BJT completely.

7.2 Constructional Features of an IGBT Vertical cross section of a n channel IGBT cell is shown in Fig 7.1. Although p channel IGBTs are possible n channel devices are more common and will be the one discussed in this lesson.


Gate

Emitter SiO2 (Gate oxide)

+

n J3 J2 J1

-

n

p

SiO2 (Gate oxide) Body region Drain drift region Buffer layer Injecting layer

nn+ p+ Collector

Fig. 7.1: Vertical cross section of an IGBT cell. The major difference with the corresponding MOSFET cell structure lies in the addition of a p+ injecting layer. This layer forms a pn junction with the drain layer and injects minority carriers into it. The n type drain layer itself may have two different doping levels. The lightly doped nregion is called the drain drift region. Doping level and width of this layer sets the forward blocking voltage (determined by the reverse break down voltage of J2) of the device. However, it does not affect the on state voltage drop of the device due to conductivity modulation as discussed in connection with the power diode. This construction of the device is called “Punch Trough” (PT) design. The Non-Punch Through (NPT) construction does not have this added n+ buffer layer. The PT construction does offer lower on state voltage drop compared to the NPT construction particularly for lower voltage rated devices. However, it does so at the cost of lower reverse break down voltage for the device, since the reverse break down voltage of the junction J1 is small. The rest of the construction of the device is very similar to that of a vertical MOSFET (Link to 6.2) including the insulated gate structure and the shorted body (p type) – emitter (n+ type) structure. The doping level and physical geometry of the p type body region however, is considerably different from that of a MOSFET in order to defeat the latch up action of a parasitic thyristor embedded in the IGBT structure. A large number of basic cells as shown in Fig 7.1 are grown on a single silicon wafer and connected in parallel to form a complete IGBT device. The IGBT cell has a parasitic p-n-p-n thyristor structure embedded into it as shown in Fig 7.2(a). The constituent p-n-p transistor, n-p-n transistor and the driver MOSFET are shown by dotted lines in this figure. Important resistances in the current flow path are also indicated.


Gate Emitter n+

MOSFET

J3 p

n-p-n

Body spreading resistance

Drift resistance

n-

p-n-p

n+ p+

Gate

J1

Collector

(a) Drift region resistance

J2

Collector

Drift region resistance

Collector

Body spreading resistance Gate (b)

Emitter

Emitter (c)

Fig. 7.2: Parasitic thyristor in an IGBT cell. (a) Schematic structure (b) Exact equivalent circuit. (c) Approximate equivalent circuit Fig 7.2(b) shows the exact static equivalent circuit of the IGBT cell structure. The top p-n-p transistor is formed by the p+ injecting layer as the emitter, the n type drain layer as the base and the p type body layer as the collector. The lower n-p-n transistor has the n+ type source, the p type body and the n type drain as the emitter, base and collector respectively. The base of the lower n-p-n transistor is shorted to the emitter by the emitter metallization. However, due to imperfect shorting, the exact equivalent circuit of the IGBT includes the body spreading resistance between the base and the emitter of the lower n-p-n transistor. If the output current is large enough, the voltage drop across this resistance may forward bias the lower n-p-n transistor and initiate the latch up process of the p-n-p-n thyristor structure. Once this structure latches up the gate control of IGBT is lost and the device is destroyed due to excessive power loss. A major effort in the development of IGBT has been towards prevention of latch up of the parasitic thyristor. This has been achieved by modifying the doping level and physical geometry of the body region. The modern IGBT is latch-up proof for all practical purpose. Fig 7.3(a) and (b) shows the circuit symbol and photograph of an IGBT.


C

G E (a)

(b) Fig. 7.3: Circuit symbol of an IGBT. (a) Circuit symbol. (b) Photograph.

Exercise 7.1 Fill in the blank(s) with the appropriate word(s). i. An IGBT is a __________________ device combining the advantages of a __________________ and a __________________. ii. IGBT is suitable for __________________ voltage __________________ frequency applications. iii. In an IGBT cell structure a __________________ type injecting layer is added on top of the drain of an n channel MOSFET. iv. The forward blocking voltage of an IGBT is determined by the __________________ and __________________ of the drain drift layer. v. A “punch through” IGBT has __________________ reverse break down voltage while the “Non punch through” IGBT has __________________ voltage blocking capacity. vi. The IGBT cell has a parasitic __________________ structure embedded into it. vii. The parasitic __________________ structure of an IGBT cell can __________________ at large collector current due to imperfect body emitter shorting. viii. The doping level and physical geometry of the IGBT __________________ region is designed to be considerably different from that of a MOSFET to prevent its __________________. Answers: i) hybrid, MOSFET, BJT ; ii) high, medium ; iii) p+ ; iv) thickness, doping level ; v) low, symmetrical ; vi) thyristor; vii) thryistor, latch up ; viii) body, latch up.

7.3 Operating principle of an IGBT Operating principle of an IGBT can be explained in terms of the schematic cell structure and equivalent circuit of Fig 7.2(a) and (c). From the input side the IGBT behaves essentially as a Version 2 EE IIT, Kharagpur 7

MOSFET. Therefore, when the gate emitter voltage is less then the threshold voltage no inversion layer is formed in the p type body region and the device is in the off state. The forward voltage applied between the collector and the emitter drops almost entirely across the junction J2. Very small leakage current flows through the device under this condition. In terms of the equivalent current of Fig 7.2(c), when the gate emitter voltage is lower than the threshold voltage the driving MOSFET of the Darlington configuration remains off and hence the output p-n-p transistor also remains off. When the gate emitter voltage exceeds the threshold, an inversion layer forms in the p type body region under the gate. This inversion layer (channel) shorts the emitter and the drain drift layer and an electron current flows from the emitter through this channel to the drain drift region. This in turn causes substantial hole injection from the p+ type collector to the drain drift region. A portion of these holes recombine with the electrons arriving at the drain drift region through the channel. The rest of the holes cross the drift region to reach the p type body where they are collected by the source metallization. From the above discussion it is clear that the n type drain drift region acts as the base of the output p-n-p transistor. The doping level and the thickness of this layer determines the current gain “∝” of the p-n-p transistor. This is intentionally kept low so that most of the device current flows through the MOSFET and not the output p-n-p transistor collector. This helps to reduced the voltage drop across the “body” spreading resistance shown in Fig 7.2 (b) and eliminate the possibility of static latch up of the IGBT. The total on state voltage drop across a conducting IGBT has three components. The voltage drop across J1 follows the usual exponential law of a pn junction. The next component of the voltage drop is due to the drain drift region resistance. This component in an IGBT is considerably lower compared to a MOSFET due to strong conductivity modulation by the injected minority carriers from the collector. This is the main reason for reduced voltage drop across an IGBT compared to an equivalent MOSFET. The last component of the voltage drop across an IGBT is due to the channel resistance and its magnitude is equal to that of a comparable MOSFET.

7.4 Steady state characteristics of an IGBT The i-v characteristics of an n channel IGBT is shown in Fig 7.4 (a). They appear qualitatively similar to those of a logic level BJT except that the controlling parameter is not a base current but the gate-emitter voltage.


iC

VCC

G VgE

RL ic + C VcE E -

Increasing Saturation V VgE6 gE VCC Active RL VgE5 Load line A VgE4

iC F Fault Load line

VgE3 B

VgE2

gfs

VgE1 VRM

Cut off

(a)

C VCC VCES VCE

VgE (th)

VgE

(b)

Fig. 7.4: Static characteristics of an IGBT (a) Output characteristics; (b) Transfer characteristics When the gate emitter voltage is below the threshold voltage only a very small leakage current flows though the device while the collector – emitter voltage almost equals the supply voltage (point C in Fig 7.4(a)). The device, under this condition is said to be operating in the cut off region. The maximum forward voltage the device can withstand in this mode (marked VCES in Fig 7.4 (a)) is determined by the avalanche break down voltage of the body – drain p-n junction. Unlike a BJT, however, this break down voltage is independent of the collector current as shown in Fig 7.4(a). IGBTs of Non-punch through design can block a maximum reverse voltage (VRM) equal to VCES in the cut off mode. However, for Punch Through IGBTs VRM is negligible (only a few tens of volts) due the presence of the heavily doped n+ drain buffer layer. As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into the active region of operation. In this mode, the collector current ic is determined by the transfer characteristics of the device as shown in Fig 7.4(b). This characteristic is qualitatively similar to that of a power MOSFET and is reasonably linear over most of the collector current range. The ratio of ic to (VgE – vgE(th)) is called the forward transconductance (gfs) of the device and is an important parameter in the gate drive circuit design. The collector emitter voltage, on the other hand, is determined by the external load line ABC as shown in Fig 7.4(a). As the gate emitter voltage is increased further ic also increases and for a given load resistance (RL) vCE decreases. At one point vCE becomes less than vgE – vgE(th). Under this condition the driving MOSFET part of the IGBT (Fig 7.2(c)) enters into the ohmic region and drives the output p-n-p transistor to saturation. Under this condition the device is said to be in the saturation mode. In the saturation mode the voltage drop across the IGBT remains almost constant reducing only slightly with increasing vgE. In power electronic applications an IGBT is operated either in the cut off or in the saturation region of the output characteristics. Since vCE decreases with increasing vgE, it is desirable to use the maximum permissible value of vgE in the ON state of the device. vgE(Max) is limited by the maximum collector current that should be permitted to flow in the IGBT as dictated by the “latch-up” condition discussed earlier. Limiting VgE also helps to limit the fault current through Version 2 EE IIT, Kharagpur 9

the device. If a short circuit fault occurs in the load resistance RL (shown in the inset of Fig 7.4(a)) the fault load line is given by CF. Limiting vgE to vgE6 restricts the fault current corresponding to the operating point F. Most IGBTs are designed to with stand this fault current for a few microseconds within which the device must be turned off to prevent destruction of the device. It is interesting to note that an IGBT does not exibit a BJT-like second break down failure. Since, in an IGBT most of the collector current flows through the drive MOSFET with positive temperature coefficient the effective temperature coefficient of vCE in an IGBT is slightly positive. This helps to prevent second break down failure of the device and also facilitates paralleling of IGBTs. Exercise 7.2

Fill in the blank(s) with the appropriate word(s). i. From the input side the IGBT behaves essentially as a __________________. ii. When the gate emitter voltage is below __________________ no __________________ layer is formed in the p type body region. iii. Electrons arriving through the drive MOSFET causes __________________ injection from the __________________ to the drain drift region. iv. In an IGBT most of the collector current flows through the __________________ and not through the __________________. v. When the gate-emitter voltage of an IGBT is below threshold if operates in the __________________ region. vi. In the active region of operation the collector current of an IGBT is determined by the __________________ characteristics which is reasonably __________________ over most of the collector current range. vii. For the same load resistance as the vgE of an IGBT is increased it enters __________________ region. viii. The forward voltage drop of an IGBT in the saturation region remains approximately __________________. ix. An IGBT has small __________________ temperature coefficient of on state voltage drop. x. An IGBT does not exhibit __________________ failure mode. Answers: i) MOSFET; ii) threshold, inversion; iii) hole, collector; iv) MOSFET, BJT; v) cut-off; vi) transfer, linear; vii)saturation; viii) constant; ix) positive; x) second break down.


7.5 Switching characteristics of IGBT Switching characteristics of the IGBT will be analyzed with respect to the clamped inductive switching circuit shown in Fig 7.5(a). The equivalent circuit of the IGBT shown in Fig 7.5 (b) will be used to explain the switching waveforms. VCC C iL

iD DF

iC Rg ig

G Q1

C

+ VCE

E

D CGD G

S

CgE

E

-

Vgg

(b) (a) Fig. 7.5: Inductive switching circuit using an IGBT (a) Switching circuit; (b) Equivalent circuit of the IGBT

The switching waveforms of an IGBT is, in many respects, similar to that of a Power MOSFET. This is expected, since the input stage of an IGBT is a MOSFET as shown in Fig 7.5(b). Also in a modern IGBT a major portion of the total device current flows through the MOSFET. Therefore, the switching voltage and current waveforms exhibit a strong similarity with those of a MOSFET. However, the output p-n-p transistor does have a significant effect on the switching characteristics of the device, particularly during turn off. Another important difference is in the gate drive requirement. To avoid dynamic latch up, (to be discussed later) the gate emitter voltage of an IGBT is maintained at a negative value when the device is off.


Vgg

∫∫ τ2 = Rg(CGS+CGD2)

VgE(th)

VgE

VgE(th)

VgE,IL

VgE,IL t

∫∫

τ1 = Rg(CGS+CGD1) VCE

VCE(sat)

VCC

VCC t

∫∫ ∫∫

iC iD

IL

IL

tdON tri tfv1

IL tfv2

∫∫

trv1

trv2

IL

tfi1

tfi2

t

Fig. 7.6: Switching waveforms of an IGBT.

The switching waveforms of an IGBT is shown in Fig 7.6. Similarity of these waveforms with those of a MOSFET is obvious. To turn on the IGBT the gate drive voltage changes from –Vgg to +Vgg. The gate emitter voltage vgE follows Vgg with a time constant τ1. Since the drain source voltage of the drive MOSFET is large the gate drain capacitor assumes the lower value CGD1. The collector current ic does not start increasing till vgE reaches the threshold voltage vgE(th). Thereafter, ic increases following the transfer characteristics of the device till vgE reaches a value vgEIL corresponding to ic = iL. This period is called the current rise time tri. The free wheeling diode current falls from IL to zero during this period. After ic reaches IL, vgE becomes clamped at vgE IL similar to a MOSFET. vCE also starts falling during this period. First vCE falls rapidly (tfv1) and afterwards the fall of vCE slows down considerably. Two factors contribute to the slowing down of voltage fall. First the gate-drain capacitance Cgd will increase in the MOSFET portion of the IGBT at low drain-source voltages. Second, the pnp transistor portion of the IGBT traverses the active region to its on state more slowly than the MOSFET portion of the IGBT. Once the pnp transistor is fully on after tfv2, the on state voltage of the device settles down to vCE(sat). The turn ON process ends here. The turn off process of an IGBT follows the inverse sequence of turn ON with one major difference. Once vgE goes below vgE(th) the drive MOSFET of the IGBT equivalent circuit turns off. During this period (tfi1) the device current falls rapidly. However, when the drive MOSFET turns off, some amount of current continues of flow through the output p-n-p transistor due to stored charge in its base. Since there is no reverse voltage applied to the IGBT terminals that could generate a negative drain current, there is no possibility for removing the stored charge by carrier sweep-out. The only way these excess carriers can be removed is by recombination within the IGBT. During this recombination period (tfi2) the remaining current in the IGBT decays relatively slowly forming a current fail. A long tfi2 is undesirable, because the power dissipation Version 2 EE IIT, Kharagpur 12

in this interval will be large due to full collector-emitter voltage. tfi2 can be reduced by decreasing the excess carrier life time in the p-n-p transistor base. However, in the process, on state losses will increase. Therefore, judicious design trade offs are made in a practical IGBT to give minimum total loss. The gate drive circuit of an IGBT should ensure fast and reliable switching of the device. In particular, it should. •

Apply maximum permissible VgE during ON period.

•

Apply a negative voltage during off period.

• •

Control dic dt during turn ON and turn off to avoid excessive Electro magnetic interference (EMI). Control dvce dt during switching to avoid IGBT latch up.

•

Minimize switching loss.

•

Provide protection against short circuit fault.

Detailed discussion on IGBT gate drive circuit is beyond the scope of this lesson. References [4] & [5] provide good discussion on this subject. Fig 7.7(a) shows a simplified IGBT gate drive circuit. +Vcc RC +Vgg Ri -

Vi

+

(Logic level) Opto isolator

R Vgg

Q1

RB

R

G

IGBT

Q2 E

Level Shifting -Vgg Comparator RB β1 +1

-Vcc

(a) R G

To IGBT Gate

-Vgg

Totem pole gate drive amplifier

RB β2 +1

G

To IGBT Gate

E

E

Turn on equivalent circuit

Turn off equivalent circuit

(b) Fig. 7.7: IGBT gate drive circuit (a) Gate drive (b) Equivalent circuit of the gate drive during turn on and turn off.


The logic level gate drive signal is first opto-isolated and fed to a level shifting comparator. This stage converts the unipolar (usually positive) out put voltage of the opto-isolator to a bipolar (±Vgg) signal compatible to the IGBT gate drive levels. The output of the comparator feeds a totem pole output amplifier stage which drives the IGBT. The equivalent circuit of the gate drive during turn on and off are shown in Fig 7.7(b). If VCC > Vgg then both Q1 and Q2 will operate in the active region and reasonably constant value of β1 & β2 of these two transistors can be used for analysis purpose. These equivalent circuits along with the model of the IGBT input MOSFET can be used to analyze the switching performance of the device. Conversely, for a desired switching performance a suitable gate drive circuit can be designed.

7.6 IGBT ratings and safe operating area Maximum collector-emitter voltage (VCES): This rating should not be exceeded even on instantaneous basis in order to prevent avalanche break down of the drain-body p-n junction. This is specified at a given negative gate emitter voltage or a specified resistance connected between the gate and the emitter. Maximum continuous collector current (IC): This is the maximum current the IGBT can handle on a continuous basis during ON condition. It is specified at a given case temperature with derating curves provided for other case temperatures. Maximum pulsed collector current (ICM): This is the maximum collector current that can flow for a specified pulse duration. This current is limited by specifying a maximum gate-emitter voltage. Maximum gate-emitter voltage (VgES): This is the maximum allowable magnitude of the gateemitter voltage (of both positive and negative polarity) in order to •

Prevent break down of the gate oxide insulation.

•

Restrict collector current to ICM.

Collector leakage current (ICES): This is the leakage collector current during off state of the device at a given junction temperature. This is usually specified at VgE = 0V and vCE = VCES. Gate-emitter leakage current (IGES): Usually specified at vCE = 0V & vgE = vgES. Collector emitter saturation voltage (VCE(sat)): This is specified at a given junction temperature, gate-emitter voltage and collector current. For more detailed data the output characteristics of the device for different vgE and expanded near the saturation zone is also provided. Gate-emitter threshold voltage (vgE(th)): It is specified at a low collector emitter voltage and collector current. Forward Transconductance (gfs): This is again specified at a low value of vCE. For more detailed data the transfer characteristics of the device (ic vs vgE) is also provided.


Input, output and transfer capacitances (Cies, Coes & Cres): These are, gate-emitter, collectoremitter and gate-drain capacitances of the device respectively, specified at a given collectoremitter voltage. Variation of these parameters as functions of vCE are also supplied. Switching times (td(ON) tri, tfv, trv, tfi): These times are specified for inductive load switching as functions of gate charging resistance and collector current. In addition turn on and turn off energy losses per switching operation are also specified. Maximum total power dissipation (Ptmax): This is the maximum allowable power lass in the device (both switching and conduction) on a continuous basis at a given case temperature. Derating curve at other temperatures are also specified.

The IGBT has robust SOA both during turn on and turn off. Fig 7.8 (a) shows the FBSOA. On the left side it is restricted by the forward voltage drop characteristics. Up to maximum continuous collector current this voltage remains reasonably constant at a low value. However, at ICM this voltage starts increasing as the IGBT starts entering active region. On the top the FBSOA is restricted by ICM. iC

iC

ICM IC

10-5sec 10-4sec 10-3sec 10-2sec DC

(a)

VCES VCE

ICM

1000V/μS 2000V/μS 3000V/μS

(b)

VCES

VCE

Fig. 7.8: Safe operating area of an IGBT (a) FBSOA; (b) RBSOA.

The other two limits are formed by the maximum power dissipation limit and the maximum forward voltage limit. Like other devices the maximum power dissipation limit increases with reduction in the on pulse width. The RBSOA for low values of dvCE dt is rectangular. However, for increased dvCE dt the upper-right hand corner is progressively cut out. The reason for this restriction on the RBSOA is to avoid dynamic latch up. The device user can easily control dvCE dt by proper choice of Vgg and the gate drive resistance. Exercise 7.3


In a modern IGBT most of the collector current flows through the _________________ and not the _________________. Version 2 EE IIT, Kharagpur 15

ii.

To avoid _________________ the gate emitter voltage of an IGBT is maintained at a _________________ value when the device is off.

iii.

During turn on of an IGBT the rate of fall of voltage slows down towords the end since the output p-n-p transistor traverses its _________________ region more _________________ compared to the drive MOSFET.

iv.

During turn off of an IGBT a _________________ is formed due to excess stored charge in the _________________ region of the output p-n-p transistor.

v.

The gate drive circuit of an IGBT should control _________________.

dic

dt

to avoid excessive

dvCE dt

vi.

of an IGBT during turn off should be controlled to prevent _________________ of the device.

vii.

A specified maximum gate emitter voltage of an IGBT helps to limit the collector current during _________________ fault.

viii.

Collector emitter saturation voltage of an IGBT _________________ with increasing gate-emitter voltage.

ix.

The FBSOA of an IGBT is similar to that of a _________________ except that the on state voltage drop is much _________________.

x.

The upper right hand corner of the IGBT RBSOA is gradually cut out with increasing _________________ to avoid _________________ of the device.

Answer: (i) MOSFET, BJT; (ii) latch up, negative; (iii) active, slowly; (iv) current tail, base; (v) EMI; (vi) Latch up; (vii) short circuit; (viii) decreases; (ix) MOSFET, lower; (x) dvCE dt , latch up.

Reference [1]

B. Jayanta Baliga, “Evolution of MOS Bipolar Power Semiconductor Technology”, Proceedings of the IEEE, vol. 76, No. 4, April 1988, pp 409-418.

[2]

“Power electronics, Converters, Applications and Design”, Mohan, Undeland, Robbins; John Wiley & Sons, 2003

[3]

B. Jayanta Baliga et. al, “The Insulated Gate Transistor: A new Three-Terminal MOSControlled Bipolar. Power Device”, IEEE transaction on Electron Devices, vol. ED-31, No. 6 June 1984 pp 421-828.

[4]

Allen R. Hefner, “An Investigation of the drive circuit requirements for the Power Insulated Gate Bipolar Transistor”, IEEE Transactions on Power Electronics. Vol. 6 No. 2. April 1991.


[5]

Carmelo Licitra et. al, “A New Driving circuit for IGBT Devices”, IEEE Transaction on Power Electronics, Vol. 10, No-3 may 1995.

[6]

“SEMIKRON Power Electronics News 2001”, SEMIKRON International, Germany.

Lesson Summary •

IGBT is a hybrid device which combines the advantages of MOSFET and BJT.

•

An IGBT is formed by adding a p+ collector layer on the drain drift layer of a Power MOSFET.

•

Punch through IGBT has a thin n+ buffer layer between the p+ collector layer and ndrain drift layer. They have significantly lower conduction loss.

•

The IGBT cell structure embeds a parasitic thyristor in it. Latching up of this thyristor is prevented by special structuring of the body region and increasing the effectiveness of the body shorting.

•

From the operational point of view an IGBT is a voltage controlled bipolar device.

•

The operational equivalent circuit of an IGBT has an n channel MOSFET driving a p-n-p BJT.

•

Like other semiconductor devices on IGBT can also operate in the cut off active and saturation regions.

•

When the gate-emitter voltage of an IGBT is below threshold it operates in the cut off region.

•

For a given load resistance the operating point of an IGBT can be moved from cut off to saturation through the active region by increasing the gate-emitter voltage.

•

In the active region, the collector current of an IGBT is determined by the gate-emitter voltage which can be limited to a given maximum value to limit the fault current through the device in the event of a load short circuit.

•

The IGBTs have a slightly positive temperature coefficient of the on-state voltage drop which makes paralleling of these devices simpler.

•

An IGBT does not exhibit second break down phenomena as in the case of a BJT.

•

The switching characteristics of an IGBT is similar to that of a MOSFET.

•

To avoid dynamic latch up of the parasitic thryrstor in an IGBT, the gate emitter voltage of the device is maintained at a negative value during it’s off period.

•

During turn off, the collector current of an IGBT can exhibit “current tailing” due to stored base change in the base region of the output p-n-p transistor.

•

The forward bias SOA of an IGBT is similar to that of a MOSFET except the on state voltage drop being much lower.

•

The maximum allowable collector current in an IGBT is restricted by the static latch up consideration. Version 2 EE IIT, Kharagpur 17

dv

•

The RBSOA of an IGBT is rectangular for low values of dtCE . For higher dvCE dt the upper right half corner of the RBSOA is progressively cut-out to prevent “dynamic latch up of the device”.

•

The IGBT can switch at moderately high frequency (> vgE Also since Vcc > Vgg, Q1 & Q2 operates in the active region. Substituting the given values


dic 40 × 15 = = 1.82 × 109 A/Sec -12 2200 dt 4500 × 10 × ( 30 + 51 ) dic Since β1 = β2 , during turn off will also have the same value dt dic = 1.82 A/ns So dt Since load current is 50 Amps and gfs = 40

vge IL = vgE (th) +

Daring turn on CgD

∴

IL = 5.25 volts gfs

V - v IL dvCE = ig IL = gg gE RB dt R + β+1

dvCE during turn ON is dt Vgg - vgE IL dvCE 15 - 5.25 = = RB dt 500 × 10-12 ( 30 + 2200 CgD R + β +1 51 )

(

1

)

= 2.67 × 108 V/Sec

Since Vgg+ =Vgg- and β1 = β2 dvCE during turn off will be same dt So

dvCE = 2.67 × 108 V/Sec or 267 V/μs. dt


Module 1 Power Semiconductor Devices Version 2 EE IIT, Kharagpur

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Lesson 8 Hard and Soft Switching of Power Semiconductors Version 2 EE IIT, Kharagpur

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This lesson provides the reader the following (i)

To highlight the issues related to device stresses under Hard switching;

(ii)

To suggest means of reducing such stresses with external circuitry;

(iii)

To propose alternative switching methods for stress reduction;

(iv)

Enable the choice of the appropriate switching strategy

Soft and Hard Switching Semiconductors utilised in Static Power Converters operate in the switching mode to maximise efficiency. Switching frequencies vary from 50 Hz in a SCR based AC-DC Phase Angle Controller to over 1.0 MHz in a MOSFET based power supply. The switching or dynamic behaviour of Power Semiconductor devices thus attracts attention specially for the faster ones for a number of reasons: optimum drive, power dissipation, EMI/RFI issues and switching-aidnetworks. With SCRs’ 'forced commutation' and 'natural (line) commutation' usually described the type of switching. Both refer to the turn-off mechanism of the SCR, the turn-on dynamics being inconsequential for most purposes. A protective inductive snubber to limit the turn-on di/dt is usually utilised. For the SCRs’ the turn-off data helps to dimension the 'commutation components' or to set the 'margin angle'. Conduction losses account for the most significant part of total losses. Present day fast converters operate at much higher switching frequencies chiefly to reduce weight and size of the filter components. As a consequence, switching losses now tend to predominate, causing the junction temperatures to rise. Special techniques are employed to obtain clean turn-on and turn-off of the devices. This, along with optimal control strategies and improved evacuation of the heat generated, permit utilisation of the devices with a minimum of deration. This chapter first examines the switching process, estimates the device dissipation and indicates design procedures for the cooling system.

Losses in Power Semiconductors A converter consists of a few controlled and a few uncontrolled devices (diodes). While the first device is driven to turn-on or off, the uncontrolled device operates mainly as a slave to the former. Power loss in the converter is the aggregate of these losses. Occasionally the diode and the controlled device are housed in the same module. The losses corresponding to each contribute to the temperature rise of the integrated module.

Version 2 EE IIT, Kharagpur

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The losses can be segregated as follows: Total module dissipation

Controlled device losses conduction

Diode losses

switching

Turn-off

conduction

Turn-off

Turn-off

switching Turn-on

Conduction Losses Conduction losses are caused by the forward voltage drop when the power semiconductor is on and can be described by (with reference to an IGBT)

Fig. 3.1 Approximate forward voltage of IGBT and diode WC = Vce (sat)(Ic).Ic where Ic is the current carried by the device and Vce(sat)(Ic) is the current dependant forward voltage drop. This drop may be expressed as Vce (sat) (Ic) = V0 + R . Ic This relation defines the forward drop of an IGBT in a similar manner to a diode. A part of the drop is constant while another part is collector current dependent. The given data should be used as follows: Using the numerical value is the most simple way to determine conduction losses. The numerical value can be applied if the current in the device is equal or close to the specified current - data sheet numerical values are specified for typical application currents. The graph most accurately determines conduction losses. The conditions in which the data are used should correspond to the application. To estimate if a power semiconductor rating is appropriate, usually the values valid for elevated temperature, close to the maximum junction temperature TJmax , should be used to calculate power losses because this is commonly the operating point at nominal load. Version 2 EE IIT, Kharagpur

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Blocking Losses Blocking losses are generated by a low leakage current through the device with a high blocking voltage. WB = Vb(I).IL Where IL is the leakage current and Vb(I) is the current dependemt blocking voltage. Data sheets indicates leakage current at certain blocking voltage and temperature. The dependence between leakage current and applied voltage typically is exponential; this means that using a data sheet value given for a blocking voltage higher than applied overestimates blocking losses. However in general, blocking losses are small and can often, but not always, be neglected.

Switching Losses IGBTs are designed for use in switching converters and not for linear operation. This means switching time intervals are short compared to the pulse duration at typical switching frequencies, as can be seen from their switching times, such as rise time tr and fall time tf in the data sheets. Switching losses occur during these switching intervals.

Fig. 3.2 Switching losses (appx) For IGBTs they are specified as an amount of energy, Eon/off for a certain switching operation. Eon/off are the energy dissipated at turn-on/turn-off respectively. Using the numerical value is again the most simple way to determine switching losses. The numerical value can be applied if the switching operations are carried out at the same or similar conditions as indicated in the data sheet. Graphs for Eon(IC)/(RG ), Eoff (IC)/(RG) with collector current IC and gate resistance RG are provided. The graphs permit the most accurate determination of switching losses, given the parameters of the converter: RG and converter current IC.


5

Diode A surge voltage occurs when the free-wheel diode recovers. Consider a converter leg. The lower device is off and that the load current is circulating through the free-wheeling diode of the upper device. Now if the lower device turns on, the current in the free-wheel diode of the upper device decreases during the overlap period and the load current begins to commutate to the lower device. It becomes negative during reverse recovery of the upper free-wheel diode. When the free-wheel diode recovers, the current in the circuit associated to the diode jumps to zero. The parasitic line inductance Lp develops a surge voltage equal to Lp di/dt in opposition to the decreasing current. This di/dt is dictated by the recovery characteristic of the free-wheel diode. Fast recovery “snappy” diodes can develop very high recovery di/dt when they are hard recovered by the rapid turn-on of a device in series with it in the same converter leg. These diodes take a smaller time to quench the reverse recovery current compared to a soft recovery diode. The off-state losses of the main device and the turn-on dissipation may be neglected for most cases. With an IGBT driven DC-DC chopper as an example, the dissipation can be estimated as: IGBT dissipation = Conduction losses + Switching losses = [ .Vce(sat)Ic] +[fc(Eon + Eoff)] Watts Diode dissipation = Conduction losses + Reverse recovery losses = [ (1 -  FVF]+ [fc Err] where, is the conduction duty ratio, fc the switching frequency and Eon , Eoff , Err are the respective energy losses, Fig 3.2, data for which is provided by the device manufacturer. The values of Eon , Eoff , Err are at the rated values only and have to be adjusted to the working values of voltage (DC bus), VCE (working) and load current, Ic.

Eon / Eoff / Err ( working ) = Eon / Eoff / Err ( working ) • ⎡⎣VCE ( working ) / VCE ( rated ) ⎤⎦

Eon / Eoff / Err ( working ) = Eon / Eoff / Err ⎡⎣ I C / I C ( rated ) ⎤⎦

a/b/c

Where, a, b and c are constants. The power device in a converter mostly sees an inductive load. A simple circuit illustrating such a situation is shown in Fig. 3.3. Corresponding ideal waveforms are also indicated. The freewheeling diode FWD, across the load is essential for clamping the induced voltages across the inductance when the device switches off. However, its presence causes the supply voltage, Vs to appear across the transistor whenever it carries part of the inductor current in overlap mode with the FWD during both turn-on and turn-off modes. This causes the transistor switching dissipation to increase.


6

Fig. 3.3 Typical current and voltage transients during turn-on and turnoff of a clamped-inductive load and transitions in the V-I plane. An RCD Switching-aid-network connected across the device reduces turn-off dissipation, Fig. 3.2. The controlled rise of the collector voltage of the transistor aids this process. However, turnoff energy is accumulated in the SAN, which is ultimately dissipated in the resistor. The RCD does not also help reduce turn-on dissipation when the reverse recovery current of the diode and the SAN current add up with the load current with Vs again appearing across the device. Example 3.1 Derive the expression for the power dissipation during turn-on and turn-off of a transistor unassisted by a SAN. The supply voltage is Vm, peak load current Im, and tr, toff being the turn on and turn-off times. Assume idealised waveforms. Solution The transition of the swichings in the VC - IC plane is rectangular. The energy dissipated in each turn-off switching cycle is t off 1 W = ∫ VT . I T dt = .V .I .t 0 T 2 M M f

If actual waveforms are considered the dissipation is close to about double the above figure. The dissipation at turn-on is, similarly 1/2. VM.I M.ton.


7

Fig. 3.4 Current and voltage waveforms at the Main Terminals of the switch with an R-C-D SAN, and in the associated FWD and SAN diode Example 3.2

For a transistor carrying a collector current IM and having a turn--off time tf, find the details of a RCD SAN to restrict the voltage rise at the end of tf to half the supply voltage. Calculate the corresponding losses in the transistor and in the SAN. Solution

The action of the SAN in restricting the rise of transistor voltage till the current in it is extinguished is illustrated in Fig. 3.4. Since the current is assumed to fall linearly during the period tf, the collector voltage rises as: 2

2

⎛ t ⎞ I .t ⎛ t ⎞ V = V0 ⎜ ⎟ = M f ⎜ ⎟ ⎜t ⎟ 2C ⎜⎝ t f ⎟⎠ ⎝ f ⎠ Where V0 is the voltage at the capacitor at the end of turn-off time tf. Thus,

V0 =

IM t f

2C ⎛ t i = I M ⎜1 − ⎜ t f ⎝ The Transistor current can be written as: The dissipation in the transistor is tf

tf

0

0

WT = ∫ v.idt = ∫

I M2 .t f ⎛ t ⎜⎜1 − 2C ⎝ t f

⎞ ⎟ ⎟ ⎠

⎞⎛ t ⎟⎟ ⎜⎜ ⎠⎝ tf

2

⎞ I M2 .t 2f 1 . Watts ⎟⎟ dt = 2C 12 ⎠

When the transistor switches off, the nearly constant load current linearly charges up the capacitor till it reaches the supply voltage. Subsequently, The FWD is positively biased and there Version 2 EE IIT, Kharagpur

8

is a short period of over-lap between the FWD and the SAN diode. During this period, the capacitor over-charges to some extent. If V0 is the capacitor voltage when the transistor current is extinguished, t2

CV0 = ∫ i.dt = t1

1 IMt f 2

If this V0 is about 1/2 Vs, C≥

IM t f Vs

The energy dissipated in the SAN resistor which is also the energy shifted to the SAN from the transistor during turn-off is 1 CVM2 F 2 Where F is the switching frequency. The resistance should be able to limit the transistor current to its peak rating. Thus, PR =

R≥

I CM

Vs − I M − I rr

Irr is the reverse recovery current of the FWD. If the capacitor has to discharge completely during the ON time, C≥

I M .t f Vs − R.I M

In a Sine-PWM controlled converter with a peak value of the fundamental current equal to Icp, the conduction losses in the IGBT would be π

Wc = δ .T ∫ I cVce ( sat ) dθ 0

⎡2 2 ⎤ = 12 δ .T ⎢ I cpVo + I cp2 .R ⎥ ⎣ π ⎦

Where Vo and R are as shown in Fig 3.1. For the diode the dissipation is WF =

1 [1 − δ ]. 2 2 I cpVod + I cp2 Rd π 2


9

Soft switching

Fig. 3.5 Basic topologies for a) Hard switch, b) Zero-voltage switch and c) for a Zero current switch

Hard switching and its consequences have been discussed above. Reduction of size and weight of converter systems require higher operating frequencies, which would reduce sizes of inductors and capacitors. However, stresses on devices are heavily influenced by the switching frequencies accompanied by their switching losses. It is obvious that switching-aid-networks do not mitigate the dissipation issues to a great extent. Turn-on snubbers though not discussed, are rarely used. Even if used, it would not be able to prevent the energy stored in the junction capacitance to discharge into the transistor at each turn-on. Soft switching techniques use resonant techniques to switch ON at zero voltage and to switch OFF at zero current. There are negligible switching losses in the devices, though there is a significant rise in conduction losses. There is no transfer of dissipation to the resonant network which is non-dissipative. The two basic configurations are as shown in Fig. 3.5.


Fig. 3.6 Switching loci for a Hard-Switched converter without Switching-Aid-Networks,

with the SAN and for a Soft-Switched converter operation

The switching trajectory in the voltage-current plane of a device is illustrated in Fig. 3.6 comparing the paths for that of a Hard-switched operation without any SAN, a Hard-switched with a R-C-D Switching-Aid-Network and a resonant converter. It is indicatve of the stresses and losses. A designer would prefer the path to be as close as possible to the origin. A Zero Current Switch based converter is provided as illustration to the soft switching mechanism. It is equivalent to the topology shown above. The input capacitor and the one across the diode may be combined to arrive at this topology.

Fig. 3.7 A ZCS resonant buck converter

The ZCS converter is considered to be in stable operation with Load current Itrans flowing through the diode and the inductor Lf. The Capacitor Cr is charged to Vs. On switching the transistor ON the current in it ramps up from zero but the diode continues conduction till this current reaches the load current Iout level. Subsequently, the load current and the resonating current flows through the transistor. This current reaches a natural zero when the negative magnitude of the resonating current equals the load current. The transistor thus switches in the Zero Current mode for both turn on and turn off. The diode, on the other hand switches in the Zero Voltage mode under both situations. It must be noted that the peak current stress on the transistor is high . The peak voltage stress on the diode is also about twice the supply voltage. Both these stresses are significantly higher than that in a comparable Hard switched buck converter. Consequently, Version 2 EE IIT, Kharagpur 11

while switching losses are practically eliminated in this resonant converter, conduction losses increase along with the device stresses. There is no scope of a SANs in resonant switching.

Objective type questions Qs#1 Which component of power dissipation in a Power Semiconductor device is reduced by an RCD Switching –Aid –Network?

a) b) c) d) Ans:

Off state losses Turn-on losses Turn-off losses On-state losses

c) turn-off losses

Qs#2 Does an RCD SAN reduce total switching losses? Ans:

No. It transfers the losses from the device to itself.

Qs#3 Are resonant converters superior to the hard switched converter on all counts? Ans:

No. The resonant converter reduces switching losses at the cost of higher voltage/current stresses on the devices.



Lesson 9 Single Phase Uncontrolled Rectifier Version 2 EE IIT, Kharagpur 2

Operation and Analysis of single phase uncontrolled rectifiers


Classify the rectifiers based on their number of phases and the type of devices used.

•

Define and calculate the characteristic parameters of the voltage and current waveforms.

•

Analyze the operation of single phase uncontrolled half wave and full wave rectifiers supplying resistive, inductive, capacitive and back emf type loads.

•

Calculate the characteristic parameters of the input/output voltage/current waveforms associated with single phase uncontrolled rectifiers.


9.1 Introduction One of the first and most widely used application of power electronic devices have been in rectification. Rectification refers to the process of converting an ac voltage or current source to dc voltage and current. Rectifiers specially refer to power electronic converters where the electrical power flows from the ac side to the dc side. In many situations the same converter circuit may carry electrical power from the dc side to the ac side where upon they are referred to as inverters. In this lesson and subsequent ones the working principle and analysis of several commonly used rectifier circuits supplying different types of loads (resistive, inductive, capacitive, back emf type) will be presented. Points of interest in the analysis will be. • • • • • •

Waveforms and characteristic values (average, RMS etc) of the rectified voltage and current. Influence of the load type on the rectified voltage and current. Harmonic content in the output. Voltage and current ratings of the power electronic devices used in the rectifier circuit. Reaction of the rectifier circuit upon the ac network, reactive power requirement, power factor, harmonics etc. Rectifier control aspects (for controlled rectifiers only)

In the analysis, following simplifying assumptions will be made. • •

The internal impedance of the ac source is zero. Power electronic devices used in the rectifier are ideal switches.

The first assumption will be relaxed in a latter module. However, unless specified otherwise, the second assumption will remain in force. Rectifiers are used in a large variety of configurations and a method of classifying them into certain categories (based on common characteristics) will certainly help one to gain significant insight into their operation. Unfortunately, no consensus exists among experts regarding the criteria to be used for such classification. For the purpose of this lesson (and subsequent lessons) the classification shown in Fig 9.1 will be followed.


This Lesson will be concerned with single phase uncontrolled rectifiers.

9.2 Terminologies Certain terms will be frequently used in this lesson and subsequent lessons while characterizing different types of rectifiers. Such commonly used terms are defined in this section. Let “f” be the instantaneous value of any voltage or current associated with a rectifier circuit, then the following terms, characterizing the properties of “f”, can be defined. Peak value of f ( fˆ ) : As the name suggests fˆ = f max over all time. Average (DC) value of f(Fav) : Assuming f to be periodic over the time period T 1 T Fav = ∫ f(t)dt ……………………………….(9.1) T 0 RMS (effective) value of f(FRMS) : For f , periodic over the time period T, 1 T 2 FRMS = f (t)dt …………………………..(9.2) T ∫0 Form factor of f(fFF) : Form factor of ‘f ‘ is defined as F f FF = RMS …………………………………. …(9.3) Fav Ripple factor of f(fRF) : Ripple factor of f is defined as 2

f RF =

2

FRMS - Fav Fav

2

= f FF -1 …………………….(9.4)


Ripple factor can be used as a measure of the deviation of the output voltage and current of a rectifier from ideal dc.

( )

Peak to peak ripple of f fˆpp : By definition fˆpp = f max - f min Over period T……………… …(9.5)

Fundamental component of f(F1): It is the RMS value of the sinusoidal component in the Fourier series expression of f with frequency 1/T. 1 2 2 f A1 + f B1 ………………………....(9.6) ∴ F1 = 2 T 2 where f A1 = ∫ f ( t ) cos 2π t dt ……………………(9.7) T T 0 2 T f B1 = ∫ f ( t ) sin 2π t dt …………………….(9.8) T T 0

(

)

Kth harmonic component of f(FK): It is the RMS value of the sinusoidal component in the Fourier series expression of f with frequency K/T. 1 2 2 ∴ FK = f AK + f BK …………………………(9.9) 2 2 T where f AK = ∫ f(t) cos2πK t T dt ………………...(9.10) T 0 2 T f BK = ∫ f(t) sin2πK t T dt …………………(9.11) T 0

(

)

Crest factor of f(Cf) : By definition fˆ ……………………………………(9.12) Cf = FRMS Distortion factor of f(DFf) : By definition F DFf = 1 …………………………………..(9.13) FRMS Total Harmonic Distortion of f(THDf): The amount of distortion in the waveform of f is quantified by means of the index Total Harmonic Distortion (THD). By definition 2

⎛ Fk ⎞ THD f = ∑ ⎜ ⎟ ………………………..(9.14) K=0 ⎝ F1 ⎠ α

K ≠1

From which it can be shown that 2

1- DFf THDf = ……………………………(9.15) DFf


Displacement Factor of a Rectifier (DPF): If vi and ii are the per phase input voltage and input current of a rectifier respectively, then the Displacement Factor of a rectifier is defined as. DPF = cosφi …………………………………(9.16)

Where φi is the phase angle between the fundamental components of vi and ii. Power factor of a rectifier (PF): As for any other equipment, the definition of the power factor of a rectifier is Actual power input to the Rectifier ….(9.17) PF = Apparent power input to the Rectifier if the per phase input voltage and current of a rectifier are vi and ii respectively then V I cosφi PF = i1 i1 ………………………………(9.18) ViRMS IiRMS

If the rectifier is supplied from an ideal sinusoidal voltage source then Vi1 = ViRMS I PF = i1 cosφi = DFi1 × DPF ………………..(9.19) so, IiRMS In terms of THDii DPF PF = ……………………………...(9.20) 2 1+ THDii Majority of the rectifiers use either diodes or thyristors (or combination of both) in their circuits. While designing these components standard manufacturer’s specifications will be referred to. However, certain terms are used in relation to the rectifier as a system. They are defined next. Pulse number of a rectifier (p): Refers to the number of output voltage/current pulses in a single time period of the input ac supply voltage. Mathematically, pulse number of a rectifier is given by Time period of the input supply voltage . p= Time period of the minium order harmonic in the output voltage/current. Classification of rectifiers can also be done in terms of their pulse numbers. Pulse number of a rectifier is always an integral multiple of the number of input supply phases. Commutation in a rectifier: Refers to the process of transfer of current from one device (diode or thyristor) to the other in a rectifier. The device from which the current is transferred is called the “out going device” and the device to which the current is transferred is called the “incoming device”. The incoming device turns on at the beginning of commutation while the out going device turns off at the end of commutation. Commutation failure: Refers to the situation where the out going device fails to turn off at the end of commutation and continues to conduct current. Firing angle of a rectifier (α): Used in connection with a controlled rectifier using thyristors. It refers to the time interval from the instant a thyristor is forward biased to the instant when a gate pulse is actually applied to it. This time interval is expressed in radians by multiplying it with


the input supply frequency in rad/sec. It should be noted that different thyristors in a rectifier circuit may have different firing angles. However, in the steady state operation, they are usually the same. Extinction angle of a rectifier (γ): Also used in connection with a controlled rectifier. It refers to the time interval from the instant when the current through an outgoing thyristor becomes zero (and a negative voltage applied across it) to the instant when a positive voltage is reapplied. It is expressed in radians by multiplying the time interval with the input supply frequency (ω) in rad/sec. The extinction time (γ/ω) should be larger than the turn off time of the thyristor to avoid commutation failure. Overlap angle of a rectifier (μ): The commutation process in a practical rectifier is not instantaneous. During the period of commutation, both the incoming and the outgoing devices conduct current simultaneously. This period, expressed in radians, is called the overlap angle “μ” of a rectifier. It is easily verified that α + μ + γ = π radian. Exercise 9.1

Fill in the blank(s) with the appropriate word(s). i) ii) iii) iv) v) vi) vii)

In a rectifier, electrical power flows from the _________ side to the ________ side. Uncontrolled rectifiers employ _________ where as controlled rectifiers employ ________ in their circuits. For any waveform “Form factor” is always _______ than or equal to unity. The minimum frequency of the harmonic content in the Fourier series expression of the output voltage of a rectifier is equal to its _________. “THD” is the specification used to describe the quality of ___________ waveforms where as “Ripple factor” serves the same purpose for _________ for waveforms. Input “power factor” of a rectifier is given by the product of the _________ factor and the ________ factor. The sum of “firing angle”, “Extinction angle” and “overlap angle” of a controlled rectifier is always equal to _________.

Answers: (i) ac, dc; (ii) diodes, thyristors; displacement, distortion; (vii) π

(iii) greater; (iv) pulse number; (v) ac, dc; (vi)

9.3 Single phase uncontrolled half wave rectifier This is the simplest and probably the most widely used rectifier circuit albeit at relatively small power levels. The output voltage and current of this rectifier are strongly influenced by the type of the load. In this section, operation of this rectifier with resistive, inductive and capacitive loads will be discussed.


Fig 9.2 shows the circuit diagram and the waveforms of a single phase uncontrolled half wave rectifier. If the switch S is closed at at t = 0, the diode D becomes forward biased in the the interval 0 < ωt ≤ π. If the diode is assumed to be ideal then For 0 < ωt ≤ π v0 = vi = √2 Vi sin ωt ………………………(9.21) vD = vi – v0 = 0 Since the load is resistive 2V0 i0 = v0 R = sinωt …………………..(9.22) R ii = i0 For ωt > π, vi becomes negative and D becomes reverse biased. So in the interval π < ωt ≤ 2π ii = i0 = 0 v0 = i0R = 0………………………………...(9.23) vD = vi – v0 = vi = √2 Vi sinωt From these relationships 1 2π 1 π 2Vi ……….(9.24) V0AV = v 0 dωt = 2Vi sinωtdωt = ∫ ∫ 2π 0 2π 0 π V 1 π 2 2 VDRMS = 2Vi sin ωtdωt = i ……………………...(9.25) ∫ 2π 0 2


It is evident from the waveforms of v0 and i0 in Fig 9.2 (b) that they contain significant amount of harmonics in addition to the dc component. Ripple factor of v0 is given by 2

2

VDRM - VDAV 1 2 v0RF = = π - 4 ………………………… (9.26) VDAV 2 With a resistive load ripple factor of i0 will also be same. Because of such high ripple content in the output voltage and current this rectifier is seldom used with a pure resistive load. The ripple factor of output current can be reduced to same extent by connecting an inductor in series with the load resistance as shown in Fig 9.3 (a). As in the previous case, the diode D is forward biased when the switch S is turned on. at ωt = 0. However, due to the load inductance i0 increases more slowly. Eventually at ωt = π, v0 becomes zero again. However, i0 is still positive at this point. Therefore, D continues to conduct beyond ωt = π while the negative supply voltage is supported by the inductor till its current becomes zero at ωt = β. Beyond this point, D becomes reverse biased. Both v0 and i0 remains zero till the beginning of the next cycle where upon the same process repeats.

From the preceding discussion For 0 ≤ ωt ≤ β vD = 0 v0 = vi i0 = ii…………………………………………(9.27) for β ≤ ωt ≤ 2π Version 2 EE IIT, Kharagpur 10

v0 = 0 i 0 = ii = 0 vD = vi – v0 = vi 1 2π 1 β V0AV = v0 dωt = ∫ 2Vsinωtdωt ………………… (9.28) i ∫ 2π 0 2π 0 2Vi 1- cosβ or V0AV = ………………………………………... (9.29) π 2 1 β 2 2 V0RMS = 2V sin ωtdωt 2π ∫0 i

(

2

)

(

)

Vi 1 V β - sin2β = i = 2π 2 2

2β - sin2β ……………………..(9.30) 2π

Form factor of the voltage waveform is V 2β - sin2β vOFF = 0RMS = π ………………………………….(9.31) 2 V0AV 2π(1- cosβ) The ripple factor. 2

v0RF = vOFF -1 =

π(2β - sin2β) 2(1- cosβ)

2

- 1 ………………………………(9.32)

All these quantities are functions of β which can be found as follows. For 0 ≤ ωt ≤ β dio vi = 2Vsinωt =L + Ri0 …………………………………….(9.33) i dt i0 (ωt = 0) = i0 (ωt = β) = 0 The solution is given by

i 0 = I0 e

-

ωt tanφ

+

2Vi sin(ωt - φ) ……………………………………(9.34) Z

where tanφ =

ωL R

2

2

and Z =

2

R + ω L ……………………………………………..(9.35)

Putting the initial conditions of (9.33) ωt ⎤ 2Vi ⎡ tanφ i0 = + sin ( ωt - φ ) ⎥⎦ ………………………………(9.36) ⎢⎣sinφe Z β ⎤ 2Vi ⎡ tanφ i 0 (ωt = β) = + sin ( β - φ ) ⎦⎥ = 0 ⎢sinφe ⎣ Z -

β tanφ

= sin ( φ - β ) ………………………………………….(9.37) or sinφe β as a function of φ can be obtained by solving equation 9.37. Version 2 EE IIT, Kharagpur 11

It can be shown that β increases with φ. From Equation (9.29), V0AV decreases with increasing β while V0RMS increases with β. Therefore, with increasing φ (and hence increasing L) the form factor and the ripple factor of v0 worsens. However, the ripple factor of i0 decreases with increasing L. Therefore, in certain applications, where a smooth dc current is of prime importance (e.g. the field supply of a dc motor) this configuration of the rectifier is preferred.

The problem of poor form factor (ripple factor) of the output voltage can be solved to some extent by connecting a capacitor across the load resistance of Fig 9.2 (a). This single phase half wave rectifier supplying a capacitive load is shown in Fig 9.5 (a). Corresponding waveforms are shown in Fig 9.5 (b). If the capacitor was initially discharged the diode “D” is forward biased when the switch S is turned on at ωt = 0. The output voltage follows the input voltage. The diode D carries both the capacitor charging current and the load current. At ωt = β the sum of these two currents becomes zero and tends to grow in the negative direction. At this point the diode becomes Version 2 EE IIT, Kharagpur 12

reverse biased and disconnects the load (along with the capacitor) from the supply. The capacitor then discharges with the load current. Diode D does not become forward biased till the input supply voltage becomes equal to the capacitor voltage in the next cycle at ωt = (2π + φ). The same process repeats thereafter.

From the preceding discussion For 2π + φ ≤ ωt ≤ 2π + β

v0 = vi = 2V1sinωt ……………………………………..(9.38) dv v ii = i c + i0 = c 0 + 0 dt R or

2Vi [ ωRCcosωt + sinωt ] R 1 2Vi ( 2 2 2 2 ) = 1+ ω R C cos(ωt - θ) ……………………..(9.39) R 1 -1 where θ = tan ωRC

ii =


At ωt = β+ 2π, ii = 0 so β – θ = π/2 or β = θ + π/2 π 1 -1 or β = + tan ……………………………………….(9.40) 2 ωRC Again for β ≤ ωt ≤ 2π + φ dv v ii = 0, C 0 + 0 = 0, v 0 ( ωt = β ) = 2Vi cosθ . dt R -(ωt-β) tanθ ∴ v 0 = 2Vi cosθ e …………………………………..(9.41) at

ωt = 2π + φ, v0 = 2Vsinφ i 2Vi sinϕ = 2Vi cosθ e

or sinφ = cosθ e

-(

π -(2π+φ- -θ) tanθ 2

3π +φ-θ) tanθ 2

3π -( -θ) tanθ ⎤ -φ tanθ ⎡ or sinφ = ⎣ cosθ e 2 ……………………………...(9.42) ⎦e

From which φ can be solved. Peak to peak ripple in v0 is vˆ 0pp = 2Vi (1- sinϕ) ………………………………………….(9.43) As c → α, θ → 0 and β and φ → π/2 and vˆ 0pp → 0 Therefore, a very large capacitor helps to improve the ripple factor of the output voltage of this rectifier. However, as indicated by Equation (9.39) the peak current through the diode increases proportionately. It is also interesting to observe that unlike the previous cases the peak reverse voltage appearing across D is given by. v D max = 2Vi + v 0M ≈ 2 2Vi ………………………………(9.44) This is sometimes referred to as the peak inverse voltage rating (PIV) of the diode. Exercise 9.2

1. Fill in the blank(s) with the appropriate word(s). i) ii) iii) iv) v)

The ripple factor of the output voltage and current waveforms of a single phase uncontrolled half wave rectifier is ____________ than unity. With an inductive load, the ripple factor of the output __________ of the half wave rectifier improves but that of the output __________ becomes poorer. In both single phase half wave and full wave rectifiers the form factor of the output voltage approaches _________ with capacitive loads provided the capacitance is ________ enough. The PIV rating of the rectifier diode used in a single phase half wave rectifier supplying a capacitive load is approximately ________ the __________ input supply voltage. The % THD of the input current of the rectifiers supplying capacitive loads is __________.

Answers: (i) greater; (ii) current, voltage; (iii) unity, large; (iv) double, peak; (v) high.


2. An unregulated dc. power supply of average value 12 V and peak to peak ripple of 20% is to be designed using a single phase half wave rectifier. Find out the required input voltage, the output capacitance and the diode RMS current and PIV ratings. The equivalent load resistance is 50 ohms. Answer:

From equation 9.43. vˆ opp = 2Vi (1- sinϕ ) = 0.2×12 = 2.4 V.

∴ Vomax = 2Vi = 12 + 2.4 2 = 13.2V

∴ Vi = 9.33V

o

∴ sin ϕ = 0.818 or ϕ = 54.9 = 0.96 rad. Then from equation 9.42 -(3 π 2 + ϕ - θ) tanθ

0.818 = cosθ e (5.67 - θ) tanθ or 0.818 e = cosθ D From which θ ≈ 2.035 1 ∴ tan θ = = 0.03553, R = 50Ω, ∴ C = 1790 μF ωRC PIV of the diode = 2 2Vi = 26.4V . V 1 β 2 1 92.035 2 2 2 2 ii dωt = i 2 (1+ ω R C ) cos (ωt - θ)dωt ∫ 2π ϕ R 2π ∫54.9o 1 ⎡β -ϕ 1 1 ⎤ = 7.432 + sin2(β - θ) - sin2(ϕ - θ) ⎥ = 0.8564 Amps. ⎢ ⎦ 2π ⎣ 2 4 4

RMS. Diode current =

9.4 Single phase uncontrolled full wave rectifier Single phase uncontrolled half wave rectifiers suffer from poor output voltage and/or input current ripple factor. In addition, the input current contains a dc component which may cause problem (e.g. Transformer saturation etc) in the power supply system. The output dc voltage is also relatively less. Some of these problems can be addressed using a full wave rectifier. They use more number of diodes but provide higher average and rms output voltage. There are two types of full wave uncontrolled rectifiers commonly in use. If a split power supply is available (e.g. output from a split secondary transformer) only two diode will be required to produce a full wave rectifier. These are called split secondary rectifiers and are commonly used as the input stage of a linear dc voltage regulator. However, if no split supply is available the bridge configuration of the full wave rectifier is used. This is the more commonly used full wave uncontrolled rectifier configuration. Both these configurations are analyzed next.


9.4.1 Split supply single phase uncontrolled full wave rectifier.


Fig 9.6 shows the circuit diagram and waveforms of a single phase split supply, uncontrolled full wave rectifier supplying an R – L load. The split power supply can be thought of to have been obtained from the secondary of a center tapped ideal transformer (i.e. no internal impedance). When the switch is closed at the positive going zero crossing of v1 the diode D1 is forward biased and the load is connected to v1. The currents i0 and ii1 start rising through D1. When v1 reaches its negative going zero crossing both i0 and ii1 are positive which keeps D1 in conduction. Therefore, the voltage across D2 is vCB = v2 - v1 . Beyond the negative going zero crossing of vi, D2 becomes forward biased and the current i0 commutates to D2 from D1. The load voltage v0 becomes equal to v2 and D1 starts blocking the voltage vAB = v1 - v2 . The current i0 however continues to increase through D2 till it reaches the steady state level after several cycles. Steady state waveforms of the variables are shown in Fig 9.6 (b) from ωt = 0 onwards. It should be noted that the current i0, once started, always remains positive. This mode of operation of the rectifier is called the “Continuous conduction mode” of operation. This should be compared with the i0 waveform of Fig 9.3 (b) for the half wave rectifier where i0 remains zero for some duration of the input supply waveform. This mode is called the “ discontinuous conduction mode” of operation. From the above discussion For 0 ≤ ωt < π v0 = v1 i0 = ii1……………………………………....(9.45) for π ≤ ωt < 2π v0 = v2 i0 = ii2……………………………………........(9.46) Since v0 is periodic over an interval π 1 π 2Vi π 2 2Vi ……………..(9.47) V0AV = ∫ v 0 dωt = sinωtdωt = ∫ 0 0 π π π 1 π 2 2 V0RMS = 2V sin ωt dωt = Vi ………………………........(9.48) π ∫0 i V π ……………………………………….(9.49) ∴ v 0FF = 0RMS = V0AV 2 2 2

π -8 v 0RF = v -1 = ……………………………………..(9.50) 2 2 Both the form factor and the ripple factor shows considerable improvement over their half wave counter parts. 2 0FF



The single phase full wave rectifier still does not offer a smooth dc voltage. With resistive load, considerable ripple current will flow into the load. This problem can be solved by connecting a capacitor across the load resistance just as in the case of a half wave rectifier. If the capacitor was initially discharged, the diode D1 is forward biased when the switch S is turned on at ωt = 0. The diode D2 remains reverse biased. The output voltage follows the input voltage. D1 carries both the capacitor charging current and the load current. At ωt = β the sum of these two currents becomes zero and tends to grow in the negative direction. At this point the diode D1 becomes reverse biased and disconnects the load along with the capacitor from the supply. The capacitor then discharges through the load until at ωt = π + φ, v2 becomes greater than v0 and forward biases D2. D1 now remains reverse biased. D2 conducts up to ωt = π + β. The same process repeats thereafter. From the discussion above For π + φ ≤ ωt ≤ π + β

v0 = v2 = - 2Vsinωt i dv v ii2 = i c + i 0 = C 0 + 0 ………………………………………………(9.51) dt R 2Vi [ ωRCcosωt + sinωt ] or ii2 = R 1 1 2Vi ( -1 2 2 2 2 ) ….(9.52) = 1+ ω R C cos ( π + θ - ωt ) where θ = tan ωRC R π π π 1 -1 at ωt = π + β, ii1 = 0 so β - θ = or β = θ + or β = + tan …………(9.53) 2 2 2 ωRC Again for β ≤ ωt ≤ π + φ dv v ii1 = 0 ∴ C 0 + 0 = 0 v0 ( ωt = β ) = 2Vsinβ = 2Vi cosθ ……….(9.54) i dt R ∴ v 0 = 2Vi cosθ e

at ωt = π + φ,

-( ωt-β ) tanθ

v0 = 2sinφ

2Vsinφ = 2Vi cosθ e i or sinφ = cosθ e

-

…………………………………………….(9.55)

( π2 +θ-π-φ)tanθ

( π2 +φ-θ )tanθ

π -( -θ ) tanθ ⎤ -φtanθ ⎡ or sinφ = ⎣cosθ e 2 ………………………………………(9.56) ⎦e

From which φ can be solved. Peak to peak ripple in v0 is vˆ 0pp = 2Vi (1- sinφ) ………………………………………………….(9.57) It can be shown that for the same R and C, vˆ 0pp given by Equation (9.57) is smaller than that given by Equation (9.43) for the half wave rectifier. The diode PIV ratings remain equal to 2 2Vi however.


Exercise 9.3

1. Fill in the blank(s) with the appropriate word(s). i) ii) iii)

The output voltage form factor of a single phase full wave rectifier is ___________. The output voltage of a single phase full wave rectifier supplying an inductive load is ___________ of the load parameters. The peak to peak output voltage ripple of a single phase split supply full wave rectifier supplying a capacitive load is ___________ compared to an equivalent half wave rectifier.

Answers: (i) π

2 2

; (ii) independent ; (iii) smaller.

2. An unregulated dc power supply is built around a single phase split supply full wave rectifier using the same input voltage and output capacitor found in the problem 2 of Exercise 9.2. The load resistance is 50 Ω. Find out the average output voltage, the peak to peak ripple in the output voltage and the RMS current ratings of the diodes. Answer: From the given data C = 1790 μF, R = 50 Ω, ∴ θ = 2.035° From equation 9.56 Sin θ = cos θ e-(π/2 + φ – θ) tan θ -0.03553(1.5353+ϕ )

= 0.946316 e Or sin θ = 0.99937 e From which φ = 65.33° Vi = 9.33 volts. ∴ vˆ opp = 2Vi (1- sinϕ ) = 1.20 volts.

-0.03553ϕ

vˆ opp = 2Vi - 0.6V = 13.2 - 0.6V = 12.6V . 2 ∴ % ripple = 9.5% V 1 π 2+θ 2 1 β 2 2 2 2 ii dωt = i 2 (1+ ω R C ) cos (ωt - θ)dωt RMS diode current = ∫ ∫ 2π ϕ R 2π ϕ 1 ⎡β -ϕ 1 ⎤ = 7.432 - sin2(ϕ - θ) ⎥ = 0.533 Amps. ⎢ ⎦ 2π ⎣ 2 4 V0AV = V0Max -


9.4.2 Single phase uncontrolled full bridge rectifier


The split supply full wave single phase rectifier offers as good performance as possible from a single phase rectifier in terms of the output voltage form factor and ripple factor. They have a few disadvantages however. These are

• •

They require a split power supply which is not always available. Each half of the split power supply carries current for only one half cycle. Hence they are underutilized. Version 2 EE IIT, Kharagpur 22

•

The ratio of the required diode PIV to the average out put voltage is rather high.

These problems can be mitigated by using a single phase full bridge rectifier as shown in Fig 9.8 (a). This is one of the most popular rectifier configuration and are used widely for applications requiring dc. power output from a few hundred watts to several kilo watts. Fig 9.8 (a) shows the rectifier supplying an R-L-E type load which may represent a dc. motor or a storage battery. These rectifiers are also very widely used with capacitive loads particularly as the front end of a variable frequency voltage source inverter. However, in this section analysis of this rectifier supplying an R-L-E load will be presented. Its operation with a capacitive load is very similar to that of a split supply rectifier and is left as an exercise. When the switch S is turned on at the positive going zero crossing of vi no current flows in the circuit till vi crosses E at point A. Beyond this point, D1 & D2 are forward biased by vi and current starts increasing through them till the point B. After point B, vi falls below E and io starts decreasing. Now depending on the values of R, L & E one of the following situations may arise.

• • •

io may become zero before the negative going zero crossing of vi at point C. io may continue to flow beyond C and become zero before the point D. io may still be non zero at point D.

It should be noted that if io >0 either D1D2 or D3D4 must conduct. Fig 9.4 (b) shows the waveforms for the third situation. If io >0 at point C the negative going input voltage reverse biases D1 & D2. Current io commutates to D3 and D4 as shown in the associated “conduction Diagram” in Fig 9.8 (b). It shows pictorially the conduction interval of different devices. The current io continues to decrease up to the point D beyond which it again increases. It should be noted that in this mode of conduction io always remain greater than zero. Consequently, this is called the continuous conduction mode of operation of the rectifier. In the other two situations the mode of operation will be discontinuous. The steady state waveforms of the rectifier under continuous conduction mode is shown to the right of the point ωt = 0 in Fig 9.4 (b). From this figure and preceding discussion For 0 < ωt ≤ π vo = vi = 2Vi sin ωt ii = io for π < ωt ≤ 2π v o = - vi = - 2Vi sin ωt ii = - io ∴ VoAV =

VoRMS

1 π 2 2 2Vi 2sin ωt d ωt = Vi ∫ π π o 1 π = 2V 2 sin 2 ωt d ωt = Vi π ∫o i

(9.58)

(9.59)

(9.60) (9.61)


∴ v OFF =

v oRF =

VoRMS π = VoAV 2 2 2

v OFF -1 =

π2 - 8 2 2

(9.62)

Finding out the characterizing quantities for ii will be difficult owing to its complicated waveform. Considerable, simplification is achieved (without significant loss of accuracy) by replacing the actual io waveform by its average value IoAV = VoAV / R. Fig 9.9 shows the approximate input current wave form and its fundamental component.

From Fig 9.9 Displacement angle φi = 0 ∴ Input displacement factor (DPF) = cos ϕi = 1 I 2 2 Distortion factor (DFil) = il = IoAV π Power Factor (PF) = DPF × DFil = % TH Dii = 100 ×

2 2 π

1 - DFii 2 = 100 × DFii 2

(9.63) (9.64) (9.65)

π2 - 8 2 2


The exact analytical expression for io (and hence ii) can be obtained as follows. for 0 < ωt ≤ π

vi =

io

ωt=0

Ldi o +E (9.67) dt (steady state periodic boundary cond.)

2Vi sin ωt = Ri o +

=

io

ωt=π

The general solution can be written as - ωt 2Vi ⎡ sinθ ⎤ i o = Io e tanϕ + sin ( ωt - ϕ ) ⎢ Z ⎣ cosϕ ⎥⎦ ωL E where tanϕ = ; Z = R 2 + ω2 L2 ; sin θ = R 2Vi From the boundary condition - tanπϕ 2Vi ⎡ sinθ ⎤ Io sin + = I e + ϕ o Z ⎢⎣ cosϕ ⎥⎦ 2Vi 2 sinϕ Io = -π Z 1 - e tanϕ

∴ io =

(9.68)

2Vi ⎡ sinθ ⎤ sin ϕ Z ⎢⎣ cosϕ ⎥⎦ (9.69)

ωt - tan 2 Vi ⎡ 2 sinϕ sinθ ⎤ ϕ e + sin ωt ϕ ( ) π ⎢⎣1 - e tanϕ Z cosϕ ⎥⎦

(9.70)

From which the condition for continuous conduction can be obtained. for continuous conduction io ≥ 0 for all 0 < ω t ≤ π hence io Min ≥ 0 or io ωt=θ ≥ 0 ∴ Condition for continuous conduction is 2 sinϕ - θ tanϕ sin θ e = sin (ϕ - θ ) + -π tanϕ cos ϕ 1- e

(9.71)

If the parameters of the load (i.e, R, L &E) are such that the left hand side of equation 9.71 is less than the right hand side conduction of the rectifier becomes discontinuous i.e, the load current becomes zero for a part of the input cycle. Discontinuous conduction mode of operation of this rectifier is discussed next.



Fig. 9.10(b) shows the waveforms of different variables under discontinuous conduction mode of operation. In this mode of operation D1 D2 are not forward biased till vi exceed E at ωt = θ. Consequently, no current flows into the load till this time. After ωt = θ, the load is connected to the input source through D1 D2 and io starts building up. Beyond ωt = π - θ, io starts decreasing and becomes zero at ωt = β < π. D1 D2 are reverse biased at this point. D3 D4 are forward biased at ωt = π + θ when io starts increasing again. Thus none of the diodes conduct during the interval β < ω + ≤ π + θ and io remains zero during this period. Form the preceding discussion Version 2 EE IIT, Kharagpur 27

θ < ωt ≤ β < π

for

vo = vi = 2Vi sin ωt

(9.72)

ii = i o for π < π + θ < ω + ≤ π + β < 2π v o = - vi = - 2Vi sin ωt

(9.73)

ii = - io vo = E ii = i o = 0

VoAV =

1 π

∫

π+θ

θ

other wise

vo d ωt =

(9.74)

π+θ 1 ⎡ β 2Vi sin ωt + ∫ E d ωt ⎤ ∫ β ⎦ π ⎣ θ

2Vi [ cos θ - cos β + ( π + θ - β ) sin θ ] π

OR VoAV =

β can be found in the following manner for θ < ωt ≤ β Ldi o v = 2 sin ωt = R i o + +E dt i o ωt =θ = io ωt=β = 0

(9.75)

(9.76)

The general solution is i o = Io e

ωt-θ - tan ϕ

+

2Vi ⎡ sin θ ⎤ sin ( ωt - φ ) ⎢ Z ⎣ cos ϕ ⎥⎦

where tanϕ = ωL , Z = R From the initial condition io Io =

∴ io = Putting i o

2Vi Z 2Vi Z ωt = β

(9.77)

R 2 + ω2 L2 , sinθ = E ωt=θ

2Vi

= 0

⎡sin (ϕ - θ ) + sinθ ⎤ ⎢⎣ cosϕ ⎥⎦ ⎡sin ϕ - θ e- tanωt-θϕ - sinθ 1- e -ωt-θ tanϕ + sin ( ωt - ϕ ) ⎤⎥ ) ⎢⎣ ( cosϕ ⎦ = 0 in Equation 9.79.

(

)

θ-β sinθ ⎡ 1 - e tanϕ ⎤ - sin (ϕ - θ ) e cosϕ ⎣⎢ ⎦⎥ Form which β can be solved.

sin ( β - ϕ ) =

θ-β tanϕ

(9.78) (9.79)

(9.80)

Exercise 9.4

1. Fill in the blank(s) with the appropriate word(s). i)

The average output voltage of a full wave bridge rectifier and a split supply full wave rectifier are __________ provided the input voltages are ___________. Version 2 EE IIT, Kharagpur 28

ii) iii) iv)

For the same input voltage the bridge rectifier uses ___________ the number of diodes used in a split supply rectifier with _________ the PIV rating. For continuous conduction, the load impedance of a bridge rectifier should be __________. In the ___________ conduction mode the output voltage of a bridge rectifier is __________ of load parameters.

Answers: (i) equal, equal; (ii) double, half; (iii) inductive; (iv) continuous, independent.

2. A battery is to be charged using a full bridge single phase uncontrolled rectifier. On full discharge the battery voltage is 10.2 V. and on full charge it is 12.7 volts. The battery internal resistance is 0.1Ω. Find out the input voltage to the rectifier so that the battery charging current under full charge condition is 10% of the charging current under fully discharged condition. Assume continuous conduction under all charging condition and find out the inductance to be connected in series with the battery for this condition. Answer: Let the rectifier input voltage be Vi and the charging current under fully discharged condition be I. Then assuming continuous conduction 2 2Vi 2 2 - 0.1I = 10.2 and V - 0.01I = 12.7 π π i ∴ 0.09I = 2.5 V ∴ I = 27.78 Amps and Vi = 14.415 volts. If conduction is continuous at full charge condition it will be continuous for all other charging conditions. For continuous conduction 2sinϕ -θ tanϕ sinθ e = sin(ϕ - θ) + -π tanϕ cosϕ 1- e E From given data sinθ = = 0.623, θ = 38.535° 2Vi From which φ = 86.5° ∴ tan ϕ = ωL = 16.35 or ωL = 1.635 ohms R ∴ L = 5.2 mH.

References [1] [2]

P.C. Sen, “Power Electronics”, Tata McGraw –Hill Publishing Company Limited. 1995 Muhammad H. Rashid, “Power Electronics, circuits, Devices and applications” Prentice – Hall of India Private Limited, Second Edition, 1994


Module Summary •

A rectifier is a power electronic converter which converts ac voltage or current sources to dc voltage and current.

•

In a rectifier, electrical power flows from the ac input to the dc output.

•

In many rectifier circuits, power can also flow from the dc side to the ac side, where upon, the rectifier is said to be operating in the “inverter mode”.

•

Rectifiers can be classified based on the type of device they use, the converter circuit topology, number of phases and the control mechanism.

•

All rectifiers produce unwanted harmonies both at the out put and the input. Performance of a rectifier is judged by the relative magnitudes of these harmonies with respect to the desired output.

•

For a given input voltage and load, the output voltage (current) of an uncontrolled rectifier can not be varied. However, the output voltage may vary considerably with load.

•

Single phase uncontrolled half wave rectifier with resistive or inductive load have low average output voltage, high from factor and poor ripple factor of the output voltage waveform.

•

Single phase uncontrolled full wave rectifier have higher average output voltage and improved ripple factor compared to a half wave rectifier with resistive and inductive load.

•

With highly inductive load the output voltage waveform of a full wave rectifier may be independent of the load parameters.

•

With a capacitive load the output voltage form factor approaches unity with increasing capacitance value for both the half wave and the full wave rectifiers. However, THD of the input current also increases.

•

A full wave bridge rectifier generates higher average dc voltage compared to a split supply full wave rectifier. However it also uses more number of diodes.


Practice Problems and Answers


Q1.

What will be the load voltage and current waveform when a single phase half wave uncontrolled rectifier supplies a purely inductive load? Explain your answer with waveforms.

Q2.

The split supply of a single phase full wave rectifier is obtained from a single phase transformer with a single primary and a center tapped secondary. The rectifier supplies a purely resistive load. Assuming the transformer to be ideal find out the, displacement factor, distortion factor and the power factor at the primary side of the transformer.

Q3.

A single phase split supply full wave rectifier is designed to supply an inductive load. The average load current is 20 A, and the ripple current is negligible. Can the same rectifier be used with a capacitive load drawing the same 20 Amps average current? Justify your answer.

Q4.

A 200V, 15 Amps, 1500 rpm separately excited dc motor has an armature resistance of 1 Ω and inductance of 50 mH. The motor is supplied from a single phase full wave bridge rectifier with input voltage of 230 V, 50 HZ. Neglecting all no load losses, find out the no load speed of the machine. Also find out the torque and speed at the boundary between continuous and discontinuous conduction.


Answer 1

Without loss of generality it can be assumed that S is turned ON at ωt = 0. Since, if it is turned ON anytime after ωt = 0, the volt-sec. across the inductor will dictate that the current through it becomes zero before the next positive going zero crossing of vi . In the region 0 ≤ ωt < π D is forward biased and v0 = vi di ∴ L 0 = 2Vsinωt i 0 (0) = 0 i dt di i0 or ωL 0 = 2Vsinωt =0 i ωt = 0 dωt 2Vi 2Vi cosωt I0 = ∴ i 0 = I0 ωL ωL 2Vi (1- cosωt) ∴ i0 = ωL 2 2Vi i0 = >0 at ωt = π, ωL ∴ D conducts beyond ωt = π until i0 is zero again. Let the extinction angle be ωt = β > π.

`

Then for 0 ≤ ωt ≤ β 2Vi i0 = (1- cosωt) ωL 2Vi i0 = (1- cosβ) for π ≤ β ≤ 2π the only solution is β = 2π ωt = β ωL


∴ v0 = vi for 0 ≤ ωt ≤ 2π and

i0 =

2Vi (1- cosωt) 0 ≤ ωt ≤ 2π ωL

Answer 2

Figure shows the secondary voltage and current waveforms of the rectifier. From the given data N vS1 = S 2VP sinωt NP N V iS1 = S 2 P sinωt NP R iS1 = 0 otherwise. N vS2 = - S 2VP sinωt NP N V iS2 = - S 2 P sinωt NP R iS2 = 0 otherwise

for 0 ≤ ωt ≤ π

for π ≤ ωt ≤ 2π

From the MMF balance of an ideal transformer N Pi P - NSiS1 + NSiS2 = 0 or

iP =

NS 2VP (iS1 - iS2 ) = sinωt 2 NP ⎛ NP ⎞ ⎜N ⎟ R ⎝ S⎠

∴ At the input Displacement factor = Distortion factor = Power factor = 1.0


Answer 3

If the load current is 20A with negligible ripple. The required RMS current rating of the rectifier diode, with reference to Fig 9.6 (b) will be I D1RMS = I D2RMS = 20 Amps . 2 However from Fig 9.7 (b) and Problem 2 of Exercise 9.3 the required RMS current for a capacitive load will be much larger than 20 Amps. Therefore the same rectifier can not be used. Answer 4

Since all no load losses are neglected the developed power at no load and hence the no load torque will be zero. Therefore, the average armature current will also be zero. However, since a diode rectifier can not conduct instantaneous negative load current, zero average current will imply that the instantaneous value of the armature current at all time will be zero at no load.With reference to Fig 9.10 this condition will require the rectifier diodes to remain reverse biased at all time. Hence at no load E ≥ 2Vi However E will not exceed 2Vi , since once ia becomes zero when E = 2Vi there will be no developed torque to accelerate the motor. Hence the motor speed and E will not increase any further. Thus at no load E = 2Vi = 325.27 volts . Under the rated condition at 1500 rpm Erated = 200 – 15 × 1.0 = 185 volts. E N Now = E rated N rated E 325.27 = 1500× = 2637 rpm . ∴ N = N rated × E rated 185 At the boundary between the continuous and discontinuous mode of conduction. 2sinφ -θ tanφ sinθ e = sin(φ - θ) + -π tanφ cosφ 1- e 2sinφ θ tanφ or = [ cosϕ sin(φ - θ) + sinθ ] e -π tanφ 1- e -3

ωL 100π ×50×10 = = 15.708 R 1 cosφ = 0.0635 φ = 1.507 rad. and sin2φ = 0.1268

where tanφ =

∴ 0.6995 = [ 0.0635 sin(1.507 - θ) + sinθ ] e E -1 o from which θ = sin ∴ E = 202.48 V = 38.5 2Vi but E at 1500 RPM = 185 volts. ∴ Speed at the junction of continuous and discontinuous condition is 202.48 1500 × = 1642 RPM. 185 0.06366 θ


⎛ 2 2Vi ⎞ Average armature current is ⎜ ⎟ R = 4.593 Amps. ⎝ π ⎠ 4.593 ×100 = 30.62% of rated torque. ∴ Torque = 15
