micromachines Article
Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application Ganesh Jayakumar *, Per-Erik Hellström
and Mikael Östling
KTH Royal Institute of Technology, Department of Electronics, School of Electrical Engineering and Computer Science, 16440 Kista, Sweden;
[email protected] (P.-E.H.);
[email protected] (M.Ö.) * Correspondence:
[email protected] Received: 3 October 2018; Accepted: 23 October 2018; Published: 25 October 2018
Abstract: Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (VG ) and backgate voltage (VBG ). The liquid potential can be monitored using the FG. We report the transfer characteristics (ID -VG ) of N- and P-type SiRi pixels. Further, the ID -VG characteristics of the SiRis are studied at different VBG . The application of VBG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (VTH ) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large VBG (≥25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large VBG to switch ON. Thus, P-type pixels exhibit excellent ION /IOFF ≥ 106 , SS of 70–80 mV/dec and VTH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors. Keywords: silicon ribbon pixel; silicon ribbon biosensor; lab-on-chip; SiRi CMOS integration; selective multiplexed detection; SiRi frontgate mode; SiRi backgate mode
1. Introduction Silicon ribbon (SiRi) field-effect-transistors (FETs) have been widely recognized as efficient standalone prostate specific antigen (PSA) cancer marker, DNA, virus and pH sensors [1–9]. The small size, high surface to volume ratio, electrical read-out and a dimension that is comparable to the target of interest make SiRi-FETs an excellent contender for label-free pH and bio detection [1–9]. Table 1 summarizes some of the most important works employing SiRi sensor for the detection of pH or bio targets. The sensing mechanism of the SiRi-FET is based on the principle of detection of surface charge (Figure 1). Initially, the current flowing through the SiRi is measured without any DNA hybridization and its threshold voltage is noted (Vth1 ) (Figure 1a). Later, the surface of the SiRi is functionalized with the receptors and target of interest such as a double stranded DNA. Then, the current flowing through the SiRi is re-measured. The addition of DNA molecule on the surface and the resulting
Micromachines 2018, 9, 544; doi:10.3390/mi9110544
www.mdpi.com/journal/micromachines
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the resulting hybridization process causes a change in the surface charge density (Qhybrid). As a result, it changes theprocess threshold voltage of the SiRi (Vth2) charge (Figuredensity 1b). By noting thea difference in the hybridization causes a change in the surface (Qhybrid ). As result, it changes threshold voltages th hybridization = )V(Figure th2 − Vth1 ) before andthe after DNA addition, the amount of the threshold voltage(ΔV of the SiRi (Vth2 1b). By noting difference in the threshold voltages additional charge (N hybrid ) resulting from the target molecule of interest can be estimated using (∆Vth hybridization = Vth2 − Vth1 ) before and after DNA addition, the amount of additional charge Equation (1) [10]. (N hybrid ) resulting from the target molecule of interest can be estimated using Equation (1) [10]. Nhybrid = Qhybrid/q = −∆Vth (ε0εr)/(qtox) Nhybrid = Qhybrid /q = −∆Vth (ε0 εr )/(qtox )
(1) (1)
Table1.1.A Asummary summary of of some some of of the the most most important important works works employing employing silicon silicon ribbon ribbon (SiRi) (SiRi) sensor sensor for for Table the detection of pH or bio targets. The distinction is made based on fabrication method (top-down the detection of pH or bio targets. The distinction is made based on fabrication method (top-down (TD) (TD) versus bottom-up substrate type Si (Bulk Si versus silicon-on-insulator (SOI)) and of versus bottom-up (BU)),(BU)), substrate type (Bulk versus silicon-on-insulator (SOI)) and type of type sensor. sensor. Further, the application and complementary-metal-oxide-semiconductor integration Further, the application and complementary-metal-oxide-semiconductor (CMOS)(CMOS) integration feature feature also considered. are also are considered. Reference Reference Zhang Zhangetetal.al.[1] [1] Lee Leeetetal.al.[2] [2] Park Parketetal.al.[3] [3] Yoo Yooetetal.al.[4] [4] Nguyenetetal.al.[5] [5] Nguyen Kimetetal.al.[6] [6] Kim Chaingetetal.al.[7] [7] Chaing Chenetetal.al.[8] [8] Chen Tarasov et al. [9] Tarasov et al. [9]
Fabrication Method, CMOS Fabrication Method, Integration Substrate, Device Type CMOS Integration Substrate, Device Type SOI, SiRi No TD,TD, SOI, SiRi No TD, SOI, SiRi No TD, SOI, SiRi No SOI, SiRi No TD,TD, SOI, SiRi No TD, SOI, SiRi No TD, SOI, SiRi No BU,BU, Bulk, SiNN-FET No Bulk, SiNN-FET No TD,TD, SOI, SiRi No SOI, SiRi No TD,TD, SOI, SiRi No SOI, SiRi No TD,TD, SOI, SiRi No SOI, SiRi No TD, SOI, SiRi No TD, SOI, SiRi No
Application Application Denguevirus virus(DEN-2) (DEN-2) Dengue pH pH pH pH pH pH DNA DNA PSA PSAcancer cancermarker marker H5N2 H5N2virus virus pH pH pH, ions pH, ions
Figure Figure 1. 1. A schematic schematic depicting the working working mechanism mechanism of aa silicon silicon ribbon ribbon (SiRi) (SiRi) sensor. sensor. (a) (a) The The threshold of the SiRi sensor is measured before bio th1)) of bio molecule molecule addition. addition. (b) The target target threshold voltage voltage (V (Vth1 double double strand strand DNA DNA molecule molecule is is added added on on the the surface surface where where itit undergoes undergoes hybridization hybridization process. process. As As aa result, the surface charge on the SiRi changes. The threshold voltage of the SiRi is measured again result, the surface charge on the SiRi changes. The threshold voltage of the SiRi is measured again (V ). By Bynoting notingthe thechange changeininthe thethreshold thresholdvoltage voltage(V (V −th1V),th1 ), the added charge on the surface th2 th2). th2 −V the added charge on the surface can (Vth2 can be estimated. be estimated.
In described in this workwork can be functionalized using the process shown In particular, particular,the theSiRi-FETs SiRi-FETs described in this can be functionalized using the process by Nguyen et al. [5] and Jayakumar et al. [11]. The first step in the DNA probe covalent grafting shown by Nguyen et al. [5] and Jayakumar et al. [11]. The first step in the DNA probe covalent process silanization. In this step, surface is functionalized with single strand DNAstrand using graftingisprocess is silanization. In the thissensor step, the sensor surface is functionalized with single
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an organosilane such as (3-Aminopropyl)triethoxysilane (APTES) [5]. Later, the sensor can be used for the hybridization detection of target DNA that is complementary to the probe DNA [11]. At the same step, to verify the selectivity of the sensor, its surface is exposed to non-complementary DNA and saline buffer solution that is free of complementary DNA [11]. A well-behaved SiRi sensor is expected to not respond to the non-complementary DNA or the salt crystallization after drying and only exhibit VTH shifts because of the target complementary DNA [11]. Indeed, the sensing mechanism employed by works listed in Table 1 relies on the conductance changes in the SiRi channel. However, as shown in our previous work, during the electrical characterization of the sensor (after silanization, grafting and hybridization steps), the current ratio (ION /IOFF ) and subthreshold slope (SS) of the SiRi-FET almost remain constant. The transfer characteristics of the sensor only translate as shift in the threshold voltage [11] (Figure 1). This method of detection ensures that there is no fluctuation of the drain current during sensing and the field effect electrostatic coupling occurs between the charges on the SiRi surface and the channel [11]. The biodetection efficiency of such a DNA hybridization detection process is characterized by the sensitivity parameter, which is defined as the threshold voltage shift (Vth2 − Vth1 ) after hybridization [11]. The attractive benefits of SiRi sensors can be further extended to selective target detection, multi-target detection, and synchronous real-time read-out by integrating them with complementary metal oxide semiconductor (CMOS) field-effect transistors (FETs) and circuits [12]. Furthermore, the integration of SiRi sensors with CMOS read-out circuits establishes a platform for the realization of a complete lab-on-chip (LOC) sensor. However, as can be seen in Table 1, even though many researchers have successfully used the standalone SiRi sensor for detection of pH and bio-targets, none of the works address the monolithic integration of SiRi with CMOS. The goal of this paper is to establish one such platform. We achieve the SiRi CMOS integration by employing a pixel-based LOC architecture. The pixel-based SiRi LOC design is akin to the CMOS image sensor pixel design [13]. Figure 2 shows the proposed scalable sequential read-out scheme to integrate SiRi sensors with CMOS. The details of the circuits and the layout are described elsewhere [14]. Here, we highlight the salient features relevant to SiRi integration. In the pixel based integration scheme, each SiRi is connected to an on-chip fluid gate and a control transistor forming a SiRi pixel [14]. “N × N” matrix of such pixels can be addressed using N-bit vertical and horizontal shift register circuits, respectively. In this design, the transistor is configured as a switch to particularly control a specific row or column. Especially, the on-chip fluid gate is integrated in the design to monitor the potential in the liquid environment. The advantage of such a design is that the output current of the pixel array could further be monolithically connected to amplifiers for signal amplitude magnification, band pass filters for reducing the noise or allowing only a certain range of the signal and other read-out circuits such as a trans-impedance amplifiers to convert current to voltage output [12]. To avail such desirable benefits of CMOS integration, the manufacturing scheme employed for the realization of SiRi pixel sensor also has to be CMOS compatible. Traditionally, there are two methods to manufacture SiRi sensors: (1) bottom-up (BU); and (2) top-down (TD) [15–17]. In the BU method, the SiRi sensors are realized by using molecular pre-cursors. For example a silicon nanonet field effect transistor (SiNN-FET) can be manufactured on a bulk Si wafer using the BU method [5,18]. On the contrary, in the TD method, SiRi sensors are commonly realized on a silicon-on-insulator (SOI) substrate using the well-established lithography and patterning techniques [2–4,6–9,19]. It is particularly challenging to transfer the bottom-up grown nanonets on to a CMOS wafer and continue processing due to the tangling of the grown wires, difficulty in alignment and manual errors [20]. Further, in the bottom-up method, the probability of introducing contaminants on to the wafer is very high [18,20]. It also demands the usage of specialized alignment methods that tend to be time consuming [18,20]. In comparison, the top down method is CMOS compatible and allows for the low-cost co-integration of SiRi sensors with metal-oxide-semiconductor field-effect transistors (MOSFETs) and circuits [14–17].
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Therefore, in this article, we utilize the fully CMOS compatible top-down method to fabricate the SiRi pixel sensors on wafer scale. Then, we show the first electrical results of the pixel design for both N- and P-type SiRi pixels. Single SiRi sensors of dimensions width W= 1 µm and length L = 1 µm were connected to N- and P-type CMOS transistors (W = 4 µm and L = 1 µm) to fully exploit the monolithic integration of SiRi with CMOS transistors. The SiRi pixel can be operated in two different modes: (a) the frontgate mode; and (b) the backgate mode. In the frontgate mode, the pixel is turned ON or OFF by applying a frontgate voltage to the N- and P-type transistors, while the backgate bias is fixed. In the backgate mode, the pixel is turned ON or OFF by applying a backgate voltage to the substrate, while the frontgate bias of the N- and P-type transistors is fixed. Both modes of operation validate the concept of establishing control of individual SiRi pixel modules in a matrix of sensors. Indeed, these promising results will empower the large-scale cost efficient production of compact label-free SiRi based lab-on-chip (LOC) sensors. Micromachines 2018, 9, x 4 of 14
Figure 2. Circuit diagram of SiRi pixel based lab-on-chip (LOC). Each SiRi is connected to an on-chip fluid gate and a control control transistor transistor forming forming aa SiRi SiRi pixel pixel [14]. [14]. “N “N × × N” N” matrix matrix of of such pixels can be addressed using N-bit vertical and horizontal shift register register circuits, circuits, respectively. respectively.
2. Materials andinMethods Therefore, this article, we utilize the fully CMOS compatible top-down method to fabricate the SiRi sensorssteps on wafer Then, we show thepixel firstsensor electrical pixel3.design for Thepixel important in thescale. fabrication of the SiRi areresults shownofinthe Figure The SiRi 15 − 3 both Nand P-type SiRi pixels. Single SiRi sensors of dimensions width W= 1 μm and length L = 1 pixel sensors were fabricated on boron doped (1 × 10 cm ) 4” (100 mm) SOI wafer. A 145 nm buried μm were connected to Nand P-type CMOS transistors (W = 4 μm and L = 1 μm) to fully exploit the oxide layer (BOX) separates the top 55 nm crystalline silicon (c-Si) device layer from the substrate. monolithic integration of SiRi with CMOS transistors. The SiRi pixel can be to operated in two different The c-Si device layer was thermally oxidized at 1000 ◦ C and thinned down 20 nm (Figure 3A). modes: (a) the frontgate mode; and (b) the backgate mode. In the frontgate mode, the pixel is turned Then, 40 nm SiO2 hard mask was deposited by plasma enhanced chemical vapor deposition ◦ ON or OFF by applying a frontgate voltage to the Nand P-type transistors, while the backgate bias (PECVD) at 400 C (Figure 3B). The SiRi pattern and active region was defined on the SiO2 surface is fixed. In the backgate the pixel is turned or the OFFSiO by2 applying a backgate to c-Si the using conventional I-line mode, lithography. Using a resistON mask was selectively etchedvoltage towards substrate, while the frontgate bias of the Nand P-type transistors is fixed. Both modes of operation in CHF3 /CF4 /O2 plasma (Figure 3C). Then, the 20 nm c-Si device layer was etched using SiO2 as mask validate the concept of establishing control of individual SiRi pixel modules in a matrix of sensors. in Cl2 /HBr/O 2 plasma (Figure 3D). The final dimension of the SiRi sensor is 1 µm × 1 µm × 20 nm Indeed, these promising results empower large-scale cost efficient of compact (L × W × H). Next, a diluted HFwill spray etch wasthe employed to strip the SiO2 production on top of source/drain label-free SiRi based lab-on-chip (LOC) sensors. pads which recessed the BOX to 140 nm. Later, the active region of the SiRi pixel was thermally oxidized at 800 ◦ C to form 5 nm SiO2 . This 5 nm SiO2 forms the gate dielectric material for the control 2. Materials Methods transistor in and the SiRi pixel. This step was followed by 10 nm physical vapor deposition (PVD) of TiN gate The metal, low-pressure vapor deposition (LPCVD) of 100are nmshown n+ polysilicon PECVD important steps chemical in the fabrication of the SiRi pixel sensor in Figureand 3. The SiRi 15 −3 deposition of 40 nm SiO hard mask. 2 pixel sensors were fabricated on boron doped (1 × 10 cm ) 4” (100 mm) SOI wafer. A 145 nm buried transistor gate and on-chip fluid were patterned usingdevice I-line lithography andsubstrate. without oxideThe layer (BOX) separates the top 55 nmgate crystalline silicon (c-Si) layer from the + poly silicon/ TiN stack was breaking vacuum in the reactive ion etching (RIE) chamber the n The c-Si device layer was thermally oxidized at 1000 °C and thinned down to 20 nm (Figure 3A).
Then, 40 nm SiO2 hard mask was deposited by plasma enhanced chemical vapor deposition (PECVD) at 400 °C (Figure 3B). The SiRi pattern and active region was defined on the SiO2 surface using conventional I-line lithography. Using a resist mask the SiO2 was selectively etched towards c-Si in CHF3/CF4/O2 plasma (Figure 3C). Then, the 20 nm c-Si device layer was etched using SiO2 as mask in Cl2/HBr/O2 plasma (Figure 3D). The final dimension of the SiRi sensor is 1 μm × 1 μm × 20
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selectively etched towards underlying c-Si active region using Cl2 /HBr/O2 and BCl3 /Cl2 plasma, Micromachines 2018, 9, x 5 of 14 respectively (Figure 3E). Next, using a resist mask that covers the SiRi region, the active regions of the SiRi pixelpixel was was implanted. To form N-type SiRi pixels, the source/drain regions was doped with with As+ , the SiRi implanted. To form N-type SiRi pixels, the source/drain regions was doped whereas, to form P-type SiRi pixels, the source/drain regions werewere doped withwith BF2 (Figure 3F). 3F). As+, whereas, to form P-type SiRi pixels, the source/drain regions doped BF2 (Figure
3. Schematic Schematicof ofthe theprocess processsteps steps employed manufacturing of the sensor: (A) Figure 3. employed in in thethe manufacturing of the SiRiSiRi pixelpixel sensor: (A) SOI wafer starting substrate; (B) deposition of 40 nm SiO hard mask; (C) lithography and RIE of SiO hard SOI wafer starting substrate; (B) deposition of 40 nm 2 SiO2 hard mask; (C) lithography and RIE of 2 SiO2 mask define contact of the control transistor SiRi channel; (D)channel; reactive ion hard to mask to the define the pads contact pads of the control and transistor and SiRi (D) etching reactive(RIE) ion of the crystalline silicon (c-Si) device SiO andSiO transfer thetransfer pattern of to the c-Sipattern device 2 maskof and etching (RIE) of the crystalline siliconlayer (c-Si)using device layer using 2 mask + polysilicon layer; thermal gate-oxide growth, TiN gate metalTiN andgate n+ polysilicon and patterning to deposition and to c-Si(E) device layer; (E) thermal gate-oxide growth, metal and ndeposition define the frontgate the frontgate transistor and fluid gate of the pixel; (F)of Asthe or BF ion-implantation step patterning to defineofthe of the transistor andSiRi fluid gate SiRi pixel; (F) As or BF 2 2 using resist mask to form N-metal-oxide-semiconductor (NMOS) and P-metal-oxide-semiconductor ion-implantation step using resist mask to form N-metal-oxide-semiconductor (NMOS) and (PMOS) pixels respectively; (G)(PMOS) after dopant and SiO /SiNdopant spacer formation the2/SiN gate P-metal-oxide-semiconductor pixelsactivation respectively; (G)2after activationalong and SiO sidewall, NiSi ohmic contact formation; contact definition and (H) TiW/Al metal spacer formation along the gate sidewall,(H) NiSi ohmichole contact formation; contact holepatterning; definition and (I) etching pathways to access theetching SiRi test site using mask etching. Later, TiW/Al metal patterning; and (I) pathways to lithography access the SiRi testand siteRIE using lithography amask 10 nm atomic layer deposition (ALD) SiO passivation oxide that also behaves as sensing dielectric 2 layer deposition (ALD) SiO2 passivation oxide that also and RIE etching. Later, a 10 nm atomic is deposited. behaves as sensing dielectric is deposited. 15 −3 and energy 10 keV was optimized In In the the cases cases of of N Nand andPPSiRi SiRipixels, pixels,the thedose doseofof1 1××10 1015 cm cm−3 and energy 10 keV was optimized based on iterations in semiconductor simulation software SRIM (2013 based on iterations in semiconductor simulation software SRIM (2013 version) version) developed developed by by James James F. Ziegler, USA. The 40 nm SiO gate etch mask and thin layer of SiO gate dielectric material F. Ziegler, USA. The 40 nm SiO22 gate etch mask and thin layer of SiO22 gate dielectric material was was ◦ preserved preserved during during the the implantation implantation to to avoid avoid surface surface damage damage and and 77° tilt tilt angle angle was was opted opted to to avoid avoid channeling. stripping, a thin layerlayer of 10 nm SiOnm deposited by atomic layer deposition 2 was channeling. After Afterresist resist stripping, a thin of 10 SiO 2 was deposited by atomic layer (ALD) followed by deposition of an additional 60 nm SiN. The SiO /SiN stack 2 SiN. The was deposition (ALD) followed by deposition of an additional 60 nm SiO2patterned /SiN stackusing was I-line lithography and etched everywhere except on-top of the SiRi. This SiO /SiN stack is later used 2 patterned using I-line lithography and etched everywhere except on-top of the SiRi. This SiO2/SiN as a mask during processthe step to prevent silicidation of the SiRi. stack is later usedthe as asalicide mask during salicide process step to prevent silicidation of the SiRi. ◦ C for 10 s After the SiO /SiN patterning, a rapid thermal annealing (RTA) After the SiO22/SiN patterning, a rapid thermal annealing (RTA) step step followed followed at at 1000 1000 °C for 10 s to activate the dopants. Next, ~40 nm gate SiO mask and ~5 nm thermal oxide/10 nm SiO lying 2 2 to activate the dopants. Next, ~40 nm gate SiO2 mask and ~5 nm thermal oxide/10 nm SiO2 lying on on top region is is cleared cleared using using diluted diluted HF HF spray A 55 nm nm Ni Ni was was deposited deposited using top of of the the source/drain source/drain region spray etch. etch. A using ◦ C for 30 s to form low resistance ohmic source/drain and gate contacts PVD PVD and and annealed annealed at at 450 450 °C for 30 s to form low resistance ohmic source/drain and gate contacts (Figure 3G). The unreacted Ni was (3:1) mixture. 44:H (Figure 3G). The unreacted Ni wasstripped strippedininHH2 SO 2SO :H22O O22 (3:1) mixture. Then, Then, 400 400 nm nm PECVD PECVD SiO SiO22 was deposited, patterned using I-line lithography and RIE was done in CHF /CF /O plasma 3 3/CF 4 4/O22 plasma to was deposited, patterned using I-line lithography and RIE was done in CHF to define contact hole for the SiRi pixel. After metallization using PVD 100 nm TiW lining layer and define contact hole for the SiRi pixel. After metallization using PVD 100 nm TiW lining layer and 500 500 Al layer, patterning SF6 /BCl /Cl2 RIE etching (Figure 3H), 100 nm PECVD passivation nm nm Al layer, patterning andand SF6/BCl 3/Cl2 3RIE etching (Figure 3H), 100 nm PECVD passivation oxide oxide layer was deposited to protect the metal lines and the transistor. layer was deposited to protect the metal lines and the transistor.
The top-view scanning electron microscope (SEM) image of a typical single SiRi pixel device after the metallization step but prior to opening access to SiRi test site is shown in Figure 4A. At this stage, the 500 nm SiO2 is still lying on-top of the SiRi along with the 10 nm SiO2/60 nm SiN stack that was deposited to mask silicidation process. The sensing area of the SiRi channel was exposed by
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The top-view scanning electron microscope (SEM) image of a typical single SiRi pixel device after the metallization step but prior to opening access to SiRi test site is shown in Figure 4A. At this stage, the 500 nm SiO is still lying on-top of the SiRi along with the 10 nm SiO2 /60 nm SiN stack that was Micromachines 2018,2 9, x 6 of 14 deposited to mask silicidation process. The sensing area of the SiRi channel was exposed by using a resist I-line lithography step and step selective of ~570 CHF3 /CF /O23/CF plasma. using mask, a resist mask, I-line lithography and RIE selective RIEnm of dielectric ~570 nm in dielectric in 4CHF 4/O2 ◦ Then, 10Then, nm ALD SiOALD deposited at 350 Caton top the SiRi sensor 2 wasSiO plasma. 10 nm 2 was deposited 350 °Cofon top of the SiRi(Figure sensor3I). (Figure 3I).
PECVD SiO2
Transistor
Fluid Gate
Fluid Gate SiRi
Drain
Drain
Source
Gate
TiW/Al metal Transistor line passivized using PECVD Source SiO2
Nano ribbon buried under 400 nm PECVD SiO2
(A)
Gate
Access to nanoribbon site
(B)
Figure 4. 4. Top Topview viewscanning scanning electron microscope (SEM) image of a single SiRishowing pixel showing the electron microscope (SEM) image of a single SiRi pixel the control FET, fluid gate andgate SiRiand sensor: before access toaccess the SiRi site; test and site; (B) after control FET, fluid SiRi (A) sensor: (A)opening before opening to test the SiRi and opening (B) after access to access the SiRi opening totest the site. SiRi test site.
The ALD thethe passivation layer on top theofsensor as wellasaswell act as The ALDSiO SiO2 2will willbehave behaveasas passivation layer on of top the sensor asthe actsensing as the dielectric during the bio functionalization experiments. Figure 4B Figure shows the top-view imageSEM of a sensing dielectric during the bio functionalization experiments. 4B shows theSEM top-view SiRi pixel after opening access to SiRi test site. To probe the SiRi pixels, the 100 nm passivation oxide image of a SiRi pixel after opening access to SiRi test site. To probe the SiRi pixels, the 100 nm lying on-topoxide of thelying bondpads was using CHF plasma. Finally, a 2forming anneala 3 /CF 4 /O2using passivation on-top of etched the bondpads was etched CHF 3/CF4/O plasma.gas Finally, ◦ was donegas at 400 C and completion of the entire fabrication process. forming anneal was marks done atthe 400 °C and marks the completion of the entire fabrication process. 3. Electrical Characterization Characterization 3. Electrical The setup was used forfor thethe electrical evaluation of the sensors prior The setup shown shownininFigure Figure3I3I was used electrical evaluation of SiRi the pixel SiRi pixel sensors to functionalization. A Cascade 12,000 semi-automatic wafer prober (Cascade Beaverton, prior to functionalization. A Cascade 12,000 semi-automatic wafer prober Microtech, (Cascade Microtech, OR, USA) that was externally connected to a Keithley 4200-SCS parameter analyzer (Tektronix, Inc., Beaverton, OR, USA) that was externally connected to a Keithley 4200-SCS parameter analyzer Beaverton, was used perform direct (DC) electrical measurements. It also (Tektronix, OR, Inc.,USA) Beaverton, OR,to USA) was usedcurrent to perform direct current (DC) electrical facilitated full-scale wafer mapping. In the pixel module, the source terminal of the transistor is measurements. It also facilitated full-scale wafer mapping. In the pixel module, the source terminal connected to the column selection line while the drain terminal of the transistor is connected to the of the transistor is connected to the column selection line while the drain terminal of the transistor is SiRi. The SiRi pixel canThe be operated incan twobe modes—the backgate mode (Figure 5B) and frontgate mode connected to the SiRi. SiRi pixel operated in two modes—the backgate mode (Figure 5B) (Figure 5C). In the backgate mode, the gate of the control transistor is biased at a fixed frontgate voltage and frontgate mode (Figure 5C). In the backgate mode, the gate of the control transistor is biased at a while the SiRi is turnedwhile ON or sweeping backgate voltage the (Figure 5B). In the backgate fixed frontgate voltage theOFF SiRiby is turned ONthe or OFF by sweeping backgate voltage (Figure mode, ON themode, SiRi pixel, sufficient voltage needs to be applied such thatto the 5B). In to theturn backgate to turn ON thefrontgate SiRi pixel, sufficient frontgate voltage needs beMOSFET applied is firstthat turned ON (Figure 5B). turned In the frontgate mode, is turned OFF by sweeping such the MOSFET is first ON (Figure 5B).the In MOSFET the frontgate mode,ON theorMOSFET is turned the gate of the control transistor while the SiRi is biased at a fixed backgate voltage (Figure 5C). In the ON or OFF by sweeping the gate of the control transistor while the SiRi is biased at a fixed backgate frontgate mode, to turn ON the SiRi pixel, sufficient backgate voltage needs to be applied such that the voltage (Figure 5C). In the frontgate mode, to turn ON the SiRi pixel, sufficient backgate voltage SiRi is first turned ON. In the frontgate mode, the SiRi behaves as a resistor but turned ON/OFF using needs to be applied such that the SiRi is first turned ON. In the frontgate mode, the SiRi behaves as a the backgate voltage (Figure using 5C). the backgate voltage (Figure 5C). resistor but turned ON/OFF In the frontgate mode, the ofof thethe transistor (VG(V ) is)swept from −2.5 to +2.5 V and an initial bias In the frontgate mode, thegate gate transistor G is swept from −2.5 to +2.5 V and an initial voltage of −0.1 V for P-metal-oxide-semiconductor (PMOS) (or 0.1 V for N-metal-oxide-semiconductor bias voltage of −0.1 V for P-metal-oxide-semiconductor (PMOS) (or 0.1 V for (NMOS)) was applied to the drain terminal (VD ) while the source terminal (VS ) was connected to the N-metal-oxide-semiconductor (NMOS)) was applied to the drain terminal (VD) while the source ground. The SiRi is turned ON by the application of a constant bias voltage to the backgate (VBG ). terminal (VS) was connected to the ground. The SiRi is turned ON by the application of a constant In the backgate mode, an initial bias voltage of −0.1 V for PMOS (or 0.1 V for NMOS) was applied bias voltage to the backgate (VBG). In the backgate mode, an initial bias voltage of −0.1 V for PMOS (or 0.1 V for NMOS) was applied to the drain terminal (VD) while the source terminal (VS) was connected to the ground. Then, a bias voltage of 0 V was applied to the gate of the control transistor (both NMOS and PMOS), while the backgate was swept from 25 to −10 V for P-type and from 0 to 30 V for N-type SiRi, respectively. In both modes of operation, the fluid gate terminal (VFG) was left open and not connected as these measurements were performed prior to bio functionalization. The
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to the drain terminal (VD ) while the source terminal (VS ) was connected to the ground. Then, a bias voltage of 0 V was applied to the gate of the control transistor (both NMOS and PMOS), while the backgate was swept from 25 to −10 V for P-type and from 0 to 30 V for N-type SiRi, respectively. In both modes of operation, the fluid gate terminal (VFG ) was left open and not connected as these measurements bias Micromachines 2018,were 9, x performed prior to bio functionalization. The influence of substrate voltage 7 of 14 (VBG ) on standalone N- and P-type transistors was also studied in this work. During the electrical measurements of NMOS transistor, the VG wasof swept from −2.5 to 2.5 keeping the−2.5 VS at V, this work. During the electrical measurements NMOS transistor, the V VGwhile was swept from to02.5 V at 0.1keeping V and stepping −D15, 10,V− 5, 0,stepping 5, 10, 15,V20, 25 and 50−5, V).0,Similarly, VDwhile the VS atV0BG V,(V at − 0.1 and BG (−15, −10, 5, 10, 15, in 20,the 25 case and of 50 the V). PMOS transistor, the V wasPMOS swepttransistor, from −2.5the to 2.5 while keeping V, while VD at keeping −0.1 V and Similarly, in the case ofG the VG V was swept from the −2.5Vto 2.50 V the S at stepping (−−0.1 50, − 20, −15, − −5, 0, 5, 10, V). −10, −5, 0, 5, 10, 15 V). VS at 0 V,VVBG D at V25, and−stepping V10, BG (−50, −25, −20,15−15,
Figure Figure 5. 5. (A) The test setup for electrical evaluation of the SiRi pixel sensors in (B) (B) backgate backgate mode mode where where frontgate frontgate of of the the control control transistor transistor is fixed at at 00 V V while while the the backgate backgate of of the the SiRi SiRi is is swept swept from from − 10 to +30 V and (C) frontgate mode where the transistor frontgate is swept from − 2.5 to 2.5 V and −10 to +30 V and the transistor frontgate is swept from −2.5 and SiRi −10 V V for for P-type P-type SiRi). SiRi is is biased biased at at fixed fixed voltage voltage where where itit is is always always ON ON((−10
Table Table 22 shows shows the the NN- and and P-type P-type pixels pixels that that were were studied studied in in this this work. work. The The dimensions dimensions of of the the corresponding control transistor and ribbon module in the respective pixel is also shown. Single corresponding control transistor and ribbon module in the respective pixel is also shown. Single N-type of W W ==11μm µmand andLL==11μm µmwas wasconnected connectedtotoN-type N-typecontrol control transistor 1 µm and N-type SiRi SiRi of transistor ofof L =L 1=μm and W W 4 µm respectively. Single P-typeSiRi SiRiofofWW= =1 1μm µmand andLL==11μm µmwas was connected connected to to P-type P-type control = 4=μm respectively. Single P-type control transistor transistor of of L L= = 11 µm μm and and W W == 44 µm, μm, respectively. respectively. The The important important performance performance metrics metrics of of the the SiRi SiRi pixels and transistors, namely the subthreshold slope (SS) and threshold voltage (V ), were pixels and transistors, namely the subthreshold slope (SS) and threshold voltage (VTH TH), were noted noted from from the the transfer transfer characteristics. characteristics. The The linear linearextrapolation extrapolationmethod methodwas wasemployed employedtotoextract extractthe theVVTH TH of of the SiRi pixels and the transistors. the SiRi pixels and the transistors. Table SiRi pixel devices studied in this work. TheThe thickness of the Table2.2.Geometrical Geometricalcharacteristics characteristicsofofthe the SiRi pixel devices studied in this work. thickness of SiRi sensors is 20 nm. a N-type pixel, a pixel, N-typeatransistor of L = 1 µm = 4 µm connected the SiRi sensors is 20Innm. In a N-type N-type transistor of and L =W 1 μm andisW = 4 μm to is aconnected N-type SiRi sensor of L = 1 µm and W = 1 µm. Similarly, in the P-type pixel, a P-type transistor of to a N-type SiRi sensor of L = 1 μm and W = 1 μm. Similarly, in the P-type pixel, a P-type L = 1 µm and 4 µm is connected toconnected a P-type SiRi L =sensor 1 µm and 1 µm. transistor of LW = 1= μm and W = 4 μm is to asensor P-typeofSiRi of LW = 1=μm and W = 1 μm. Type of of Pixel Type Pixel Type Typeof ofTransistor Transistor NN PP
NN PP
Transistor Dimensions Transistor Dimensions LL(μm) W (µm) W(μm) (µm) 11 44 11 44
Type Type of of SiRi SiRi
N N P P
SiRiDimensions Dimensions SiRi LL (μm) (µm) WW(μm) (µm) 11 11 11 11
4. Results and Discussion 4. Results and Discussion 4.1. IID-V G Transfer Characteristics of N- and P-Type Transistors 4.1. D -VG Transfer Characteristics of N- and P-Type Transistors Figure 66 shows shows the thewafer waferscale scaleIID-V -VG transfer characteristics (at VBG = 0 V) of standalone NMOS Figure D G transfer characteristics (at VBG = 0 V) of standalone NMOS and PMOS transistors manufactured using same fabrication process thepixels. SiRi The pixels. The and PMOS transistors manufactured using the the same fabrication process as theas SiRi NMOS NMOS andtransistors PMOS transistors a SSmV/dec. of 60–65The mV/dec. The Vextracted VTH for NMOS is in the and PMOS have a SShave of 60–65 extracted TH for NMOS is in the range from range from −0.3 to 0.3 V while the PMOS transistor has V TH in the range of −0.9 to −1.1 V. Figure 7A,B −0.3 to 0.3 V while the PMOS transistor has VTH in the range of −0.9 to −1.1 V. Figure 7A,B shows shows the ID-VG transfer characteristics of a single PMOS and NMOS device manufactured on SOI wafer at different VBG. In Figure 7A, the black color ID-VG curve of the PMOS is at VBG = 0 V. The positive VBG values cause the ID-VG transfer characteristics to shift to the left side (blue color) of the ID-VG curve at VBG = 0 V as the back interface is in accumulation. The VTH decreases by ~20–25 mV for 1 V change in VBG.
10-3 10-3 Drain 10-4 Drain Drain 10-4 Drain 10-5 10-5 10-6 10-6 10-7 10-7 10-8 10-8 10-9 10-9 10-10 10-10 10-11 10-11 10-12 10-12 10-13 10-13 -3 -3
voltage = 0.1 V for N-type voltage voltage = = 0.1 - 0.1VVfor forN-type P-type voltage = - 0.1 V for P-type
-2 -2
-1 -1
0 0
10-3 10-3 10-4 10-4 10-5 10-5 10-6 N-type transistor of 10-6 N-type transistor of 10-7 W = 4 µm, 10-7 W = 4 µm, L = 1 µm 10-8 L = 1 µm P-type transistor of 10-8 P-type transistor of 10-9 W = 4 µm, 10-9 W = 4 µm, L = 1 µm 10-10 L = 1 µm 10-10 10-11 10-11 10-12 10-12 10-13 -13 1 2 3 10 1 2 3
Drain current [A][A] Drain current
Drain current [A][A] Drain current
Similarly, in Figure 7B the black color ID-VG curve of the NMOS is at VBG = 0 V. The negative VBG values cause the ID-VG transfer characteristics to shift to the right side (red color) of the black curve as values cause the ID-VG transfer characteristics to shift to the right side (red color) of the black curve as the back interface is in accumulation. The VTH linearly increases by ~20−25 mV for 1 V change in VBG. the back interface is in accumulation. The VTH linearly increases by ~20−25 mV for 1 V change in VBG. The SS is only slightly influenced. Whereas the positive VBG values cause the ID-VG transfer The SS is only slightly influenced. Whereas the positive VBG values cause the ID-VG transfer characteristics to shift more towards the left side (blue color) of the ID-VG curve at VBG = 0 V as the characteristics to shift more towards the left side (blue color) of the ID-VG curve at VBG = 0 V as the Si/BOX interface inversion. At 50 V ≤ VBG ≤ 15 V, the frontgate control over the channel is Micromachines 2018, 9,approaches 544 8 of 14 Si/BOX interface approaches inversion. At 50 V ≤ VBG ≤ 15 V, the frontgate control over the channel is gradually lost causing the increase in SS. As a result, at VBG values >25 V, the transistor can no longer gradually lost causing the increase in SS. As a result, at VBG values >25 V, the transistor can no longer be turned off. For 15 V ≤ VBG ≤ 5 V, the VTH linearly depends on VBG and changes by ~100 mV for 1 V be off. For 15 V ≤ VBG ≤ 5 V, VTH linearly depends ondevice VBG and changes by ~100 mVwafer for 1 at V theturned ID -Vin transfer characteristics ofthe a single PMOS and NMOS manufactured on SOI GV change BG. change BG.. differentinVVBG
Frontgate voltage [V] Frontgate voltage [V]
10-2 (A) 10-2-3 10 P type transistor L = 1 µm, W = 2 µm(A) 10-3-4 P typevoltage transistor = 1Vµm, W = 2 µm Drain = - L0.1 10 Drain voltage = - 0.1 V 10-4-5 10-5 10-6 10 10-6-7 10 10-7-8 10 10-8-9 10-9 10-10 10-10 10-11 10 10-11 10-12 Substrate voltage = 0 V 5 Substrate V
