GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering
MOS Based Testing Of Gyrator-C Active Inductor Sneha Meti 1, Rohini Hongal 2 1
ENC Dept, BVBCET, Hubli. India ENC Dept, BVBCET, Hubli. India
2
E-mail Id:
[email protected],
[email protected]
ABSTRACT: This paper presents a systematic approach to test the gyrator-C active inductor using MOS transistor. The inductance, self resonance and quality factor of the gyrator-C active inductor test circuit are investigated by considering the low bias voltage. Practical implementations of the proposed gyrator-C active inductor are realized with 100mV, 0.18nm CMOS technology Keywords: Active inductor, self-resonant frequency (fSR), low-Q, High-Q. I. INTRODUCTION Active inductor provides high impedance for the higher frequency components contained in the impulse-like current so that these do not flow in the power supply bus. It is necessary to provide low impedance for these transients to flow via the decoupling capacitor. This is a well-known and commonly employed technique for reducing the supply noise in PC boards. If only decoupling capacitors are used, the filtering is only partially effective, and a residual part of the noise always flows through the PG bus owing to its inherent low impedance. The series inductor should have low output impedance at low frequencies to act as a good dc voltage source. As passive inductors require large chip area, active inductors are considered. Active inductors are popular in widely tunable VCOs and tunable filters. The basic parameter required for those applications is a high-Q factor [1]. A. High-Q Inductor
Figure 1: Capacitor loaded gyrator circuit used to obtain a high-Q active inductor It has an inverting transconductor[1] consisting of M1and a unity-gain current mirror (M3, M4) providing a current at the output port proportional to the voltage applied at the input port. The output port is loaded by a capacitor C1. The noninverting transconductor consists of a single transistor M2 operating in the common-source configuration. It converts the voltage across C1 to a current and makes it flow at the input as shown. This realizes an inductor of value c1/gm1gm2, where gm1 and gm2 are the small-signal transconductance of the transistors M1 and M2 respectively. The small output conductance at the two ports causes the Q to be finite but large. Both the value of the inductance and the Q are dependent on the bias currents IB1 and IB2 flowing in the transistors M1and M2, respectively. Such a high-Q inductor would cause the system to be highly under-damped and cause a lot of ringing on the power supply bus thus cannot be used. B. Low- Q inductor
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GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering
Figure 2: Low-Q inductors Figure 2 shows a few possible inductor circuits which offer a low Q. The two transconductance needed for a gyrator are obtained using two p-channel transistors M1 and M2. In high-Q inductors both the transistors are in common-source configuration. Since one of the transconductors must be noninverting, additional transistors (typically a current mirror) will be needed to do the inversion. In designing a low-Q inductor, use one of the transistors in its common-gate configuration. Thus, realized an inductor with just two devices. This makes the input impedance finite and causes the necessary low Q. All of the three circuits have low input impedance owing to the transistor operated in the common-gate configuration. All of them provide inductive behavior as each of the circuits act as a gyrator. The voltage at node X is converted into a small-signal current by M1, which is then integrated by the capacitor C1 , and, finally, a current proportional to the voltage across the capacitor is delivered back into node X by the transistor M2 operating in its common-source configuration. Circuits in (a) and (b) require only small-voltage headroom to operate, which would typically be around 100mV.The circuits in (b) and (c) are also not chosen because of a fixed current I flowing from the supply, even in the absence of any digital switching activity. The circuit in (c) has an added disadvantage in terms of a larger headroom requirement. The circuit in (a) supplies the current as demanded by digital gates and does not have a fixed rationed current I. In addition, the current I flows through the device M2 as well. Note that this current varies as per the current demanded at the node X, thus minimizing static power dissipation. The circuit in (a) is the best choice. Let us analyze the circuit in (a) in some more detail .Here the non-inverting trans conductance is provided by the commongate transistor M1 , the inverting trans conductance by the common-source transistor M and the gyration by capacitor C1. Neglecting the output resistances of M1 and M2, the inductive component [2] of the input impedance can be written as Zin= sC1/ gm1 gm2
(1)
Where gm1 and gm2 are the transconductance of PMOS devices M1 and M2, respectively. The inductor realized is directly proportional to the size of the capacitor C1 used. C1 is predominantly composed CGS of M2 and any additional capacitor used at the output port2. The inductance is also inversely proportional to the product of both of the transconductance. This would mean, for a smaller bias current IB , that a large inductor can be synthesized. A source–drain voltage, enough to keep in the device M2 in saturation, is required (100 mV). The two other important parameters of an inductor are its self resonant frequency and Q. The self-resonant frequency (fSR) is the frequency up to which the circuit has inductive impedance and beyond which it is capacitive. The parasitic capacitance at node X, which limits the self resonant frequency, is a combination of the gate–source capacitance of M1 and junction capacitance associated with the source and drain of M1 and M2, respectively. The self-resonant frequency can be written as fSR = 1/(2π(LCP)1/2)
(2)
A choice of large would improve current delivering capacity (reduce power overhead) at the cost of poor self resonance. The Q of the active inductor can be written as follows Q = ωCx / (gm1 +go2) = 1 / ωL (gm1 + go2)
(3)
Where Cx is the total capacitance at node X and g02 is the output conductance of M2. A low Q is achieved due the input resistance of the common-gate device M1. When the node X is loaded with decoupling capacitors, the Q of the active L-C circuit increases as the bandwidth of the L-C reduces more rapidly
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GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering II.TESTING THE FUNCTIONALITY OF INDUCTOR The estimate of the three parameters inductance (L) , self-resonant frequency(fSR) , and the Q at self-resonance. It can also be observed that decreasing the bias current IB can help reduce the Q, though this also reduces the self-resonant frequency. To achieve a higher fsr, a smaller inductance needs to be synthesized by using larger bias currents. To test the functionality of the active inductor, The active inductor is biased with an external current source IB, which is varied to observe the change in inductance.
Figure 3: Test setup to observe functionality of inductor The inductor is loaded by a dc current IL through a current mirror arrangement. To measure the self-resonant frequency and Q, an ac current (iac) is added to the load current. The ac current added is small-signal in nature, with a magnitude of 5% of the load current. The load current chosen was 100µA. The node X is sensed through a source follower. For the test setup, the bias current (IB) is varied from 0.5 to 3 µA. As the inductance decreases with bias current, observed an increase in self-resonant frequency. Q at self resonance increases with bias current (IB)[3]. Thus, both Q and the self-resonant frequency increase with increasing bias current. Varying the bias current to achieve the desired Q, but it does change the resonant frequency. III.RESULTS OF TESTING OF GYRATOR-C ACTIVE INDUCTOR ACROSS PROCESS CORNERS The test setups of the active inductor have been used to examine the parameters and characteristics of the principles, topologies, characteristics, and implementation of gyrator-C active inductors in CMOS technologies has been presented. To provide a quantitative measure of the performance of active inductors, a number of figure-of-merits have been introduced. These figure-of-merits include frequency range, inductance tunability, quality factor, noise, linearity, stability, supply voltage sensitivity, parameter sensitivity, signal sensitivity, and power consumption. Frequency range specifies the lower and upper bounds of the frequency in which gyrator-C networks are inductive. One of the key advantages of active inductors over their spiral counterparts is the large tunability of their inductance. Thus have shown that the inductance of gyrator-C active inductors can be tuned by varying either the transconductance or the load capacitance in the table 1, 2, 3, 4 and 5. The distinct sensitivities of the quality factor of active inductors to their parasitic series and parallel resistances have been investigated. The linearity of active inductors has been investigated. Because active inductors are active networks that are sensitive to both supply voltage fluctuation and parameter spread. Utilized the supply voltage sensitivity and parameter sensitivity to quantify the effect of these unwanted variations. To increase the tunability of active inductors, additional voltage controlled capacitors can be employed at critical nodes of active inductors.
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GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering Table 1: Observation table for the typical process corner VDD(V) VB(V) IB(µ A) L(H) FSR(HZ) Q
1.8
0
.523
6.271m 1.675m 1.143m
1.004M 1.943M 2.352M
1.144 1.904 2.118
1.8
100m
.523
4.955m 1.344m 0.925m
1.13M 2.1M 2.615M
1.27 2.046 2.243
1.8
300m
.523
2.598m 0.761m 0.655m
1.561M 2.882M 3.106M
1.662 2.374 2.395
Table 2: Observation table for the slow slow process corner VDD(V) VB(V) IB(µ L(H) FSR(HZ) Q A) 1.8
0
.523
6.122m 1.657m 1.139m
1.016M 1.954M 2.357M
0.585 0.378 0.363
1.8
100m
.523
4.628m 1.293m 0.903m
1.169M 2.212M 2.647M
0.523 0.367 0.352
1.8
300m
.523
2.149m 0.696m 0.518m
1.716M 3.013M 3.495M
0.405 0.342 0.344
Table 3: Observation table for the fast fast process corner VDD(V) VB(V) IB(µ A) L(H) FSR(HZ) Q 1.8
0
.523
6.423m 1.709m 1.163m
992.80k 1.924M 2.333M
1.288 0.732 0.639
1.8
100m
.523
5.240m 1.404m 0.960m
1.099M 2.123M 2.568M
1.171 0.677 0.597
1.8
300m
.523
3.062m 0.852m 0.594m
1.437M 2.725M 3.264M
0.916 0.566 0.515
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GJTE-Vol(2)-Issue(4)
April 2015
ISSN: 2393-9923
Global Journal of Trends in Engineering Table 4: Observation table for the slow Nmos fast pMOS process corner VDD(V) VB(V) IB(µ L(H) FSR(HZ) Q A) 1.8
0
.523
7.611m 2.010m 1.362m
912.03k 1.735M 2.155M
0.989 0.569 0.517
1.8
100m
.523
6.158m 1.641m 1.118m
1.013M 1.964M 2.379M
0.897 0.541 0.487
18
300m
.523
3.491m 0.976m 0.682m
1.346M 2.546M 3.046M
0.707 0.462 0.432
Table 5: Observation table for the fast nmos slow pmos process corner VDD(V) VB(V) IB(µ L(H) FSR(HZ) Q A) 1.8
0
.523
5.159m 1.399m 0.964m
1.107M 2.127M 2.562M
0.767 0.475 0.432
1.8
100m
.523
3.960m 1.101m 0.768m
1.264M 2.397M 2.871M
0.684 0.442 0.411
1.8
300m
.523
1.900m 0.597m 0.439m
1.825M 3.256M 3.797M
0.514 0.389 0.380
IV. CONCLUSION The approach in this paper is often preferable over those that vary the transconductance of active inductors because the latter also alters other parameters of the active inductors such as inductance with a downside that the tuning range is rather small. Functionality of Gyrator-C active inductor satisfies completely for the typical (tt) process corner & varies by 0.74 for the other process corners compared to typical process corner. ACKNOWLEDGMENT The authors would like to thank our PG students Meenaxi T. Jyoti M.H and Kishan P for their discussion and support in this work. REFERENCES [1] Ajay Taparia, Member, IEEE, Bhaskar Banerjee, Member, IEEE, and T. R.Viswanathan , IEEE “Power-supply noise reduction using active inductors in mixed-signal systems,” IEEE Transactions on very large scale integration (VLSI) systems, VOL. 19, NO. 11, NOVEMBER 2011. [2] A. Taparia, T. R. Viswanathan, and B. Banerjee, “Active inductor for power supply decoupling in mixed signal systems,” in Proc. IEEE Dallas Circuits Syst. Workshop, 2008, pp. 1–4. [3] D. A. Johns and K. Martin, “Analog Integrated Circuit Design,” NewYork: Wiley, 1997.
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