MoS2 interlayer tunneling field

Solid-State Electronics 126 (2016) 96–103

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Vertical MoS2/hBN/MoS2 interlayer tunneling field effect transistor Ashok Srivastava ⇑, Md S. Fahad Division of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803, USA

a r t i c l e

i n f o

Article history: Received 10 March 2016 Received in revised form 17 August 2016 Accepted 13 September 2016 Available online 17 September 2016

a b s t r a c t Gate induced interlayer tunneling field effect transistor (iTFET) is studied analytically considering vertical heterostructure of boron nitride (BN) layer sandwiched between two monolayers of molybdenum disulfide (MoS2). The device structure in comparison to recently reported work shows subthreshold slope close to 60 mV/decade and operation at upper GHz. Ó 2016 Elsevier Ltd. All rights reserved.

Keywords: Vertical interlayer MoS2 FET hBN Tunnel FET

1. Introduction Moore’s law for scaling of planar metal oxide semiconductor field effect transistor (MOSFET) is predicted to face its formal end [1]. In addition to shrinking MOSFET channel length to sub10 nm for high transistor density, vertical integration of MOSFETs based on stacking of two dimensional layered materials have recently been explored [2–16]. Novel two dimensional material systems such as graphene and non-graphene have largely made this feasible [17]. These transistors hold the promise for vertical integration, providing an alternative approach for maintaining the lifeline of Moore’s law and beyond. Compared to conventional inversion mode of operation, field effect tunneling based current transport has been studied in these vertical FETs. Majority of these vertical FETs consider two graphene layers separated by a thin tunnel barrier, mostly hex boron nitride (hBN). Considering Bose condensation of Fermions (electron-hole pairs) between two graphene layers, BiSFET proposed by Banerjee et al. [5] was one of the theoretical graphene based interlayer FETs. The theoretical model of an interlayer tunneling transistor, SymFET, proposed by Zhao et al. [7] was another graphene/hBN heterostructure. With an on/off current ratio of 100, SymFET provides a large resonant current peak. However, the model in [7] does not provide any insight of SymFET subthreshold slope. Operating frequency of SymFET was also not reported in [7]. Recently, Fiori et al. [9] have studied very large current modulation in graphene/hBN vertical heterostructure from the multi-scale simulation approach. A large subthreshold slope of 385 mV/decade with

⇑ Corresponding author. E-mail addresses: [email protected], [email protected] (A. Srivastava). http://dx.doi.org/10.1016/j.sse.2016.09.008 0038-1101/Ó 2016 Elsevier Ltd. All rights reserved.

an on/off current ratio of 15 are reported. The intrinsic cut-off frequency also falls below 1 GHz. Ghobadi and Pourfath [10] studied a vertical heterostructure similar to [9] considering both graphene and quantum confined graphene nanoribbon (GNR) separated by hBN with a focus on high frequency operation. However, low on/off current ratio (3–10) and high subthreshold slope (>1000 mV/decade) were obtained for 100 GHz cut-off frequency. Compared to graphene, atomically thin molybdenum disulfide (MoS2) based planer FET has already shown promise [18–21]. However, unlike graphene, study of vertical FET based on interlayer tunneling between two MoS2 layers separated by a thin tunnel barrier has remained largely unexplored. In this work, a gate induced interlayer tunneling field effect transistor (iTFET) is studied considering MoS2/hBN/MoS2 for reduced subthreshold slope and sustainable leakage. The interlayer tunneling based barrier control mechanism proposed in [16] is used for the current transport study of MoS2/hBN/MoS2 iTFET through self-consistent simulation method. As opposed to bulk oxide, multilayer hBN is considered as the gate dielectric. We have compared the performance of iTFET with the earlier reported graphene based heterostructures reported in [9,10].

2. Device structure and operation Fig. 1 shows schematic of iTFET where the channel is a monolayer MoS2 of 10 nm length and 5 nm width. Following the work in [3,16], gate dielectric comprises of 20 layers of hBN (7 nm). Monolayer hBN is considered as the vertical tunneling barrier between two MoS2 layers. We assume that both the top and bottom (channel) MoS2 are a single layer. Compared to conventional

97

A. Srivastava, M.S. Fahad / Solid-State Electronics 126 (2016) 96–103

Fig. 1. Schematic of MoS2/hBN/MoS2 interlayer tunnel field effect transistor (iTFET). The dash line AA0 refers to vertical direction of interlayer tunneling and BB0 refers to lateral direction of source-drain ballistic transport.

interlayer tunneling field effect transistor, MoS2 iTFET considers source and drain contacts on bottom MoS2 layer. Recently, in a graphene switching transistor such design has been proposed which provides interlayer tunneling dependent channel barrier control mechanism [16]. Following the work in [16], MoS2 iTFET also explores such design. Recently, it has been experimentally observed that chemical vapor deposition based direct growth of monolayer MoS2 on hBN provides smaller lattice strain, low doping level and clean and sharp interface [22]. Moreover, monolayer MoS2 is stable over monolayer hexagonal BN (hBN) substrate for an inter-planer distance of 4.89 Å [23]. Based on density functional theory (DFT), an energy bandgap of 1.83 eV is observed between the MoS2 and hBN [23]. This is little more than the energy bandgap (1.5 eV) between graphene and hBN valence bands. A hybridization between dxy orbital of MoS2 and the pz orbital of hBN originates such band gap [23]. Recently, it is demonstrated that monolayer MoS2 retains high carrier mobility free of surface scattering on hBN substrate. The layer hBN protects MoS2 layer from Coulomb scattering from charge impurities in SiO2 [24].

In a fully planar two dimensional FET based on layered semiconductors, hBN has also been used as the top gate dielectric layer providing superior gate control over the channel [25]. Therefore, we have considered hBN as both top and bottom gate dielectric in iTFET. Experimentally it is found that single layer hBN is a potential candidate for interlayer tunneling barrier for vertical tunnel transistor [26,27]. Such thin tunnel barrier not only allows wave function extension between two semiconducting layers but also preserves the coherent length of tunneling [4]. Operation of iTFET is twofold [16], i.e. (a) gate bias (VG) between top and bottom MoS2 layers initiate the vertical interlayer tunneling of carriers which changes the channel Fermi level and (b) the corresponding shift in channel Fermi level controls the height of the barrier between source and drain. In Fig. 1, dashed line A-A0 refers to vertical direction of interlayer tunneling and B-B0 refers to the lateral direction of source-drain ballistic transport. Fig. 2(a) and (b) shows the MoS2/hBN vertical energy band diagram for VG = 0 V and |VG| – 0 V, respectively. For VG = 0 V, Fermi levels of both top and bottom MoS2 layers are assumed to be in equilibrium as shown in Fig. 2(a). As bias is applied between these two layers, the tunnel barrier hBN screens out some electric field, however, a shift in Fermi level at the bottom (channel) MoS2 layer is still observed. This is shown in Fig. 2(b). As the gate bias is applied, a finite amount of carrier tunnels from top MoS2 layer to bottom MoS2 which is estimated as follows [28],

Z

D/

N1 ¼ 0

qMoS2 TT ðEÞf t ðEÞdE

ð1Þ

Similarly tunneling of carriers from bottom MoS2 to top MoS2 layer is estimated from,

Z

D/

N2 ¼ 0

qMoS2 TT ðEÞf b ðEÞdE

ð2Þ

The net amount of tunnel carrier concentration at the bottom MoS2 channel is described as follows,

Z

D/

N¼ 0

qMoS2 TT ðEÞðf t ðEÞ f b ðEÞÞdE

ð3Þ

where qMoS2 = gsgvmMoS2 /(2p⁄2) is density of states (DoS) in MoS2, gs(=2) and gv(=2) are spin and valley degeneracy, respectively, mMoS2 is effective mass in MoS2 (0.57mo) and ⁄ is reduced Planck’s constant [29]. TT(E) is tunneling probability between two MoS2

Fig. 2. (a) Energy band diagram along vertical AA0 direction in off state and (b) in on state. Note: D/ denotes change in Fermi level at bottom (channel) Fermi level.

98


layers through hBN barrier and ft(E) and fb(E) are Fermi functions at the top and bottom MoS2 layers (with the generic expression of (1/(1 + exp((E-EF)/kBT))) and kB is Boltzmann’s constant), respectively. Interlayer tunneling probability is determined as in [6],

pffiffiffiffiffiffiffiffiffiffiffiffiffi TT ðEÞ ¼ expð2d 2m D=hÞ

ð4Þ

where d is the thickness of the tunnel barrier (1.3 nm in this work), m⁄ is carrier effective mass inside the barrier (=0.5mo inside hBN) [3] and D is height of the tunneling barrier (1.83 eV between MoS2 and hBN) [23]. Effective change in Fermi level of the bottom MoS2 layer (which is also the channel MoS2 layer) is expressed as D/. Using proper limits of integration, net carrier concentration (N) from Eq. (3) is integrated as follows,

N¼

2qVT mMoS2

pðhÞ2

D/ D/ þ lnð4=1 þ exp TT ðEÞ ln 1 þ exp VT VT ð5Þ

where VT (=kBT/q) is the thermal voltage. Compared to a doped MoS2 layer, we have estimated the position of Fermi level for a biased and non-doped MoS2 channel. The objective is to study the gate induced channel degeneracy due to an applied bias in an intrinsic MoS2 layer. For a positive bias, an n-type degeneracy in channel Fermi level is observed whereas for a negative bias, ptype degeneracy in channel Fermi level is observed. Change in Fermi level in n-type channel is determined as follows [29],

EFn ¼ EC þ qVT ln½expðN=ðqMoS2 kB TÞÞ

ð6Þ

and in p-type, the expression is,

EFp ¼ EV qVT ln½expðN=ðqMoS2 kB TÞÞ

ð7Þ

In both types of interlayer tunneling transistors and vertical band-to-band tunneling transistors, tunneling phenomena is dependent on temperature [6,19]. Using Eqs. (4)–(7), Fig. 3(a) is plotted which shows the change in Fermi level with temperature at different interlayer gate biases. Fig. 3(b) shows the induced carrier concentration from interlayer tunneling. It is found that Fermi level curve for an intrinsic MoS2 channel biased at 0.74 V matches with the that of an unbiased MoS2 channel doped at 1017/cm2. Considering the band gap of 1.8 eV of single layer MoS2, the conduction or valence band lies at ±EG/2. However, using interlayer tunneling technique, the Fermi level of an intrinsic MoS2 can shift above the conduction band or below the valence band for positive or negative gate bias, respectively. Temperature effect on carrier concentration is also studied in Fig. 3(b). The zero gate bias carrier concentration increases as the temperature increases and gets saturated at higher gate bias. At

high temperature, more carriers gain higher energy resulting in interlayer tunneling between the two MoS2 layers which raises the zero bias carrier concentration. Furthermore, impurity scattering and electron-hole interaction at higher gate bias cause the carrier concentration to saturate. 3. Estimation of drain current The effective change in channel Fermi level not only depends on gate bias but also on associated voltage drops between the two gate contacts [29]. In order to model and calculate drain current of iTFET, these voltage drops are necessary to calculate as follows in this section. The voltage drop in the channel (Vch) due to interlayer tunneling charge density (N), is determined as follows [29],

Vch ¼ Vo VT ln½expðN=ðqMoS2 kB TÞ 1

ð8Þ

where V0 = E0/q and E0 = EG/2 [29]. We refer the channel charge induced voltage drop along A-A0 as in [29],

VV ¼ qN=CV

ð9Þ

where CV is net vertical capacitance between top and bottom gate electrodes. Having similarity with MOSFET, iTFET is also assumed to suffer the effect of drain induced barrier lowering (DIBL). We consider DIBL as,

k ¼ aVDS

ð10Þ

where a lies between 0 and 1 where 0 stands for no drain bias effect and 1 stands for full drain bias effect [30]. Now the effective change in channel Fermi level D/ becomes,

D/ ¼ VG Vch VV k

ð11Þ

Eq. (11) is dependent on Eq. (5) and is a transcendental equation which needs to be solved both numerically and self-consistently. Considering transverse mode along the channel for an energy window between 0 and D/, using Landauer’s expression, drain current of iTFET can be written as follows [30],

Z

I¼

dE½ðGðEÞðf S ðEÞ f D ðEÞÞÞ

ð12Þ

Here G(E) is channel conductance and expressed as,

GðEÞ ¼ ð2q2 =hÞTB ðEÞMðEÞ

ð13Þ

where fS(E) and fD(E) are source and drain Fermi levels, respectively. TB(E) is the transmission coefficient in the channel and is taken 1 for the ballistic transport. M(E) is the number of modes in the channel and written as follows [31],

Fig. 3. (a) Change in Fermi level in n-type (above 0 eV) and p-type (below 0 eV) for a single layer (SL) MoS2 channel with change in temperature (T) for different gate bias (VG). The Fermi level for a doped SL-MoS2 of ns = 1 1017/cm2 at zero gate bias matches with non-doped SL-MoS2 iTFET operating at |VG| = 0.74 V. (b) Induced interlayer tunnel carrier concentration (N) with change in gate bias (VG) for different temperatures (T).

99


qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi MðEÞ ¼ gv W 2mMoS2 ðE EC Þ=ph

ð14Þ

where W is the width of the channel and EC is position of the channel conduction band. Combining Eqs. (12)–(14), drain current becomes,

Z ID ¼

dE

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2q2 g W 2m ðE E Þ ðf ðEÞ f ðEÞÞ C S D v MoS2 ph2

ð15Þ

The Fermi functions in the source and drain are described as follows,

f S ðEÞ ¼

1 1þe

and f D ðEÞ ¼

ð16Þ

ðEEsF Þ=kB T

1 D

1 þ eðEEF Þ=kB T

ð17Þ

Eq. (15) becomes,

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Z pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðE EC Þ ðE EC Þ 2q2 ID ¼ g W 2m dE v S D MoS2 1 þ eðEEF Þ=kB T 1 þ eðEEF Þ=kB T ph2

Now considering,

n ¼ ðE EC Þ=kB T

ð19Þ

gFS ¼ ESF EC =kB T

ð20Þ

gFD ¼ EDF EC =kB T Drain current in Eq. (18) can be written as,

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi q2 ID ¼ pffiffiffiffi 2 gv W 2mMoS2 qVT ½I1=2 ðgFS Þ I1=2 ðgFD Þ ph 2 where I1=2 ðgFS Þ ¼ pffiffiffiffi 2 and I1=2 ðgFD Þ ¼ pffiffiffiffi

ð18Þ

ð21Þ

p

Z

p

0

Z

D/

0

D/

n1=2 dn 1 þ eðngFS Þ

n1=2 dn 1 þ eðngFD Þ

ð22Þ

ð23Þ

ð24Þ

Both Eqs. (23) and (24) are the expressions of Fermi-Dirac integral of order 1/2 which needs to be solved numerically. Solving Eq. (22) for n from 0 to D/, drain current can be written as,

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffi pffiffiffiffiffiffi 2q2 I ¼ pffiffiffiffi 2 W 2mMoS2 qVT ½ v1 v2 ph

ð25Þ

v1 ¼ ðD/ EC Þ½lnð1 þ expðD/ EDF ÞÞ lnð1 þ expðD/ ESF ÞÞ ð26Þ

v2 ¼ ðEC Þ½lnð1 þ expðEDF ÞÞ lnð1 þ expðESF ÞÞ

ð27Þ

From Eq. (25), the drain current depends on both Eqs. (5) and (11) for which it needs to be solved self-consistently in order to account for both interlayer tunneling induced charge density and sourcedrain ballistic transport. 4. Results and discussion Fig. 4. Transfer characteristics of iTFET. (a) ID-VG curve for different drain biases (VDS) and (b) ID-VG curve for different number of hBN layers as tunnel barrier between top and bottom MoS2 layers. Inset in (b) shows drain current for complete bias operation where effect of number of hBN layers on drain current are nondifferentiable.

Using Eqs. (5), (11) and (25), transfer characteristics of iTFET are plotted in Fig. 4. A small negative differential resistance (NDR) region is observed at different drain bias at room temperature as shown in Fig. 4(a). For VDS = 1.2 V, an on/off current ratio of 17 with

Fig. 5. (a) Energy band diagram of bottom (channel) MoS2 layer in equilibrium at off-state, (b) energy band diagram at on-state for qVG > 0 and (c) energy band diagram at onstate for qVG < 0. Red arrow points for thermionic transport and green arrow for band-to-band tunneling transport. BB0 refers to lateral direction of ballistic transport between source and drain. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

100


Fig. 6. Output characteristics of iTFET. (a) ID-VDS curve for different gate biases (VG) and (b) ID-VDS curve for different number of hBN layers as tunnel barrier between top and bottom MoS2 layers.

Fig. 7. (a) Gate bias dependent field effect mobility in iTFET and (b) capacitive network of iTFET.

a subthreshold slope of 57 mV/decade is obtained for VG > 0 which is 70 mV/decade for VG < 0 with an on/off current ratio of 18. The off-state leakage current of iTFET is calculated as 27.2 lA for VDS = 1.2 V. Subthreshold slope is calculated from SS = log(10)[ID/ (dID/dVG)], where ID is the drain current and VG is the gate bias. Compared to a conventional MOSFET, a reduced subthreshold slope at low on/off current ratio in iTFET is observed and explained through Fig. 5(a)–(c).

The intrinsic MoS2 channel in Fig. 5(a) considers the source (EFS), channel (EFC) and drain (EFD) Fermi levels in equilibrium. As the negative gate bias (VG < 0 giving qVG > 0) is applied, the degenerately doped (from interlayer tunneling) n-type channel Fermi level (EFC) moves down which is shown in Fig. 5(b). The |qVDS| is the amount of shift between EFS and EFD due to drain-source bias. Similar to a MOSFET, thermionic transport (red arrow) dominates the source-drain ballistic transport. For this reason, a subthreshold slope more than the thermionic limit of 60 mV/decade is observed. We assume a small amount of phonon assisted indirect band-toband tunneling (BTBT) which occurs between source and channel and is shown by a single green arrow in Fig. 5(b). Note that similar BTBT contributes toward the NDR trend which is also found in ATLAS TFET for a p+ Ge source and n-MoS2 channel [19]. As the positive gate bias (VG > 0 giving qVG < 0) is applied, the degenerately doped (from interlayer tunneling) p-type Fermi level (EFC) of the channel moves below the channel valence band. Hence, the channel valence band comes opposite to the drain conduction band and channel-drain BTBT is occurred. A subthreshold slope of 57 mV/decade is observed due to this BTBT dominated drain current which is shown by green arrow in Fig. 5(c). Number of hBN layers as tunnel barriers also affects iTFET transfer characteristics which is studied in Fig. 4(b). As the number of hBN layers as tunnel barrier increases, the tunneling probability exponentially decreases which results in less charge density. Therefore, with a shallow degeneracy, less NDR is observed at higher number of hBN layers. The output characteristics of iTFET are plotted in Fig. 6(a) and (b) considering change of gate bias and change in number of hBN layers, respectively. Since operation of iTFET is more controlled by the gate bias than drain bias, insignificant effect is observed in output characteristics as the number of hBN layers varies in Fig. 6(b). Compared to benchmarked performance of monolayer MoS2 transistor [20,21], iTFET provides low on/off current ratio. This can be understood from the field effect mobility (lFE) diagram in Fig. 7(a). Field effect mobility is estimated from lFE = dID/dVG(L/W) (1/CG), considering both quantum and geometric capacitances [29]. As VG increases, lFE drops. Based on semi-classical Drude formula, conductivity r(=lFENq) is linearly dependent on lFE. Therefore, as the channel MoS2 becomes degenerately doped, conductivity drops as lFE decreases. Moreover, we study the metal-insulator transition in the channel MoS2 layer of iTFET which can be understood by Ioffe-Regel criterion [32,33]. According to this criterion, MoS2 is metallic for kFle 1 and is insulating for kFle 1. Here p kF = (2pN) is Fermi wave vector and le = ⁄kFr/Nq2 is the mean free path [32]. We choose two points (VG = 0.2 V and 0.5 V)

Fig. 8. (a) Change in channel quantum capacitance (Cqch) and total gate capacitance (CG) with gate bias (VG) for different temperature. Note: Non-channel fixed vertical capacitance (CV) is shown in green line and (b) intrinsic cut-off frequency (fT) variation with change in gate bias (VG). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

101


Fig. 9. (a) Intrinsic gate delay (s) versus the gate bias (VG) and (b) corresponding power delay product (PDP) for different temperatures.

between which the mobility drops and check this criteria. Using Fig. 7(a), we found at VG = 0.2 V, kFle 294 (1); and at VG = 0.5 V, kFle 5.16 104 ( 1), providing a metal-insulator transition in the channel MoS2 layer at high gate bias. Therefore, a low on-state drive current is obtained resulting in low on/off current ratio in iTFET. The low subthreshold slope of iTFET is comparable with the standard MOSFET subthreshold slope of

60 mV/decade. However, metal insulator transition and mixed mode of thermionic and BTBT current transport limits achieving high on/off current ratio in iTFET. The capacitance network for the iTFET is shown in Fig. 7(b). The total gate capacitance is estimated as follows: 1/CG = 1/CV + 1/Cqch where 1/CV = 1/(C1 + C2) + 1/(C3 + C4) + 1/(C5 + C6) + 1/(C8 + C9) considering series-parallel network of all the vertical capacitances. The geometric and quantum capacitances of top and bottom gate hBN layers and top MoS2 layer are expressed as C1 = C8 = e0ehBN/(ZgthBN), C2 = C9 = Cq,hBN/Zg, C3 = e0eMoS2/tMoS2 and C4 = Cq,MoS2 = q2qMoS2, respectively. Cq,hBN = q2qhBN (where qhBN = gsgv mhBN /(2p⁄2)) is the quantum capacitance of single layer hBN [34]. Zg is the number of hBN layers (Zg=20) in gate dielectric in AA0 direction. Similarly, the geometric and quantum capacitances of the single layer hBN as tunnel barrier are expressed as C5 = e0ehBN/(ZtthBN) and C6 = Cq,hBN/Zt (where Zt is the number of hBN layers (Zt = 1) in tunnel barrier), respectively. C10 and C11 are source and drain quantum capacitances of MoS2. Note that tMoS2 (=0.65 nm) and eMoS2(=2.8) [35], thBN(=0.325 nm) and ehBN(=4) are the thickness and dielectric permittivity of MoS2 and hBN, respectively. Based on the work of Ma and Jena in [29], the gate dependent channel quantum capacitance (Cqch) is estimated as follows,

Table 1 Comparison of iTFET performance with earlier similar models. Parameters

Fiori et al. Ref. [9]

VTGFET Ref. [10]

VTGNRFET Ref. [10]

This Work

Gate voltage #hBN layers Subthreshold slope Ion/Ioff Cut-off frequency

1.2 V 3 386 mV/decade 15 0.5 GHz

1.2 V 3 1535 mV/decade 3 58 GHz

1.2 V 3 1297 mV/decade 4 97 GHz

1.2 V 3 57 mV/decade 17 19.73 THz

Table 2 Comparison of iTFET with existing two dimensional high frequency devices. Ref. [Year]

Device Transport Type

Material system/ channel

Channel length/tunneling barrier thickness

Bias voltage

On/off current ratio (if any)

Operating frequency

[9] [2013]

iTFET

15

0.5 GHz

iTFET

1.2 V

4

97 GHz

[36] [2016]

FET

1.03 nm (tunneling barrier thickness) 1.03 nm (tunneling barrier thickness) 1 lm (channel)

1.2 V

[10] [2014]

Graphene-hBNgraphene GNR-hBN-GNR

2V

105

5.6 GHz

[38] [39] [40] [41] [42] [43]

FET FET FET FET FET FET

500 nm (channel) 240 nm (channel) 40 nm (channel) 140 nm (channel) 40 nm (channel) 100 nm (channel)

1.6 V 2V 1V 1V 1.5 V 0.8 V

2 300 800 3 800 2

4 GHz 8.2 GHz 1.5 THz 300 GHz 155 GHz 110 GHz

2–5 nm (SiO2 tunneling barrier thickness) 2 nm (Al2O3 tunneling barrier thickness) 20 nm (channel)

1V

104

1 THz

[2009] [2014] [2012] [2010] [2011] [2013]

[44] [2013] [45] [2013] [46] [2015] [47] [2012] [48] [2016]

[49] [2014] [50] [2012] [51] [2014] [52] [2014] [53] [2015] This work

BJT type Hot electron transistor TFET TFET Interlayer excitonic generation FET iTFET-plasma resonance based FET FET FET iTFET-interlayer tunneling based barrier control

CVD MoS2 on flexible substrate Graphene MoS2 Bilayer graphene Graphene Graphene Epitaxial graphene from SiC Graphene base heterojunction Graphene base Graphene nanoribbon (GNR) Graphene-hBCN MoS2-hBN-MoS2

Black phosphorus Graphene-barriergraphene Bilayer graphene Exfoliated MoS2 on SiO2 CVD MoS2 on SiO2 MoS2-hBN-MoS2

5

1.5 V

>10

Unspecified

0.1 V

122

1 THz

7 nm (channel) 5 nm (tunneling barrier thickness)

0.6 V –

104 –

2 THz –

300 nm (channel) 10 nm (tunneling barrier thickness) 500 nm (channel) 2.5 lm (channel) 68 nm (channel)

2V 0.5 V

2 103 Unspecified

12 GHz 1.42 THz

0.001 5V

Unspecified 104

0.29–0.38 THz 42 GHz

3.5 V 1.2 V

200 17

6.7 GHz 19.73 THz

250 nm (channel) 10 nm (channel) 1.03 nm (tunneling barrier thickness)

102

Cqch ¼ C7 ¼ q2 qMoS2 1 þ


1 expðEG =2kB TÞ 2 cos hðqD/=kB TÞ

ð28Þ

Using Eqs. (5) and (11), Eq. (28) is solved and is plotted in Fig. 8(a). For VG = 1.2 V, CG is estimated to be 0.0952 F/m2. Intrinsic cut-off frequency (fT = gm/2pCG) dependence on gate bias is shown in Fig. 8(b) for transconductance, gm = dID/dVG. For a supply voltage of 1.2 V, we have calculated fT = 19.73 THz which increases as VG reduces. This value is higher than the reported fT in [9,10]. Intrinsic frequency of MoS2 transistors is independent of on/off current ratio [36,37] and is related to gate capacitance. From Fig. 8(a), the gate capacitance (CG) is nearly two orders less than the channel quantum capacitance (Cqch) for which iTFET achieves very low gate capacitance providing high intrinsic cut-off frequency. Using s = CGVDD/ION, intrinsic gate delay is plotted in Fig. 9(a) from which the power delay product (PDP = sVDDION) is plotted in Fig. 9(b). From Figs. 8(b) and 9(a), beyond THz operation of iTFET can be observed. Performance of iTFET is compared in Table 1 with the results reported in [9,10] for an equal number of hBN layers as tunnel barrier and gate bias. In terms of subthreshold slope, iTFET provides 7 and 27 times less than that of the reported in [9,10], respectively, for graphene vertical FETs. Due to a small band gap at 5 nm width, subthreshold slope of iTFET is 23 times less than that of the vertical GNR FET reported in [10]. Compared to both [9,10], iTFET provides THz operation due to very low gate capacitance. The on/ off current ratio is nearly the same as reported in [9,10]. Furthermore, high frequency performance of this iTFET is also compared with the existing two dimensional materials (both graphene and non-graphene) based high frequency devices and is summarized in Table 2. Based on the data in Table 2, iTFET outperforms other devices at a comparable supply voltage, on/off current ratio and channel length. The only similar device structure like MoS2/hBN/MoS2 iTFET is found in the work of Calman et al. [48] which studies controlled excitonic generation in similar van der Waals heterostructure. However, the work in [48] does not account for any high frequency performance estimation and transistor type electronic behavior and hence become unsuitable for comparison. The high frequency performance of MoS2/hBN/MoS2 iTFET originates from interlayer tunneling based barrier control mechanism and use of two dimensional layered materials (in this work hBN) as the gate dielectric providing low gate-capacitance. 5. Conclusion Current transport is studied in MoS2/hBN/MoS2 iTFET which is controlled by the gate induced interlayer tunneling dependent charge density unlike inversion mode operation in MOSFETs. The current transport between source and drain is ballistic. Compared to recently reported device structures in [9,10], the present device structure gives subthreshold slope close to 60 mV/decade and demonstrates upper GHz operation with relatively comparable on/off current ratio. Low bandgap insulator or wide bandgap layered semiconductor materials can be used as interlayer tunneling barrier to improve the on/off current ratio and making iTFET suitable for digital applications. A comparison of performance of iTFET with other types of device structures exhibits superior performance and promise of ultra-low power and high-frequency operation. References [1] Waldrop M. The chips are down for Moore’s law. Nature 2016;530:144–7. [2] Sachid AB, Tosun M, Desai SB, Hsu C-Y, Lien D-H, Madhvapathy SR, et al. Monolithic 3D CMOS using layered semiconductors. Adv Mater 2016;28:2547–54.

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