MOSFET hot-carrier reliability improvement by forward ... - IEEE Xplore

IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 7, JULY 2006

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MOSFET Hot-Carrier Reliability Improvement by Forward-Body Bias Akira Hokazono, Member, IEEE, Sriram Balasubramanian, Student Member, IEEE, Kazunari Ishimaru, Senior Member, IEEE, Hidemi Ishiuchi, Member, IEEE, Chenming Hu, Fellow, IEEE, and Tsu-Jae King Liu, Senior Member, IEEE

Abstract—Active threshold voltage VTH control via well– substrate biasing can be utilized to satisfy International Roadmap for Semiconductors performance and standby power requirements for CMOS technology beyond the hp65-nm node. In this letter, the impact of substrate bias VSUB on hot-carrier reliability is presented. The impact varies with the gate length and body effect factor. These findings are explained, and the effects of future scaling are discussed using a quasi-two-dimensional model. Significant and important improvement in hot-carrier lifetime with forward-bias VSUB can be expected for deeply scaled CMOS devices, making it an attractive method for extending the scalability of bulk-Si transistor technology. Index Terms—Forward-body bias, hot-carrier reliability, MOSFET, reverse-body bias, substrate bias.

I. I NTRODUCTION YNAMIC threshold voltage (VTH ) control achieved by active-well biasing [1]–[3] is an attractive approach to meet International Roadmap for Semiconductors (ITRS) performance specifications for sub-hp65 nm CMOS technologies. In particular, forward-well biasing is attractive for extending the scalability of bulk-Si CMOS technology [2], [3]. As the lateral dimensions of a MOSFET are scaled down with each technology node, the peak electric field near the drain junction increases. Therefore, the impact of well–substrate bias (VSUB ) on hot-carrier reliability is of potential concern. A casual consideration of the effect of VSUB on the electric field in the drain region suggests that a forward-bias VSUB (VF ) should improve hot-carrier reliability, whereas a reverse-bias VSUB (VR ) should degrade it. Therefore, VR should not be preferred for dynamic VTH control. From Flash electrically erasable programmable read-only memory (EEPROM) technology [4], it is well known that hot-carrier injection is enhanced by application of VR but that scaling of the gate length LG makes this enhancement weak. Togo et al. [5] showed that a reverse-bias

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Manuscript received March 6, 2006; revised April 21, 2006. The review of this letter was arranged by Editor E. Sangiorgi. A. Hokazono is with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720-1770 USA, and also with the SoC Research and Development Center, Toshiba Corporation Semiconductor Company, Yokohama 235-8522, Japan. S. Balasubramanian, C. Hu, and T.-J. King Liu are with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720-1770 USA. K. Ishimaru and H. Ishiuchi are with the SoC Research and Development Center, Toshiba Corporation Semiconductor Company, Yokohama 235-8522, Japan. Digital Object Identifier 10.1109/LED.2006.877306

VSUB (VR = −2 V) did not degrade the hot-carrier lifetime of nMOS devices with LG = 50 nm. Another issue to be considered, however, is the phenomenon of photon emission resulting from impact-ionization under VR , which can affect adjacent devices [6]. In this letter, the gate-length dependence of hot-carrier reliability under well–substrate biasing is evaluated, and the use of forward-well biasing to improve hot-carrier reliability is proposed. For long-channel MOSFETs (LG > 100 nm), a significant degradation in the hot-carrier lifetime under VR and an improvement under VF were observed. In contrast, the dependence of hot-carrier reliability on VSUB is small for very short-channel MOSFETs (LG = 40 nm). The difference in reliability dependence on VSUB can be explained using a quasi-two-dimensional (2-D) model of the electric field in the drain region [7] and considering the substrate bias effect factor. II. D EVICE F ABRICATION AND C HARACTERIZATION Complementary MOSFETs (CMOSFETs) fabricated using hp45-nm-node technology were used in this letter. The gate dielectric was SiOx Ny [1.1-nm equivalent oxide thickness (EOT)], which was formed by plasma nitridation of 0.8-nm SiO2 . Following the formation of poly-Si gate electrodes, offset spacers were formed beside the gate electrodes. Next, source– drain extension ion implantations were performed, wherein the offset spacers delineated the implanted areas. After the formation of gate sidewalls (which are 45 nm wide), the source–drain contact junctions were formed by high-dose ion implantation and spike annealing. Front-end processing was completed with a nickel salicide process. DC hot-carrier stress of various levels was applied to nMOS and pMOS devices under the bias stress condition of VGS = VDS . This is clearly the worst case degradation bias condition for short-channel MOSFETs with LG < 110 nm. On the other hand, for long-channel MOSFETs, the worst case bias condition was not clear when comparing degradation under the VGS = VDS condition with that under the condition where VGS corresponds to the peak substrate current (ISUB ), which is consistent with previous work [8]. Interface state generation is the primary source of degradation in short-channel devices, and the charge pumping analysis showed that more interface states were generated under the VGS = VDS condition than the bias condition at peak ISUB [9]. Thus, VGS = VDS was used as the worst case degradation bias stress condition in this letter. The maximum voltage for a ten-year lifetime, which is defined

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Fig. 1. Dependence of hot-carrier reliability on substrate bias for short-and long-channel MOSFETs. (a) nMOS. (b) pMOS. The gate dielectric is plasmanitrided SiOx Ny (1.1-nm EOT).

as the time required to reach 10% degradation in peak linear transconductance gm,lin , was compared for various devices and substrate biasing conditions. The dependence of the VTH shift on substrate bias is also important to track; however, because the initial VTH values are different for devices designed for VF operation compared with those designed for VR operation, gm,lin was used to monitor hot-carrier degradation in this letter.

Fig. 2. Voltage for a ten-year lifetime versus substrate bias for various gate lengths. (a) nMOS. (b) pMOS. The substrate bias effect factor γ ≡ ∆VTH /∆VSUB is shown in parentheses.

where ESAT is the critical electric field for velocity saturation. Equation (1) can be rewritten as 1 1 1 + = . VDSAT ESAT L VGS − VTH

(2)

III. R ESULTS AND D ISCUSSION Due to the effect of VSUB on the electric field in the channel–drain region, it is expected that hot-carrier reliability should improve with forward substrate bias (VF ) and degrade with reverse substrate bias (VR ). Our experimental findings confirm this to be the case for MOSFETs with LG > 100 nm (Fig. 1). However, the dependence of hot-carrier reliability on VSUB is small for MOSFETs with LG = 40 nm. These results are consistent with the previous report by Togo et al. [5] and can be explained with the aid of the following quasi-2-D model of the electric field in the drain region, which is similar to those used for modeling the substrate current and other hotelectron phenomena in MOSFETs [10], [11]. The saturation drain voltage VDSAT is expressed as VDSAT =

ESAT L(VGS − VTH ) VGS − VTH + ESAT L

(1)

The electric field in the drain region is proportional to the voltage drop across the pinchoff region, i.e., VDS − VDSAT . For a long-channel device, the term (1/ESAT L) in (2) is relatively small; therefore, VDSAT ≈ VGS − VTH . Under forwardbias VSUB , VTH is decreased and hence, VDSAT is increased. As a result, VDS − VDSAT , which in turn is the electric field in the drain region, is decreased under forward substrate bias. Therefore, hot-carrier lifetime improves. For a very short-channel device, the term (1/ESAT L) is significant and hence, VDSAT is less sensitive to changes in VTH [see (2)]. Furthermore, VTH is also less sensitive to VSUB at a small LG so that VSUB has little impact on VDSAT . Hence, it has little impact on hotcarrier reliability in very short-channel MOSFETs. The effect of substrate bias on the ten-year lifetime voltage is plotted in Fig. 2 for devices with various gate lengths. It is clearly shown that the dependence on substrate bias decreases with decreasing gate length. However, even a small improvement in hot-carrier

HOKAZONO et al.: MOSFET HOT-CARRIER RELIABILITY IMPROVEMENT BY FORWARD-BODY BIAS

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Fig. 4. (a) Body effect factor γ and (b) threshold voltage VTH versus gate length for various device designs. A strong correlation between γ and VTH rolloff is shown. Each is improved as the depth of the source–drain extension junctions is scaled. Since nanometer-scale MOSFETs will likely have sophisticated structure for good immunity to short-channel effects, γ can still be significant.

IV. C ONCLUSION

Fig. 3. Hot-carrier reliability versus substrate bias for fixed gate length and various channel implant doses, i.e., various values of γ. (a) nMOS. (b) pMOS. Larger γ results in a stronger effect of VSUB on hot-carrier reliability.

lifetime by applying VF can be valuable, considering the low ten-year lifetime voltage for short gate lengths. In addition, the improvement can actually be more substantial for scaled CMOS technologies, as discussed in the following text. Hot-carrier reliability varies with VSUB through the change in VTH . Therefore, it should be strongly correlated with the substrate bias effect factor γ ≡ ∆VTH /∆VSUB . In Fig. 3, the ten-year lifetime voltage is plotted for devices with the same LG but different channel implant doses, i.e., for various γ. The devices with LG = 110 nm in Fig. 2(a) and (b) correspond to the devices with γ = 0.19 in Fig. 3(a) and γ = 0.18 in Fig. 3(b), respectively. The data show stronger VSUB dependence of hotcarrier reliability and hence, a more significant improvement with forward-bias VSUB for larger γ. Thus, not only gate length but also γ has an influence on the hot-carrier reliability dependence on VSUB . The pMOS devices in Figs. 1 and 2 have larger γ than the nMOS devices; thus, a larger dependence of hot-carrier reliability on VSUB is observed in the very short channel pMOS devices as compared with the nMOS devices. Strong correlation between γ and the VTH rolloff behavior can be shown in Fig. 4. The improvement in γ is due to the scaling of source–drain extension junction depth. Because nanometerscale MOSFETs will likely have heavily doped channels and sophisticated structure for good immunity from short-channel effects, γ can still be significant and therefore, forward substrate biasing can be expected to provide valuable improvement in hot-carrier lifetime for sub-hp65 nm CMOS technologies.

Forward substrate bias improves hot-carrier reliability by reducing VTH and therefore VDS − VDSAT which is the electric field in the drain region. Reverse substrate bias, on the other hand, degrades hot-carrier reliability. The sensitivity of hotcarrier reliability to substrate bias decreases with decreasing gate length within a given process technology and increases with increasing γ. Nevertheless, improvement in hot-carrier lifetime can be significant for minimum-channel-length devices (Fig. 2). The criterion for “short gate length” is related to 1/ESAT (2); therefore, it will be desirable to increase ESAT . With the VDD scaling, hot-carrier lifetime sensitivity to VSUB will become more important for shorter gate lengths. Therefore, forward substrate biasing is a promising approach to extend the bulk-Si CMOS scaling limit because it provides for smaller depletion width [2], suppression of the band-to-band tunneling, and improvement in hot-carrier reliability. R EFERENCES [1] H. Koura, M. Takamiya, and T. Hiramoto, “Optimum conditions of body effect factor and substrate bias in various threshold voltage MOSFETs,” Jpn. J. Appl. Phys., vol. 39, no. 4B, pp. 2312–2317, Apr. 2000. [2] S.-F. Huang, C. Wann, Y.-S. Huang, C.-Y. Lin, T. Schafbauer, S.-M. Cheng, Y.-C. Cheng, K.-C. Juan, D. Vietzke, M. Eller, C. Lin, Q. Ye, N. Rovedo, S. Biesemans, P. Nguyen, R. Dennard, and B. Chen, “Scalability and biasing strategy for CMOS with active well bias,” in VLSI Symp. Tech. Dig., 2001, pp. 107–108. [3] S. Borkar, “Circuit techniques for subthreshold leakage avoidance, control, and tolerance,” in IEDM Tech. Dig., 2004, pp. 421–424. [4] D. Esseni, L. Selmi, A. Ghetti, and E. Sangiorgi, “Injection efficiency of CHISEL gate currents in short MOS devices: Physical mechanism, device implications, and sensitivity to technological parameters,” IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2194–2200, Nov. 2000. [5] M. Togo, T. Fukai, Y. Nakahara, S. Koyama, M. Makabe, E. Hasegawa, M. Nagase, T. Matsuda, K. Sakamoto, S. Fujiwara, Y. Goto, T. Yamamoto, T. Mogami, M. Ikeda, Y. Yamagata, and K. Imai, “Power-aware 65 nm node CMOS technology using variable VDD and back-bias control with

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