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MOSIS CMOS Scalable Rules An Example of Scalable Design ...
An Example of Scalable Design Rules for Integrated Circuit Layout The following pages contain an example of a typical set of design rules that is used by the MOSIS integrated circuit fabrication service. The symbol names, colors, and patterns for the different layers refer to the MAGIC layout software package.
MOSIS CMOS Scalable Rules LAYER
SYMBOL MIN. DIM. COLOR PATTERN
NDIFFUSION
ndiff
3
green
PDIFFUSION
pdiff
3
brown
POLYSILICON
poly
2
red
METAL1
m1
3
blue
METAL2
m2
3
purple
NWELL
nwell
10
lt. green
PWELL
pwell
10
lt. brown
CONTACT
m2c, pc, ndc, pdc, nnc, ppc
2 M1
1
M2
COMMENTS 1. ALL CONTACTS ARE WITH RESPECT TO THE METAL1 LAYER (e.g. pc= m1 to poly). 2. DIMENSIONS ARE IN UNITS OF LAMBDA FOR GENERAL LAYOUTS OR MICRONS FOR 2.0 MICRON TECHNOLOGY (LAMBDA = 1.0). 3. A SUBSTRATE OR WELL CONTACT MAY BE SHOWN BY A FREE STANDING CONTACT OR BY A DOUBLE CONTACT AT THE SOURCE OF A TRANSISTOR. 4. DIMENSIONS GIVEN ARE MINIMUM VALUES, EXCEPT FOR CONTACT SIZES WHICH MUST BE EXACTLY 2 X 2 AS SHOWN.
RULES A. ACTIVE (TRANSISTOR) POLY GATE OVERLAP
POLY WIDTH ACTIVE TO CONTACT 2
NDIFF WIDTH 2
2
3
2
CONTACT
1 FIELD POLY TO DIFFUSION
3
3 DIFFUSION BEYOND POLY GATE
SUMMARY OF RULES: 1. MINIMUM DIFFUSION WIDTH = 3 2. MINIMUM POLY WIDTH = 2 3. MINIMUM SPACING OF FIELD POLY TO DIFFUSION = 1 4. POLY GATE OVERLAP OF DIFFUSION = 2 5. EXTENSION OF DIFFUSION BEYOND POLY GATE = 3 6. MINIMUM POLY GATE TO CONTACT = 2 7. CONTACT IS EXACTLY 2 X 2 2
B. GENERAL WIDTHS AND SPACINGS 2
2
3
3
3
3
3
3
2
3
3
4
POLY
DIFFUSION
METAL1
METAL2
10
10
10
4
9
PWELL
NWELL
DIFFUSION TO WELL EDGE
DIFFUSION CONTACT
CONTACT AND OVERLAP 4
5
5
5
1
5 DIFFUSION TO WELL
3
CONTACT OVERLAP WELL/SUBSTRATE CONTACT 3 WELL CONTACT DIFFUSION TO WELL EDGE ACTIVE TO SUBS/WELL CONTACT
5. MINIMUM WELL WIDTH = 10 MINIMUM WELL SPACING = 4 MIN PWELL TO NWELL SPACING = 9
12. MIN OVERLAP PLUS CONTACT = 4 3
C. OTHER CONTACTS 2
2
2
2
1
POLY
DIFFUSION
4
DIFFUSION
5
4 2 many contacts
6
DIFFUSION
2 2
3
2
2 VIA (M2 TO M1)
ALTERNATE VIA (M2 TO M1)
VIA (M2 TO M1)
SUMMARY OF RULES: 1. MULTIPLE POLY/DIFFUSION CONTACT SPACING = 2 2. POLY/DIFF/METAL OVERLAP OF CONTACT = 1 3. CONTACT TO TRANSISTOR CHANNEL = 2 4. DIFF CONTACT TO POLY CONTACT = 4 5. FIELD POLY TO DIFF W/ MULTIPLE CONTACTS = 2 6. POLY CONTACT TO POLY CONTACT = 5 7. POLY CONTACT TO FIELD POLY = 4 8. METAL2 ONLY CONNECTS TO METAL 1 9. A VIA MUST BE ON A FLAT SURFACE BY SPACING CONTACTS 3 UNITS WHEN NO DIFF/POLY IS UNDERNEATH OR EXTENDING DIFF/POLY 2 UNITS BEYOND THE VIA ON ALL SIDES. UNRELATED DIFF/POLY TO VIA = 2. 10. CONNECT METAL2 TO DIFF/POLY BY FORMING A METAL2 TO METAL1 VIA AND THEN A METAL1 TO DIFF OR POLY CONTACT. 4
