MRAM Cell Technology for Over 500-MHz SoC - IEEE Xplore

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007

MRAM Cell Technology for Over 500-MHz SoC Noboru Sakimura, Member, IEEE, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, and Shuichi Tahara, Fellow, IEEE

Abstract—This paper describes newly developed magnetic random access memory (MRAM) cell technology suitable for high-speed memory macros embedded in next-generation system LSIs: a two-transistor one-magnetic tunneling junction (2T1MTJ) cell structure, a write-line-inserted MTJ, and a 5T2MTJ cell structure. The 2T1MTJ cell structure makes it possible to significantly improve the write margin and accelerate the operating speed to 200 MHz. Its high compatibility with SRAM specifications and its wide write margin were confirmed by measuring 2T1MTJ MRAM test chips. Although the cell structure requires a small-writing-current MTJ, the current can be reduced to 1 mA using the newly developed write-line-inserted MTJ. Further development to reduce the current down to 0.5 mA is required to obtain a cell area of 1.9 m2 , which is smaller than the SRAM cell area, in the 0.13- m CMOS process. The 5T2MTJ cell structure also enables random-access operation over 500 MHz because the sensing signal is amplified in each cell. Random access time of less than 2 ns can be achieved with SPICE simulation when the magnetic resistance is 5 k and the magnetoresistive (MR) ratio is more than 70%.

Fig. 1. Random-access-operation frequency versus relative cell size in various types of memory cells, where F is feature size.

Index Terms—High speed, low switching current, MRAM, nonvolatile memories, systems-on-chips.

I. INTRODUCTION

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WO TYPES of memory macros have been embedded in recent system LSIs. One is high-speed RAMs used for temporary data processing with the SRAMs that are in particularly wide use. The other is nonvolatile memories used for data retention in the power-off state with flash memories mainly being used. MRAMs are the only nonvolatile memory devices with unlimited write endurance [1], [2], which makes it possible for them to be substituted for both SRAMs and flash memory macros [3], [4]. Embedding MRAM macros in system LSIs is expected to unify RAMs and ROMs. It will also enable systems to be ready for use immediately after the power is switched on and enable zero stand-by current in the memory macros. A clock frequency of over 200 MHz is required in next-generation system LSIs, and this will rise to over 500 MHz in high-performance applications within a few years. To advance memory technology, the operating speed of MRAMs needs to be enhanced to that of SRAMs as shown in Fig. 1. However, it is difficult for conventional MRAMs to operate at clock frequencies over 100 MHz even in burst-mode operation, because

Manuscript received August 25, 2006; revised December 3, 2006. A portion of this work was supported by NEDO-F21. N. Sakimura, T. Sugibayashi, T. Honda, H. Honjo, S. Saito, T. Suzuki, and N. Ishiwata are with the System Devices Research Laboratories, NEC Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan (e-mail: [email protected]). S. Tahara is with NEC Corporation, Tsukuba, Ibaraki 305-8501, Japan. Digital Object Identifier 10.1109/JSSC.2007.891665

of the narrow operational margin with both write and read operations [5]–[8]. MTJ polarization is switched by a synthesized magnetic field and ) through the induced by two writing currents ( word line (WL) and bit line (BL) [1], [5] in the conventional dual-axis MRAM writing scheme. The writing currents must be precisely controlled so that they are within the lower and upper limits to avoid multiple writing in half-selected cells. This makes the write-current source (WCS) complicated in MRAMs. For example, analog-current sources with a bias circuit are typically used for WCSs to constantly supply writing current independent of their output impedance and power-supply voltage . The circuit is further complicated due to compensation for the dependence of switching characteristics on temperature and the writing-current variations caused by cell-parameter variations [9], [10]. As a result, it is difvariations and ficult to enable write operation over 100 MHz because of the writing-current width of around 10 ns, as seen in Fig. 4(a). The sensing signal is small because of a low magnetoresistive (MR) ratio of 30%–40% in conventional MRAM cells including AlOx-barrier MTJs, which makes read circuits complicated for the following reasons. When the voltage of a 300–500 mV is clamped to a selected BL, a current conveyer detects sensing and converts it to sensing voltage in a concurrent ventional current sensing scheme widely used in MRAMs [2], , which is required to [5]–[7]. Reference sensing voltage determine whether a stored data bit is 0 or 1, is generated from averaged reference sensing current by using two reference cells in which complementary data are stored. The sense amplifier with the to determine a stored data (SA) compares the and bit’s value. However, it takes over 10 ns for the

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SAKIMURA et al.: MRAM CELL TECHNOLOGY FOR OVER 500-MHz SoC

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Fig. 2. (a) 2T1MTJ cell structure, (b) cell layout, and (c) write margin.

to reach a reliable value because of the small sensing signal and the BL’s large parasitic capacitance. In addition, MTJ resistance cannot be reduced to under 10 k to avoid the decrease in the sensing signal caused by series parasitic resistance. Consequently, it is difficult for conventional MRAMs to operate with read-access time of less than 10 ns. To address these problems, we have developed a new MRAM cell technology suitable for high-speed memory macros embedded in system LSIs. The technology involves the use of a two-transistor one-magnetic tunneling junction (2T1MTJ) cell structure, a write-line-inserted MTJ and a 5T2MTJ cell structure. The 2T1MTJ cell structure eliminates the upper limit of the writing current, which enables very high-speed write operation. Although the random-access operating speed in 2T1MTJ MRAM macros is limited by the reading speed, it can be accelerated to 200-MHz clock frequency by introducing an MgO-barrier process. The write-line-inserted MTJ has great potential for reducing the writing current to 1 mA so that 2T1MTJ cell area is less than or equal to an SRAM cell area. Therefore, the 2T1MTJ MRAM macros can be embedded in mainstream system LSIs as high-speed nonvolatile RAMs. High-speed SRAM macros operating at frequencies of over 500 MHz are used in system LSIs for high-performance applications. The 5T2MTJ cell structure, in which the sensing current signal is amplified and transformed into the voltage signal, makes it possible to design MRAM macros operating at such high frequencies. The remainder of this paper is organized as follows. Section II describes the 2T1MTJ cell structure. Section III presents a write-line-inserted MTJ. Section IV describes the 5T2MTJ cell structure. Finally, a summary of this work is provided in Section V. II. 2T1MTJ-CELL STRUCTURE A. Cell Structure and Contribution to High-Speed Writing Fig. 2 illustrates the proposed 2T1MTJ cell structure and its cell layout. The cell consists of two pass transistors (M1 and

M2) and one MTJ overlying a write line connected to both the transistors. The cell structure can greatly improve cell selecbut also tivity in MRAMs because not only sensing current writing current are conducted into a selected cell by the activated M1 and M2, as shown in Fig. 2(a). The cell is therefore superior to other MRAM cells from the viewpoint of macro design because it can be accessed in the same way as SRAM cells. MTJ polarization in 2T1MTJ cells is switched by a magnetic induced by one that flows through the write line field in a selected cell, as shown in Fig. 2(a). In the cell structure, a base electrode of the MTJ is used as the write line and the MTJ is directly placed on the thin write line to effectively enhance the . The direction of the easy axis for MTJ polarization is inclined by 45 with respect to the direction of the write line is optimized according to astroid switching curve because shape [see Fig. 2(c)]. Furthermore, it is necessary to use a metal layer, which is far from the MTJ layer, as the bit lines (BL and BLb) so that the current in these lines will not affect MTJ polarization. For example, the first metal layer is used as the BLs, and the MTJ and the write line are formed between the third and fourth metal layer. Therefore, the 2T1MTJ cell can provide a new single-axis writing scheme that applies a writing field to an MTJ only in a selected cell. The scheme eliminates both the and the need for accurate current control. upper limit of the This simplifies the write circuit (WC), and it can thus only be composed of logic gates, like an SRAM’s decoder. The simplified WC can easily change the direction of by supplying complementary voltage to the BL and BLb according to input data. Furthermore, the circuit can supply a writing current waveform of less than 1 ns, as seen in Fig. 4(b). The writing scheme will help to realize MRAM macros operating with write cycle time of around 1 ns, although the number of transistors and metal lines in 2T1MTJ cells is more than that in conventional MRAM cells. 2T1MTJ cells are classified into two types in terms of paths: common BL cells and separated BL cells. In the former, the SA connected to the BL supplies the , which flows through

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Fig. 3. Cell current paths in (a) common BL cell and (b) separated BL cell.

the M1 and the MTJ to the GND line, shown in Fig. 3(a). At that time, both the BL and BLb are not connected to the WC. In the latter, the SA connected to the read-bit line (RBL) supflowing through the MTJ, the M1 and the M2 to plies the the grounded write-bit lines (WBL and WBLb) with the WC, shown in Fig. 3(b). In terms of reading speed, the separated BL type is superior to the common BL type because the parasitic capacitance of the RBL can easily be reduced by hierarchically dividing the line. B. Test Chips Measurement Results Test chips using 2T1MTJ cells have already been fabricated in 0.18- m CMOS and 0.24- m MRAM processes. The test chips include six 16-kbit memory macros and various types of 2T1MTJ cells are fabricated in each macro, as shown in Fig. 5. Each macro was designed by partially modifying an SRAM macro to evaluate the compatibility of embedded SRAM interfaces. Thus, all circuits in an SRAM macro are reused, except for memory cells and SAs. A controller selects and connects the pins of one macro to external pins. Each macro has 16 data I/O pins and the area of each macro is 0.42 mm . The writing current was a large 6 mA because the MRAM technology was optimized for conventional MRAM cells. Thus, the cell area of 14.3 m , which is four times that of the SRAM cell, was enlarged to enable the writing and reading characteristics to be measured and understood. Measuring the test chips confirmed the outstanding compatibility with SRAM specifications and the wide-write margin


Fig. 4. Writing current waveform in (a) the dual-axis writing scheme and (b) the single-axis writing scheme using the 2T1MTJ cell.

characteristics in 2T1MTJ MRAM macros. It was also confirmed that there were no disturbed cells in the memory array. Fig. 6 shows a measured access shmoo plot of a data I/O pin that included defect-free 1-kbit memory cells. This plot indicates that 2T1MTJ MRAM macros can operate in a wide range. The lower limit of the passing region was restricted by the write margin and the upper limit was restricted by the read noise in margin. The read operation was also sensitive to the lower anomalous passing region: failure was not caused by cell characteristics but by the SA’s characteristics, which had not been optimized. The cycle time was limited to around 20 ns by the reading speed because the MR ratio had only been about 30% in the AlOx-barrier MTJ. The limited cycle time corresponded with the read-access time that had been obtained using SPICE simulation. C. Reading Speed Study The cycle time of 2T1MTJ MRAM macros is limited by the reading speed since stored data is read out in the same way as in conventional MRAMs. It is necessary to accelerate the reading speed to 200-MHz clock frequency to embed the macros into mainstream system LSIs. Fortunately, an MgO-barrier MTJ that can achieve a high MR ratio of over 100% has recently been reported [11]. The barrier makes it possible to greatly improve the sensing signal and reading speed even with conventional sensing schemes. The widely improved sensing signal reduces MTJ resistance to less than 10 k in order to shorten the settling time of . Fig. 13(a) plots the read-access time for 2T1MTJ MRAM macros estimated with SPICE simulation using 0.13- m


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Fig. 5. (a) Microphotograph of 2T1MTJ MRAM test chip and (b) structure of MRAM macro.

Fig. 6. Access shmoo plot measured in 2T1MTJ MRAM test chip. Fig. 7. Estimated cell area of (a) 2T1MTJ cell and (b) 5T2MTJ cell.

CMOS-model parameters and taking the high MR ratio of 5% MgO-barrier MTJs into consideration. A variation of 5 in MTJ resistance was assumed in the simulation based on MTJ variation of a well-known experimental results, and the 3 value and the cell area for a 0.5-mA writing current were used. The resulting read-access time of less than 5 ns could be obtained by assuming an MTJ resistance of 5 k and an MR ratio of more than 50% with up to 256 rows in a memory array. The introduction of MgO-barrier technology in the cell structure makes it possible to design MRAM macros operating at 200-MHz clock frequency, which is sufficiently high to enable MRAM macros to be substituted for the SRAM macros used in mainstream system LSIs. III. WRITE-LINE-INSERTED MTJ The 2T1MTJ cell area needs to be as small as possible to advance memory technology in next-generation system LSIs. The writing current supplied to a 2T1MTJ cell is restricted by the series on-state resistance of pass transistors in each cell. As shown in Fig. 7(a), it is necessary to reduce the current to under 1 mA so that the cell area is less than or equal to the SRAM cell

area. For example, the estimated cell area is 1.9 m , which is less than the SRAM cell area, at a writing current of 0.5 mA in the 0.13- m CMOS and 0.24- m MRAM processes. However, it is very difficult to achieve such a low writing current with conventional MRAM technology where the current is more than 5 mA [2], [12]. One approach to reduce the current is to use a cladding line that can concentrate the magnetic field induced by the current [13], [14]. This approach, however, is not suitable for embedding MRAM macros in system LSIs because of the complicated cladding-line process that is involved. Another approach is to reduce the free layer’s coercivity, which is proportional to the writing current. It can be easily reduced by lowering the aspect ratio, which is defined as the ratio of the major to the minor axis of the elliptical free layer, even though this approach deteriorates endurance against thermal fluctuations. However, it is not necessary to maintain the high degree of endurance required in the conventional writing scheme since the proposed one does not contain any half-selected cells. This is furthering the development of a new MTJ structure whose switching current becomes much smaller than that of conventional MTJs.

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Fig. 9. Switching current as a function of aspect ratio of write-line-inserted MTJ.

Fig. 8. Cross section of MTJ into which the write line is inserted between two statically magnetic coupled free layers.

Fig. 8 shows a cross section of newly developed write-line-inserted MTJ, which has the potential to reduce the switching current to less than 1 mA. It includes two free layers with a low aspect ratio and a write line directly inserted between the layers. A pinned layer is placed on a tunneling barrier in the MTJs to facilitate ease of fabrication. These free layers are magnetostatically coupled to each other, which provides good switching properties even with a low aspect ratio of about one. Therefore, the switching current becomes much smaller than that of conventional MTJs by means of a magnetic field directly applied to the free layers with much smaller magnetic anisotropy. The MTJ is also superior to conventional MTJs in terms of the endurance against thermal fluctuations. This endurance is enhanced by the magnetostatic coupling between the free layers and doubling of the total thickness of the free layers despite such a low aspect ratio. We expect that the structure which enables efficient writing will have some scalability, and this is now being investigated. The switching current as a function of the aspect ratio of write-line-inserted MTJs is plotted in Fig. 9. The simulation result indicates that the switching current decreases as the aspect ratio decreases. The switching current for the proposed MTJ fabricated in a 1-bit MTJ test structure was measured. The plot reveals the smallest current data at each aspect ratio. The measured switching current was as low as 1 mA when its aspect ratio was about one. This indicates good agreement with the simulation result. IV. 5T2MTJ CELL STRUCTURE A. Cell Design and Contributions Although the simulation results in Fig. 13(a) predict a random access time of less than 5 ns in a 2T1MTJ MRAM macro, the reading speed is not sufficiently fast for high-performance system LSIs operating at clock frequencies of over 500 MHz. It

Fig. 10. 5T2MTJ cell structure and in cell-signal amplification sensing scheme.

is difficult for conventional current-sensing schemes to achieve settling time of more than such frequencies because of the 2 ns. It is necessary to develop a new MRAM cell technology and a new sensing scheme to overcome this limitation. Fig. 10 is a circuit diagram of a 5T2MTJ cell structure that enables very high-speed GHz level operation. The cell consists of two MTJs (J1 and J2) connected in series between the plate line (SPL) and GND line, two pass transistors (M1 and M2) for writing, a common-source circuit comprising M3 and M4, and a pass transistor (M5) for reading. A bit of data and its complement are stored in the two MTJs [15]–[17] to expand the sensing signal. As can be seen from Fig. 11, the write line is


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Fig. 11. 5T2MTJ cell layout.

Fig. 13. Simulated read-access time in 0.13-m CMOS process at 1.2 V. In each simulation, R = 5 k , C = 20 fF, and 0.5-mA cell area were variation of 5 = 5% was used. assumed. Worst condition was when R

at the node to which these MTJs are connected is either more according to the stored data. Here, the or less than settling time can be improved because the parasitic capacitance of the node to which the is output is greatly reduced (the capacitance is approximately equal to tunnel barrier capaci). When the J1 resistance is in a low-resistance tance and the J2 resistance is in a high-resistance state state , the can be expressed as (1)

Fig. 12. Simulated read waveform for 5T2MTJ MRAM when memory array = 5 k , MR ratio = 150%. MTJ consists of 32 rows and 8 columns, R resistance variations are not included in simulation.

laid out under the two MTJs so that a writing magnetic field can be supplied to each MTJ in opposite directions. The WBL and RBL have been separated to reduce their parasitic capacitance. The sensing signal, , in the cell structure is amplified by the common-source circuit and transformed into the RBL in each cell. The in cell-signal amplification in voltage the 5T2MTJ cell enables extremely high-speed read operation. Details on the write and read operations are as follows. A bit of input data is written to the cell in the same way as in the single-axis writing scheme mentioned in Section II. The in write mode, and both the SPL and the WWL is driven to RWL are grounded in a selected cell. The activated M1 and M2 to the write line within the cell. Although the then drive the leaks through the J1 and J2 in the 5T2MTJ cell, the leakage is very small and does not complicate design of the circuit. The WWL is grounded in read mode, and the SPL and the . The SPL current then flows RWL are driven to generated through the J1 and J2, as seen in Fig. 10. The

The common-source transistor, M4, is then only weakly activated and the diode-connected transistor, M3, charges the to . The assist transistor, M6, activated by the rise in the RBL driver charges it more until . of In this case, the read data is “0” . When the J1 resisand the J2 resistance is , the can be tance is expressed as (2) Then, the M4 is strongly activated and rapidly discharges the to 0 V. In this case, the read data is “1” . Fig. 12 shows the reading waveform in a majority cell simulated using the 0.13- m CMOS process at 1.2 V when the memory array consists of 32 rows and 8 columns. Assuming that a 150% MR ratio is achieved with 5-k MTJ resistance, a read-access time of 0.85 ns can be obtained and 1-GHz operation can be achieved. The simulated read-access time as a function of MR ratio is plotted in Fig. 13(b). The worst condition in the simulation was when both the MTJ resistance variation variation of the 5 of the 5 value and the cell-transistor value were used. The simulation also assumed 20 fF and MTJ resistance of 5 k . These results indicate that the proposed cell and sensing scheme can make random read access

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Fig. 14. Design example for dual-port MRAM macro using 5T2MTJ cell.

over 500 MHz possible without clock-cycle latency if the MR ratio is more than 70% for a memory array consisting of 64 rows and 16 columns. A 5T2MTJ cell area of 5.8 m is estimated when 0.5 mA. This is almost equal to that of a dual-port SRAM cell using the same CMOS technology [see Fig. 7(b)]. An inverter can be substituted for the common-source circuit in the cell, and using it simplifies the cell design and greatly increases the gain needed to amplify . Almost the same read-access time as that in Fig. 13(b) can be obtained even in this inverter-using cell. However, its use necessitates an N-well area in the cell layout and the area overhead consequently increases by about 20%. B. Design Example of 5T2MTJ MRAM Macro Using a 5T2MTJ cell structure makes it possible to design dual-port MRAM macros that can be operated at clock frequencies over 500 MHz because the cell has one write port and one read port. Both writing and reading in this macro can be operated in the same cycle as shown in Fig. 14 unless the write-port address corresponds to the read-port address. For example, consider the case where input data is being written to memory cell A (MC-A), and data stored in MC-B is being read out in the same cycle. When the corresponding addresses are input into their ports, write operation is given priority and the macro outputs pseudo-output data that are the same as the input data. Each memory array is hierarchically divided by SPL drivers and RBL drivers to maintain extremely high-speed operation. Furthermore, data stored in all memory cells selected by an input row-address are read out in parallel to increase the bit width of read data. WBLs are shared between memory arrays to conserve both the decoder and write-circuit areas. The authors attempted to design a 16-kbit dual-port MRAM macro in an experiment based on memory organization shown in Fig. 14, using a 0.13- m CMOS process with five metal layers. A 0.5-mA

writing current, 5-k MTJ resistance, and a 100% MR ratio were assumed in the design. Each memory array divided by SPL and RBL drivers consisted of 32 rows and 8 columns, and the macro had 32-bit internal input pins and 128-bit internal output pins. The estimated macro area was 0.5 mm with a 30% area overhead for the drivers. V. CONCLUSION A new MRAM cell technology suitable for high-speed nonvolatile memory macros embedded in next-generation system LSIs has been developed. The 2T1MTJ cell structure employed enables 200-MHz random-access operation in MRAM macros through a single-axis writing scheme and an MR ratio of more than 50%. The 5T2MTJ cell structure makes it possible to accelerate the operating speed to a clock frequency of 500 MHz through an in cell-signal amplification scheme and an MR ratio of more than 70%. The new write-line-inserted MTJ can reduce the writing current to 1 mA, and further development to reduce this down to 0.5 mA is required to obtain an area smaller than that for an SRAM cell. MRAM macros applying these technologies have great potential for acting as substitutes for SRAM macros used in system LSIs. ACKNOWLEDGMENT The authors would like to thank H. Matsutera for his useful advice, T. Urai for his support with the design and technical discussions, and N. Sumihiro and N. Kasai for their assistance with management and their encouragement. The authors also would like to thank the members of the Toshiba-NEC MRAM development project. REFERENCES [1] S. Tehrani, “Magnetoresistive RAM (MRAM),” presented at the 2001 IEDM Short Course Washington, DC, Dec. 2001.


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Noboru Sakimura (M’02) received the B.E. and M.E. degrees in electrical and electronic engineering from Hiroshima University, Higashi-Hiroshima, Japan, in 1996 and 1998, respectively. In 1998, he joined the Silicon System Laboratories, NEC Corporation, Kanagawa, Japan, where he was engaged in research and development of wide-bandwidth delta-sigma ADCs. Since 2000, he has been working on research and development of large-scale MRAMs at Systems Devices Research Laboratories, NEC Corporation, Kanagawa, Japan. His current interests are in design of high-speed MRAMs. Mr. Sakimura is a member of the IEEE Solid-State Circuits Society.

Tadaiko Sugibayashi received the B.S. and M.S. degrees in material science from Osaka University, Osaka, Japan, in 1984 and 1986, respectively. He joined NEC Corporation in 1986, where he worked on memory LSI design. He is now engaged in the development of MRAM. He is a principal researcher with System Device Laboratories, NEC Corporation, Kanagawa, Japan. Mr. Sugibayashi is a member of Institute of Electronics, Information and Communication Engineers of Japan.

Takeshi Honda received the B.E., M.E., and Ph.D. degrees in applied physics from University of Tokyo, Tokyo, Japan, in 1993, 1995, and 1998, respectively. He joined NEC Corporation, Tsukuba, Japan, in 1998. He is currently involved in research and development of MRAM technology at System Devices Research Laboratories, NEC Corporation, Kanagawa, Japan. Dr. Honda is a member of the Physical Society of Japan.

Hiroaki Honjo received the B.E. and M.E. degrees in science from Kyusyu University, Fukuoka, Japan, in 1990 and 1992, respectively. He joined NEC Corporation, Tokyo, Japan, in 1992, where he developed the fabrication process of HDD heads. Since 2002, he has worked on development of MRAM technology at System Devices Research Laboratories, NEC Corporation, Kanagawa, Japan, where he develops MTJ films and MRAM design cells.

Shinsaku Saito joined NEC Corporation, Tokyo, Japan, in 1968, where he was engaged in development of wire relays for telephone exchange equipment. He worked on the development of HDD heads from 1971 to 1998, and MR heads from 1998 to 2002. Since 2002, he has been engaged in research and development of MRAMs at System Devices Research Laboratories, NEC Corporation, Kanagawa, Japan.

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Tetsuhiro Suzuki received the B.S. and M.S. degrees in physics from Keio University, Tokyo, Japan, in 1986 and 1988, respectively. He joined NEC Corporation, Kanagawa, Japan, in 1988, where he designed MR and GMR heads. From 1998 to 2001, he worked on the development of the HDD recorder. Since 2001, he has been engaged in research and development of MRAMs. His research interests include the design of MRAM, micromagnetics, and spintronics. Mr. Suzuki is a member of the Magnetics Society of Japan.

Nobuyuki Ishiwata received the B.E. and M.E. degrees in electrical and electronics engineering from Tokyo Institute of Technology, Tokyo, Japan, in 1981 and 1983, respectively, and the D.E. degree in physical electronics engineering from Tokyo Institute of Technology in 1994. He was engaged in research and development of magnetic recording technology, in particular magnetic heads for VCR and HDD, at NEC Corporation from 1984 to 2001. Since 2002, he has been working on the development of MRAMs at System Devices Research Laboratories, NEC Corporation, Kanagawa, Japan. Dr. Ishiwata is a member of the Institute Of Electronics, Information and Communication Engineers of Japan, and the Magnetics Society of Japan.

Shuichi Tahara (M’88–SM’99–F’06) received the M.S. and Dr. degrees in electronics engineering from Kyushu University, Fukuoka, Japan, in 1981 and 1990, respectively. He joined the NEC Corporation in 1981, where he has been engaged in the research and development of superconducting devices, Josephson LSI, and MRAM technology. He is currently a Chief Manager in Fundamental and Environmental Research Laboratories, Tsukuba, Japan. He is an IEEE Fellow and a member of the Institute of Electrical and Electronics Engineers and the Japan Society of Applied Physics.