Multimode power modeling and maximum-likelihood estimation

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 11, NOVEMBER 2004

Transactions Briefs__________________________________________________________________ Multimode Power Modeling and Maximum-Likelihood Estimation R. Chandramouli and Vamsi K. Srikantam Abstract—It is known that circuits exhibit multiple modes of power consumption due to various factors such as the presence of many feedback (or sequential) elements, RAM, large size, etc. Previous power-estimation techniques have largely ignored this fact. For example, Monte Carlo simulationbased power estimators tend to produce estimates for the average power consumption that corresponds only to the most probable power mode of the circuit. This can be a cause for trouble later in the design step. The aim of this paper is twofold. First, an algorithm is proposed that estimates the total number of power modes of a circuit based on simulated data. This is then followed by a maximum-likelihood estimation procedure that produces the average values of the power modes along with their probabilities of occurrence. Theoretical ideas are supported by experimental results for ISCAS ’85 benchmark circuits and a large industrial circuit. The proposed method is shown to perform well by capturing the multiple power modes for both large and small circuits even when the number of simulated samples is small while the Monte Carlo estimator does not. We conclude with a note that the proposed method is also applicable to other model selection problems in VLSI. Index Terms—Digital-CMOS, power-consumption model, switching activity, system-level.

I. INTRODUCTION The increasing demand for personal computing devices and wireless communication equipment with real-time applications has resulted in the need for designing circuits with low-power consumption. The addition of power as a parameter to the design search space has consequently lead to the exploration of the tradeoff between area, delay, and power. Accurate estimation of power consumption is useful during the synthesis of low-power designs. However, power dissipation is an input dependent phenomenon and would require exhaustive simulation to get an accurate estimate. This becomes intractable for circuits with large numbers of inputs. Apart from dependence on the input pattern applied, accurate estimation of power dissipation is difficult due to its dependence on the delay model and the circuit structure. Hence, two approaches for power estimation have been investigated in the literature: 1) nonsimulative (probabilistic) and 2) simulative. Simulative or statistical methods take care of the input dependence by proper choice of the input vectors. Details about various aspects of simulative power estimation methodology can be found in [1]–[7]. Most of the methods discussed so far assume a unimodal Gaussian probability distribution for the power consumption of the circuits, i.e., the Gaussian probability distribution has only one peak (mean value). It is justified to a large extent by the central limit theorem. Unfortunately, this may not be the case in many practical scenarios. The probability distribution may be bimodal or even multimodal, called, mixture density Manuscript received October 15, 2002; revised March 30, 2004. The work of R. Chandramouli was supported in part by the National Science Foundation under Grant 0082064. This paper was presented in part at the Asia South Pacific Design Automation Conference (ASPDAC) 2000, and in part at the International Symposium on Circuits and Systems (ISCAS) 2000. R. Chandramouli is with Stevens Institute of Technology, Hoboken, NJ 07030 USA (e-mail: [email protected]). V. K. Srikantam is with Agilent Laboratories, Palo Alto, CA 94304-1317 USA. Digital Object Identifier 10.1109/TVLSI.2004.836319

Fig. 1. Normal mixture density with three components.

models as shown in Fig. 1. Fig. 1 shows an example where a circuit has three average power values 1 , 2 and 3 with certain probabilities. The reasons for this behavior could be due to any of the following: 1) structure of the circuit and/or inputs; 2) limited sampling due to cost,; 3) conditions for central limit theorem to hold may not be valid for the given data; and/or 4) the power modes can be located in the tails of the probability distribution which could be difficult to capture. For example, a circuit may be enabled or disabled by means of a signal, and based on the activity on that signal the circuit can show very different power consumptions. Hence, such power distributions need to be captured for accurate power estimation and optimization. Usually, power estimation based on the Monte Carlo methods produce estimates that correspond only to the most probable component of the mixture density. As discussed above, there can be many components in the probability distribution of the power consumption of a circuit. Therefore, an efficient power-estimation technique must account for these components. Therefore, the problem is two-fold for power estimation for VLSI circuits: 1) estimate the number of modes of operation of a circuit in terms of its multiple average power consumption values and 2) estimate these average power values and the probabilities of their occurrences. So far in the low-power VLSI literature, computation of the multiple components has been largely ignored or manual choices are made based on visually looking at the histogram of the simulated power data. But, we know that both these approaches could lead to large errors in the power estimates. The aim of this paper is to first develop and discuss an algorithm that automatically estimates the number of components in a mixture density model for the simulated power data [8]. The method is based on optimizing an information criterion called the Akaike’s information criterion (AIC) [12]. The algorithm computes the optimum number of components by minimizing the AIC based on the observed power values. Once this is done, it can then be used in a maximum-likelihood power estimation procedure [9] to obtain the average power consumptions, corresponding to the multiple modes of operation of the circuit along with their associated variances and their probabilities of occurrence. This is modeled as a statistical optimization problem and a numerical solution based on the principle of expectation-maximization [13] is proposed. We believe this is the first attempt in automating the computation of the optimal probability model for power estimation in low-power applications. The paper is organized as follows. For mathematical preliminaries, model selection using AIC and power estimation can be found in Section II. Experimental results for ISCAS’85 benchmark circuits and a

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TABLE I VALUES OF AKAIKE’S INFORMATION FOR VARIOUS BENCHMARK CIRCUITS WHEN k

large industrial circuit are given in Section III to validate our theory. Concluding remarks can be found in Section IV.

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= 1 AND k

=6

a) well studied asymptotic theory; b) estimates can be computed easily; and c) can be combined with the likelihood-based statistical inference methods.

II. MODEL SELECTION AND POWER ESTIMATION In this section, we describe the mathematical ideas and concepts behind mixture distribution model for a random variable, AIC based model selection, and maximum-likelihood estimation of the model parameters. Suppose a random variable, P , takes values in a sample space, P , and admits a probability density function (PDF). Let the PDF be of the form

( ) = 1 f1(p) + 2 f2(p) + 1 1 1 + k fk (p) (p 2 P) (1) where j > 0, j = 1; 2; . . . ; k ; j j = 1, fj (:) 0, and P fj (p)dp = 1. We then say that P has a finite mixture distribution and that f (p) in (1) is a finite mixture density function. The parameters 1 ; 2 ; . . . ; k are called the mixing weights and f1 (:); f2 (:); . . . ; fk (:) the component densities of the mixture dependent on a parameter set = f1 ; 2 ; . . . ; k g. The mixing f p

weights give the proportion of the data that can be modeled using the corresponding PDF. In this paper, the component probability densities are assumed to be Gaussian for the following reasons. From an information theoretic point of view, for a given variance, the Gaussian distribution has the maximum entropy among all finite-variance continuous random variables and also this assumption is consistent with the cited empirical studies. Then, from (1), we have f (p) = 1 f1 (pj1 ) + 2 f2 (pj2 ) + 1 1 1 + k fk (pjk ). We denote the complete collection of all the parameters in the k -component mixture model by 9 = f1 ; 2 ; . . . ; k ; 1 ; 2 ; . . . ; k g. The finite mixture density then takes the form

( j9) =

f p

k j =1

~( j )

j f p j

(2)

where, each of 1 ; 2 ; . . . ; k belongs to the same parameter space, 2 (say) and f~(:j) denotes a generic density function. The first issue

is to compute the number of components k in the mixture. Toward this end, we use the Akaike information criterion [12]. The optimal number of components is given by the value of k that minimizes this criterion. Once this value is computed we then attempt to estimate the values in 9 using the maximum-likelihood approach. That is, the estimates are the most likely given the observed data. Given n statistically independent observations from the mixture, the likelihood function is L

(9) =

n

k

i=1

j =1

~( j )

j f pi j

:

(3)

The maximum likelihood estimate (MLE) of 9, say, 93 is then defined as 93 = max9 L( ). Usually, for computational simplicity the log-likelihood, L(9) = loge L(9) is maximized to obtain the MLE. MLE is a popular estimation technique due to the following reasons :

A. Model Selection Using AIC The theory of probability model selection deals with constructing probability models from observations. Let the n independent observations be denoted by fp1 ; p2 ; . . . ; pn g. In this brief, each observation corresponds to the simulated average value of the power consumption of a circuit. Determining the number of components in the mixture density fixes the probability model for the power estimation problem. Once the probability model is chosen, then the problem of power estimation can be considered as one of parameter estimation. We determine the number of components using a distance measure called the Akaike’s information criterion. The Akaike’s information criterion is expressed as [12]

AIC(k) = 02ln [93 ] + 2M1

(4)

where M1 is the number of freely adjustable parameters in 9. There are k 01 freely adjustable parameters in the set f1 ; 2 ; . . . ; k g since i i = 1 and 2k free parameters in f1 ; 2 ; . . . ; k g due to the mean and variance of each component in the mixture. Hence, the total number of free variables are M1 = 3k 01. The optimal number of components, kopt , in the range kmin k kmax , is found by minimizing the AIC. AIC measures the Kullback–Leibler [12] mean distance between the estimated mixture and the mixture that generates the data. The method to find the optimal k is summarized in the following steps: 1) choose initial value of k 2 [kmin ; kmax ]; 2) maximize (3) with respect to 9 for the assumed value of k using expectation–maximization algorithm [9]; 3) compute AIC(k); 4) repeat steps (1)–(3) for k 6 1 values; 5) if AIC(k) AIC(k 6 1) then kopt = k , otherwise assume k 6 2 and repeat steps (2)–(5). If the initial value of k is chosen to be closer to kopt the amount of computations is reduced. B. Expectation–Maximization (EM) Algorithm for Power Estimation The EM algorithm for MLE was first proposed in [13]. It produces the MLE of the unknown parameters iteratively. Two steps: expectation and maximization (EM) are iterated until some convergence condition is met. It does not depend on gradient computations like the stochastic approximation methods. Note that the numerical maximization of L is difficult because it contains terms involving the log of a sum. If we know the component of the mixture from which an observed datapoint is generated then the problem would be simpler. Since this information is not known when the data is observed the observations are termed as incomplete. The idea is to maximize L using the incomplete data. Define the complete data to be the fully categorized data, i.e., fyi =

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TABLE II COMPARISON OF EM POWER ESTIMATES (IN W ) FOR THE MULTIMODAL MIXTURE MODEL AND MONTE CARLO APPROACH. PROBABILITY OF EACH MODE IS ALSO GIVEN FOR THE PROPOSED METHOD

(pi ; zi ); i = 1; 2; . . . ; ng where each zi = (zij ; j = 1; 2; . . . ; k) is an indicator vector of length k with 1 in the position corresponding to the mixture component to which pi belongs. Now, the likelihood for the complete data can be written as g ( y1 ; y 2 ; . . . ; y n

j9) =

n

k

i=1 j =1

z j

[fj (pi jj )]z

TABLE III COMPUTATIONAL TIME TAKEN IN SECONDS FOR POWER ESTIMATION

(5)

which, with the logarithm becomes

L0 = =

n

k

zij loge (j fj (pi jj )) i=1 j =1 n n T T z i V ( ) + z i U i ( ) i=1 i=1

(6)

where V ( ) has loge j as its j th component and Ui () has the j th component logfj (pi jj )1. We now note that each sample is associated with its component density. The maximization of this new likelihood can be decoupled into a set of simpler maximization problems. Maximization for each of the densities in the mixture model can be performed separately. The data observations from each of the densities can be used to estimate its parameters. However, we do not know the value of zij a priori making the data incomplete. To overcome this difficulty the expected value of the log-likelihood, L0 , can be maximized instead. In [13] it is shown that if a certain value of the parameter increases the expected value of the log-likelihood (6) then the log-likelihood also increases. Our intention is to compute 93 = max9 L(9) for the incomplete data. Let y denote a complete version of p and Y (p) the set of all possible such y . Clearly, the cardinality of Y (x) is equal to kn . Then, starting from some initial value, 9(0), a sequence of estimates, f9(m) g is obtained. Let the d-dimensional Gaussian mixture density be given by f (p)=

k

1 )601 (p 0 )T j j j j d j6j j)1=2 exp 0 2 (p 0 ((2 ) j =1

where j and 6j , j = 1; 2; . . . ; k contain parameters of the component densities and j , j = 1; 2; . . . ; k are the unknown probability of occurrence of each component in the mixture. 6j is a positive definite symmetric matrix. Let fpi gin=1 denote n, d-dimensional Gaussian random vectors. Assume that each Gaussian component has a covariance matrix 6j = j2 I. Then the parameters to be estimated are j = (j ; j ), and j , j = 1; 2; . . . ; k. Observing that in our notation, 9 = (j ; j ; j ; j = 1; 2; . . . ; k) we see that 1

T

denotes the transpose of a vector.

TABLE IV VALUES OF AIC WHEN k

FOR THE INDUSTRIAL CIRCUIT = 1 AND =6

k

Expectation Step: wij

= E [zij jpi ; 9(m)] kp 0 (m)k j0d exp 0 2 (m) = k j0d (m)exp 0 kp 20 ((mm))k

:

l=1

(7)

Maximization Step: j (m + 1) = j (m + 1) =

j (m + 1) =

1

n

wij n i=1 n wij pi i=1 n wij i=1 n wij pi i=1

(8)

(9)

k 0 j (m + 1)k2 n

i=1

wij

:

(10)

III. EXPERIMENTAL RESULTS The algorithms described in previous sections were implemented in MATLAB, running on a 930-MHz PC with Pentium processor, and two


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TABLE V EM BASED MAXIMUM-LIKELIHOOD POWER ESTIMATES AND THEIR PROBABILITIES FOR THE INDUSTRIAL CIRCUIT

sets of experiments were performed. In the first experiment, six ISCAS ’85 benchmarks were used. The circuits were mapped and simulated in SIS [10]. The circuits were mapped to the lib2.genlib library and power was estimated using simulation. We used a small sample size of 150. There are two reasons for this. First, it is known that for small sample sizes the central limit theorem may not hold. This is because the rate of convergence of the distribution of the samples to the Gaussian distribution is affected by the sample size and other factors. Also, in many circumstances obtaining a large number of samples could be costly. The proposed AIC minimizing model selection algorithm was used for each circuit to estimate the optimum number of components, kopt , in the mixture density. Table I shows the values of the AIC for various probability models (1 k 6) for each benchmark circuit. The search range for kopt was restricted to f1; 2; . . . ; 6g as a user specified option without loss of any generality. The value of kopt for each benchmark circuit corresponding to the minimum value of the AIC measure as computed by the algorithm is marked by an asterix in Table I. We note that larger search ranges for k can also be chosen at the cost of more computations. Our experience shows that the chosen search range suffices for most of the circuits we considered as can be seen from Table I. In this table all the circuits except one have kopt < 6. We conducted a number of other experiments with kmax = 10 but the final result did not vary significantly. The average increase in run time for this choice of kmax was found to be about 15% which is reasonable. Table II shows the comparison between the estimated multimodal average power consumption values for the various benchmark circuits using the EM algorithm and the unimodal Monte Carlo estimator. We observe that even the power modes of the circuits with small probabilities are captured by the proposed approach. On the other hand, the Monte Carlo method produces estimates corresponding to the most probable component only—a well-known disadvantage of this approach. Table III gives the computational time to obtain the power estimates for various benchmark circuits using the proposed method and the Monte Carlo estimator. We note that the software code was not optimized for speed, and in general, MATLAB codes take longer to run compared to software written in high-level languages. Observe from this table that the computational times are comparable. When the number of exhibited power modes is small then the difference in the computational times is quite small. In the second experiment, an industrial circuit was used. The circuit is very large and was synthesized and mapped using commercial tools. The circuit was described in Verilog and synthesized using Design Compiler from Synopsys. Technology mapping was performed using the HP/Agilent 0.25-m CMOS libraries. The gate-level netlist with all delays annotated was then simulated using Verilog and the power estimates were obtained using Sente’s WattWatcher tool. The circuit was simulated extensively using 500 samples. Table IV shows the optimum value of kopt = 6 computed by the proposed algorithm. As can be seen from Table IV the power distribution is a mixture of six components. The multimodal power distribution is due to the fact that the circuit is large and consists of many feedback (or sequential) elements along with a RAM. Hence, many parts of the circuit have different power dissipation under different input conditions. For each simulation run, enough vectors were given for the circuit to be in a steady state before applying the vectors for which the power was measured.

Some clock gating is also used in the circuit; this further causes the power-dissipation fluctuation based on the activity of the control signal. The maximum-likelihood estimates of the average power consumption corresponding to each of the six modes as computed by the model selection algorithm and also seen in the histogram is summarized in Table V [9]. We note that a Monte Carlo simulator again captured only the most probable component and missed the remaining five components in this case. This analysis with a real large design using the state of the art CAD tools validates the practicality of the proposed algorithm. In deep submicron regimes, power consumption can be affected by many secondary factors that contribute to bimodal or multimodal power distribution. The proposed algorithm estimates these multiple components (or modes), thereby, giving a better power distribution estimate that will be very useful in power optimization procedures. IV. CONCLUSIONS An automated mixture density probability model selection procedure based on the Akaike’s information criterion is proposed for power estimation in low-power VLSI applications. Unlike most of the previous approaches, this method can be used to estimate the optimal number of power consumption modes based on the simulated power data for a circuit. Average power estimates based on simulations for a number of ISCAS’85 benchmark circuits and a large industrial circuit validate our claim. From these experiments we conclude that the proposed algorithm is efficient and can handle the randomness in simulated power values in both small and large circuits. The method can also be used as an effective preprocessing step to get accurate power estimates based on simulation. A maximum-likelihood power estimation procedure is proposed and discussed for simulated power data. An efficient iterative computational procedure based on the EM algorithm is given for the estimation algorithm. Average power estimates and the probabilities of their occurrences produced by the EM algorithm using simulated data for various ISCAS’85 benchmark circuits and a large industrial circuit are accurate within an acceptable level of confidence. Comparison with the Monte Carlo estimator shows that the proposed algorithms may be preferable due to its generalization capacity. ACKNOWLEDGMENT The authors thank the reviewers for their valuable comments that helped in improving the paper. REFERENCES [1] M. Xakellis and F. Najm, “Statistical estimation of switching activity in digital circuits,” in IEEE Design Automation Conf., 1994, pp. 728–733. [2] C. S. Ding, C. T. Hsieh, Q. Wu, and M. Pedram, “Stratified random sampling for power estimation,” in IEEE Int. Conf. Computer-Aided Design, San Jose, CA, 1996, pp. 577–582. [3] A. K. Murugavel, N. Ranganathan, R. Chandramouli, and S. Chavali, “Least square estimation of average power in digital CMOS circuits,” IEEE Trans. VLSI Syst., vol. 10, pp. 55–58, Feb. 2002. [4] W. W. Bachmann and S. A. Huss, “Extended time handling strategies for the improvement of prediction accuracy in event driven power estimation,” in IEEE Workshop Signal Processing Systems, Oct. 2000, pp. 539–552.

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[5] P. Israsena and S. Summerfield, “Novel pattern-based power estimation tool with accurate glitch modeling,” in Int. Symp. Circuits and Systems, vol. 4, May 2000, pp. 721–724. [6] L. Benini, G. de Micheli, E. Macii, M. Poncino, and R. Scarsi, “A multilevel engine for fast power simulation of realistic input,” IEEE Trans. Computer-Aided Design, vol. 19, pp. 459–472, Apr. 2000. [7] L. P. Yuan, C. C. Teng, and S. M. Kang, “Statistical estimation of average power dissipation using nonparametric techniques,” IEEE Trans. VLSI Syst., vol. 6, pp. 65–73, Mar. 1998. [8] R. Chandramouli and V. K. Srikantam, “Optimum probability model selection using Akaike’s information criterion for low power applications,” in Proc. Int. Symp. Circuits and Systems, May 2000, pp. 467–470. , “On mixture density and maximum likelihood power estimation [9] via expectation-maximization,” in Asian and South Pacific Design Automation Conf. , Jan. 2000, pp. 423–428. [10] E. M. Sentovich et al., “Sequential circuit design using synthesis and optimization,” in IEEE Int. Conf. Computer Design, 1992, pp. 328–333. [11] C. Ding, C. Hsieh, and M. Pedram, “Improving the efficiency of Monte Carlo power estimation,” IEEE Trans. VLSI Syst., vol. 8, pp. 584–593, Dec. 1998. [12] E. Parzen, K. Tanabe, and G. Kitagawa, Selected Papers of H. Akaike. New York: Springer Verlag, 1998. [13] A. M. Dempster, N. M. Laird, and D. B. Rubin, “Maximum likelihood from incomplete data via the EM algorithm,” J. Royal Stat. Society, vol. 39, no. 1, pp. 1–38, 1977.

Ultralow-Power Adiabatic Circuit Semi-Custom Design Antonio Blotti and Roberto Saletti

is obtained at switching speed of the circuit well below the maximum speed allowed by the technology used. Moreover, the adiabatic solutions presented are usually designed as special circuits with custom methodologies, optimized for the particular application in which they are adopted. Therefore, it becomes very hard for a designer used to the traditional CMOS design flow even to consider the adiabatic approach as feasible, without acquiring very particular skills and methodologies. In order to make adiabatic logic more friendly to the designer, it is necessary to develop methodologies and semi-automatic tools that allow the design and verification of complex adiabatic systems in short times, to enjoy the energy reduction benefits of adiabatic logic in an easy, fast, and general way. The aim of this work is to demonstrate the use of a cell-based semi-custom design flow in the design of adiabatic logic circuits. The example given is the design of arithmetic units (a family of adders and a family of multipliers) based on an adiabatic logic cell-library developed by the authors. The main result obtained is that the semi-automatic design flow quickly and easily leads to the realization of adders and multipliers characterized by a very significant energy gain, if compared to traditional CMOS and also better than other adiabatic custom solutions presented in the literature. The basic circuit topology, operation, and features of the adiabatic gates adopted are shown in Section II. Section III describes the adiabatic standard-cell library developed and the design flow adopted for the arithmetic units design. Section IV presents the adiabatic adder and multiplier architectures, whereas results are shown and discussed in Section V, by also considering the energy dissipated in the power-clock signals generation. The conclusions are finally given in Section VI. II. POSITIVE FEED-BACK ADIABATIC LOGIC

Abstract—This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom PFAL carry lookahead adders and parallel multipliers were designed in a 0.6- m CMOS technology and verified. Post-layout simulations show that semi-custom adiabatic arithmetic units can save energy a factor 17 at 10 MHz and about 7 at 100 MHz, as compared to a logically equivalent static CMOS implementation. The energy saving obtained is also better if compared to other custom adiabatic circuit realizations and maintains 6) even when the losses in power-clock generation are high values (3 considered. Index Terms—Adiabatic circuit, computer arithmetic, dynamic-logic circuit, low-power design, low power dissipation, power-consumption model.

I. INTRODUCTION The low-power requirement of present electronic systems is one of the main challenges for the research of technologies, circuits, and architectures allowing a reduction of the energy dissipated by a circuit. Adiabatic switching [1], [2] was proposed as an alternative to the traditional techniques of CMOS dynamic power consumption reduction. The low-power feature of adiabatic circuits is usually demonstrated in the literature in comparison to equivalent traditional CMOS circuits and a significant energy gain is very often obtained. However, this reduction in energy dissipation, reaching even factors of some tens [3],

Manuscript received January 2, 2003; revised January 8, 2004. The authors are with the Dipartimento di Ingegneria dell’Informazione: Elettronica, Informatica, Telecomunicazioni, University of Pisa, Pisa 56122, Italy, (e-mail: [email protected]). Digital Object Identifier 10.1109/TVLSI.2004.836320

We used the partial energy recovery circuit structure named positive feedback adiabatic logic (PFAL) [4], since it shows the lowest consumption if compared to other similar families [3], [5], and a good robustness against technological parameter variations [6], [7]. It is a dualrail circuit with partial energy recovery [3], [4]. The basic buffer/inverter PFAL gate is shown in Fig. 1(a). The core of all the PFAL gates is an adiabatic amplifier, a latch made by the two pMOS MP1-MP2 and the two nMOS MN1-MN2, that avoids a logic level degradation on the output nodes Y and /Y. The functional blocks (the simple nMOS MX and M/X in the case of the buffer/inverter gate) are in parallel with the pMOS of the adiabatic amplifier and form a transmission gate. PFAL uses a four-phase power-clock (t), as shown in Fig. 1(b): (t) rises from 0 to VDD in the evaluate phase (E) and supplies energy to the circuit, then (t) returns to 0 in the recovery phase (R) and the energy flows back from the circuit to the power-clock generator; the hold phase (H) and the idle phase (I) are needed for cascading gates. Let us suppose the input X and /X coming from another PFAL gate, that works with a power-clock signal anticipated a quarter of a period. Let us assume X high and /X low during the evaluation phase; consequently, MX is conducting and the output Y follows the power clock. Regenerative operation starts when the power-clock voltage reaches Vtn , the threshold voltage of MN2. At this time, MN2 clamps /Y to ground, MP1 turns on and reduces the charging resistance, being in parallel with MX. In the hold phase (t) = VDD , so that Y and /Y hold valid logic levels and can be used as input to other cascaded PFAL gates working in the evaluation phase in their turn. In the recovery phase, the charge stored on the load capacitance C connected to Y is recovered to (t) through MP1. As (t) falls down from VDD to 0, the resistance of MP1 increases up to the point in which MP1 turns off and the recovery stops. A residual charge on Y cannot be recovered and it is dissipated in the next cycle. This energy loss is the reason why PFAL is only a partial energy-recovery logic. As shown in Fig. 1(b), the power-clock

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