Mutually connected phase-locked loop networks

www.ietdl.org Published in IET Circuits, Devices & Systems Received on 5th March 2007 Revised on 26th August 2008 doi: 10.1049/iet-cds:20080116

ISSN 1751-858X

Mutually connected phase-locked loop networks: dynamical models and design parameters F.M. Orsatti1 R. Carareto2 J.R.C. Piqueira2 1

Departamento de Engenharia Mecaˆnica do Centro Universita´rio da FEI, Sa˜o Bernardo do Campo, Brazil Departamento de Engenharia de Telecomunicac¸o˜es e Controle, Universidade de Sa˜o Paulo, Escola Polite´cnica, Brazil E-mail: [email protected] 2

Abstract: Distribution of timing signals is an essential factor for the development of digital systems for telecommunication networks, integrated circuits and manufacturing automation. Originally, this distribution was implemented by using the master–slave architecture with a precise master clock generator sending signals to phaselocked loops (PLL) working as slave oscillators. Nowadays, wireless networks with dynamical connectivity and the increase in size and operation frequency of the integrated circuits suggest that the distribution of clock signals could be more efficient if mutually connected architectures were used. Here, mutually connected PLL networks are studied and conditions for synchronous states existence are analytically derived, depending on individual node parameters and network connectivity, considering that the nodes are nonlinear oscillators with nonlinear coupling conditions. An expression for the network synchronisation frequency is obtained. The lock-in range and the transmission error bounds are analysed providing hints to the design of this kind of clock distribution system.

1

Introduction

In engineering, there are systems that operate based on spatially separated devices with a well-determined temporal sequence. Synchronisation network is the general denomination of part of the whole system responsible for this temporal order [1– 4]. A lot of effort has been spent in the development of synchronisation networks, mainly in public telecommunication networks, digital integrated circuits and manufacturing processes automation. Since the operation procedures of telecommunication networks became digital, synchronous operation is an important factor to improve the service quality [5, 6] simplifying the access to low-frequency channels belonging to the data stream without demultiplexing it [7]. A complete description of synchronisation networks for telecommunication is given in [8]. Digital integrated circuits have several processes that are supposed to be executed in a specific sequence or in a IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 495– 508 doi: 10.1049/iet-cds:20080116

synchronous way, as in parallel processing systems [9]. Formerly, this problem was of easy solution, but the increase in the dimensions of the circuits and the high operational frequencies demanded complex synchronisation networks built together in the electronic chip [10, 11]. In both cases, telecommunications and integrated circuits, master– slave architectures were originally used to distribute a precise clock signal generated by a master node to the other points of the circuits, where controlled oscillators regenerate the phase and frequency information [8, 9]. The evolution of the telecommunication services to wireless and dynamical networks, as well as the new high frequency-integrated circuits, has shown the inadequacy of centralised clock distribution structures in these cases, motivating the study of mutually connected architectures to generate reference signals with the phase-locked loops (PLL) operating as nodes of the synchronisation networks [11 – 16]. 495

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www.ietdl.org Some interesting works about this kind of architecture were developed between 1960 and 1980 [17 – 21]. These papers were written when the service integration started to be taken into account for telecommunication networks and present several robust results for clock distribution systems, mainly considering linear analogous phase detection and linear coupling between nodes. In these works, synchronous state frequencies and their stability conditions for fully connected networks were presented depending on the free-running frequencies and node phase detector (PD) gains. Here, expressions for synchronous state frequencies and capture ranges are obtained, considering nonlinear digital PDs and, consequently, nonlinear nodes with nonlinear coupling. The motivation is that mutually connected PLL networks, nowadays, can be cheap and reliable as synchronisation networks for the described applications. Besides, they can be successfully used in sensor networks in automation [22], power distribution systems [23, 24], ad hoc multimedia networks [25], climatology systems [26] and neural computation [27]. Mutually connected networks of analogue PLLs (LPLL) with multiplier PDs were object of former studies [28 – 30]. As the performance of isolated LPLL nodes is similar to the PLL with digital phase detection (DPLL) [31] and digital circuits are more common in practical situation, the DPLLs are studied and the main goal is to analyse how the node parameters are related to the conditions for the existence of synchronous states and how the behaviour of the whole network depends on the node parameters. In Section 2, the DPLL and the network models are described and a generalisation of the work presented in [3] is proposed. In Section 3, analytical results are derived for synchronisation conditions and for the network synchronisation frequency. The existence of multiple synchronous states due to the nonlinearity of the PD is shown. In Section 4, a capture range criterion for the nodes is developed. Consequently, for the network designer, it is possible to choose the capture range of the nodes guaranteeing the existence of at least one synchronous state for the whole network. Section 5 presents, in fully connected DPLL networks, how the transmission noise affects the dynamical behaviour considering the node parameters and the connection matrix of the network. An abacus summarises the influence of the filters cut-off frequencies in the transmission errors, giving hints to estimate the network performance during its design. 496 & The Institution of Engineering and Technology 2008

Section 6 presents some numerical experiments confirming the theoretical results presented. Section 7 summarises the results that can be useful in the design of synchronisation networks composed of nonlinear oscillator nodes with nonlinear coupling [12, 32, 33].

2

DPLL models

In this section, the models for DPLLs are presented either for the single-node operation or for their dynamic behaviour when building a mutually connected network. In order to simplify the reasoning, noise-free models are presented, providing the necessary tools for the results to be obtained in Sections 3 – 5.

2.1 Single-node DPLL All PLL implementations can be modelled as a closed loop composed of a PD, a low-pass filter (LPF) and a voltage controlled oscillator (VCO) [31]. In DPLLs, the input signal, vi (t) that arrives to the PD, and the output signal vo (t), that is the VCO output, are digital with levels 0 and Vdd . PDs are implemented with an exclusive-or (XOR) port, a JK flip-flop, or a charge-pump circuit (PFD). XOR PDs demand 908 phase differences between the inputs when the signals to be compared have the same central frequencies [31]. Consequently, it is impossible to build a mutually connected network with three or more nodes by using XOR PDs [34]. The models of mutually connected networks with charge-pump (PFD) PDs are similar to those with JK flip-flop PDs. Thus, only the JK flip-flop PD option is studied here. The operation of the JK flip-flop as PD considers two input signals V1 (t) and V2 (t) controlling the output Vd (t). A positive transition in V1 (t) produces a positive transition in Vd (t), and a negative transition in V2 (t) produces a negative transition in Vd (t) [31]. Calling Q1 and Q2 the phases of V1 and V2 , respectively, and defining the phase difference DQ12 ¼ Q1  Q2 , it can be shown that the phase-detector output has duty cycle 0.5 for DQ12 ¼ 0, 1 for DQ12 ¼ 0:5 and 0 for DQ12 ¼ 0:5 [31]. Extrapolating this fact to all values of DQ12 , Fig. 1 shows how the duty cycle of the PD output depends on the input phase differences. Consequently, to provide a dynamical model for the PLL phase, a corrected phase difference G is defined as G12 ¼ DQ12  floor(DQ12 þ 0:5)

(1)

with floor(x) being a function that gives the greatest integer less or equal to x. Therefore the duty cycle, DC, of the IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 495– 508 doi: 10.1049/iet-cds:20080116

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Figure 2 DPLL model Figure 1 PD output duty cycle against input signals phase difference output of the PD is given by DC ¼ G12 þ 0:5

and, in order to obtain a frequency band independent model, a reference frequency, f0 , corresponding to a period, T0 ¼ 1=f0 , is chosen and a non-dimensional variable, t^ ¼ t=To ¼ fo t, is defined.

(2) Consequently, redefining the normalised parameters as

Equation (2) supposes that both input signals have the same central frequency, being used in the analytical study of the synchronous network.

fc ¼ Fc fo 

The LPF is a linear first-order lag and is supposed to cutoff double frequency terms, generating a signal proportional to the input phase error, and to eliminate the transmission noise accumulated in the input signal vi (t) [35, 36]. The VCO generates square waves with frequency depending on the input voltage according to :

Q ¼ fmin þ Kv vc

As the VCO operates digitally, its input must be in the interval [0,Vdd ] implying the inclusion of a saturation block in the model that avoids signals greater than Vdd and lesser than 0 in the VCO input. Fig. 2 shows a model for DPLLs, considering the assumptions above. Defining fmax the maximum VCO frequency, that is, the frequency when vc ¼ Vdd , (3) becomes Kv Vdd ¼ fmax  fmin

(4)

It is usual to characterise a PLL device by its central frequency, f , and its lock-in range, df , defined as 

fmin þ fmax 2

(5)

df ¼ fmax  fmin

(6)

f ¼

IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 495– 508 doi: 10.1049/iet-cds:20080116

 f ¼W fo

(8)

df ¼ dW fo

(9)

and considering the derivatives related to t^, the model for a single-node DPLL is given by

(3)

with fmin representing the minimum output frequency of the VCO signal, that is, the frequency when vc ¼ 0, and Kv the VCO gain.

(7)

    _ ¼ F dW V  1 þ F W € þF Q Q c c d c 2

(10)



with Vd ¼ vd =Vdd .  and dW are called filter cut-off From now on, Fc , W frequency, PLL central frequency and PLL lock-in range, respectively.

2.2 DPLL network model Considering a network composed of n nodes with each node receiving signals from all others, as the phase comparison performed by JK flip-flops needs exactly two inputs, each node needs n  1 PDs and n  1 filters [37]. The signals are weighted and summed in the output of the filters as shown in Fig. 3, containing the structure of each node belonging to a n-node DPLL mutually connected network. In Lindsey et al.’s seminal paper [3], there is only one filter in each node. Here as in each node, there are n  1 filters, one can choose a different cut-off frequency for each filter, corresponding to the noise level of the corresponding 497

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www.ietdl.org it is possible to guarantee that 0  vit  Vdd

(14)

Consequently vic ¼ vit ¼

n X

vpji Pji

(15)

j¼1

Considering the normalised model for the VCO from node i, obtained from (3), definitions (8) and (9) combined with (11) and (15) give Pn

dW

i

j¼1

(vpji =Fc ji )Pji Vdd



i

¼ W þ dW

i

n X

_i þQ

ji Vd Pji

j¼1

! 1  2

(16)

ji ji where V d ¼ vd =Vdd .

Figure 3 DPLL node in a mutually connected network transmission channel. Besides, the model developed in [3] corresponds to a particular case of the model studied here, with all filters having the same cut-off frequency. Referring to Fig. 3, representing an i-node, each PDj ji compares the signal from node j, vi , with the internal ji signal of node i, and its output, vd , is the input of the filter LPFji , the cut-off frequency of which is Fcji . Consequently, the filter output, vpji , taking the normalisation into account, is given by ji

vpji ¼ vd 

_ji vp Fc

ji

n X

vpji Pji

(12)

j¼1

In order to satisfy the input conditions of the VCO, vit is the input of a saturation block. The output of the saturation block feeds the VCO. This nonlinearity included in the model, in spite of being simple to simulate, complicates the analytical reasoning. Assuming that n X

Pji ¼ 1

and

Pji  0 8i, j

j¼1

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i

€ þ Q

_i Fci Q

¼

Fci

dW

i

n X j¼1

ji Vd Pji

!  1 þ Fci W i  2

(17)

Equation (17) represents the dynamics of node Pn i in a DPLL n-node mutually connected network if j¼1 Pji ¼ 1 and Fc ji ¼ Fci 8j.

(11)

Defining the weighting matrix, P, with each element Pji representing the gain in the output of node j in the composition of the input signal of node i, it is possible to express the weighted input signal of node i as vit ¼

Equation (16) describes the behaviour of a DPLL operating as a node in a mutually connected network. A simplifying assumption is that all the cut-off frequencies of node i are Fci . Applying these conditions, taking the derivative related to t^ and doing algebraic manipulations

(13)

3

Network synchronous state

In this section, an algebraic-equation system expressing the synchronous state of the mutually connected network is obtained, allowing an estimation of the network operation frequency. The synchronous state is considered to be reached when the frequency errors between any pair of nodes vanish, that is, when the phase errors between any pair of nodes are constant. Because the aim of this section is to obtain an estimation for the network synchronous state, the dynamics of the filters will be replaced by its averaging function. This simplification, however, is only for deriving the synchronous state existence conditions. The existence of a synchronous state for the network does not guarantee that this state is reached by the network for any initial condition. Later, the filter dynamics will be considered to verify its influence in the ability of the network to reject transmission errors. IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 495– 508 doi: 10.1049/iet-cds:20080116

www.ietdl.org To further simplify the reasoning, the signal transmission time between nodes is not considered. Furthermore, the diagonal elements of the connection matrix are zero, that is, Pii ¼ 0 8i. The sum of the elements of any line of the connection matrix is equal to 1, as indicated in (13), guaranteeing that the VCO input is between 0 and Vdd .

3.1 PD and filter dynamic behaviour

Consequently, a simplified model for the node i PD-F system, receiving a signal from node j, is vpji ¼ (Gji þ 0:5)Vdd

(18)

Replacing (18) in the VCO model and considering Pn P ¼ 1 ji j¼1 

The long-term behaviour of the system composed of the PD and the filter (PD-F) is studied considering that vi and vs are synchronous with frequency Ws and period T, with a fixed phase difference DQ ¼ Qi  Qs .

_ i ¼ W i þ dW i Q

n X

! Gji Pji

(19)

j¼1

which expresses how the phase of node i evolves in time. Considering zero initial conditions, Fig. 4, obtained by using numerical simulation, shows the filter output, normalised to Vdd , with Fc ¼ 1 and for G ¼ 0:25. This figure shows that the mean value of the filter output tends towards the duty cycle of the input signal that is 0.75, according to (2). To verify the influence of the cut-off frequency, additional simulations were conducted and the main conclusions are summarised below.

The simplified model given by (19) does not consider the filter dynamics and is used only in the calculations of the network synchronous state that is conducted in Section 3.3. In Section 5, the filter dynamics is reconsidered, in order to study the transmission noise effects.

3.2 Filter output oscillation

† The PD-F time constant increases with the decrease in the filter cut-off frequency, because it is a first-order system.

As shown, there is an oscillation in the output of the filter, even in the steady condition. Here, the amplitude of this oscillation is related to the filter cut-off frequency and to the phase difference between the PD input signals, in order to obtain, in Section 5, expressions for the phase errors due to transmission noise as a function of the filter dynamics.

† The filter output oscillates with increasing amplitude as the filter cut-off frequency increases.

and vmin are mean, maximum and The values of vp , vmax p p minimum values of the filter output, respectively. As

† The filter output, normalised to Vdd , tends towards the PD duty cycle, given by (2).

Figure 4 Filter output: G ¼ 0.25, Fc ¼ 1 and normalised time units IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 495– 508 doi: 10.1049/iet-cds:20080116

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www.ietdl.org vp =Vdd ¼ DC, and considering the filter dynamics  vp ¼

vp Vdd

¼ 0:5 þ G

where (20)

where G is the phase difference between the compared signals. and vmin To determine vmax p p , the filter dynamics is studied considering inputs 0 and Vdd . For input vd equal to 0, the solution is vp (t) ¼ vp (0) eFc t

8 < 0 aji ¼ þ1 : 1

(21)

Considering the network synchronisation frequency and Gi1 , for i ¼ 2, . . . , n, as unknown variables, the set of equations given by (25) can be written in the form of a linear algebraic equations system AxT ¼ B

(22)

Replacing all these facts in the corresponding equations, an algebraic system of equations is obtained. Solving this system and using (2) 



vmin p Vdd

¼ vmax p

¼

vmax p Vdd

(23)

1  eFc (0:5þG)T 1  eFc T

(24)

3.3 Network synchronous state To estimate the synchronous state frequency, the node phases _ ¼Q _ ¼  ¼ are considered to be constant, that is, Q 1 2 _ Qn ¼ Ws , with Ws being the synchronous frequency of the network. This assumption is satisfactory when telecommunication networks are treated, in spite of the fact that the nodes of this kind of network can be locked to different frequencies, harmonic related [29]. Consequently, for the n nodes of the network, (19) can be written as 

Ws ¼ W iþ dW i

n X

! Gji Pji , i ¼ 1, . . . , n

(25)

j¼1

It is possible to express Gji depending on Gj1 and Gi1 in the following way Gji ¼ Gj1  Gi1 þ aji , i, j ¼ 1, . . . , n 500 & The Institution of Engineering and Technology 2008

1=dW1

6 6 6 1=dW2 6 6 . 6 A ¼ 6 .. 6 6 1=dWi 6 6 .. 4 . 1=dWn

P21

   Pj1

...

1 .. . P2i .. . P2n

. . . Pj2 .. .. . . ... 1 .. .. . . . . . Pin

... .. . ... .. . ...

 x ¼ Ws

G21    Gi1    Gn1

Pn1

3

7 7 Pn2 7 7 .. 7 7 . 7 7 Pni 7 7 .. 7 . 5 1 

(29)

(30)

and

eFc (0:5G)T  eFc T 1  eFc T ¼

(28)

with 2

Choosing the time variable t1 , which is zero in the positive transition of the filter input signal, and t2 , which is zero in the negative transition of the same signal, (21) is valid for 0  t2  (1  DC)T , and (22), for 0  t1  (DC)T . Besides, vp (t1 ¼ 0) ¼ vmin vp (t1 ¼ (DC)T ) ¼ vmax p , p , max . vp (t2 ¼ 0) ¼ vp and vp (t2 ¼ (1  DC)T ) ¼ vmin p

¼ vmin p

(27)

From the expression of aji , it can be verified that: aji ¼ aij , aii ¼ 0, and ai1 ¼ 0.

for input equal to Vdd , the solution is vp (t) ¼ (vp (0)  Vdd ) eFc t þ Vdd

if jGj1  Gi1 j  0:5 if Gj1  Gi1 , 0:5 if Gj1  Gi1 . 0:5

(26)

2



W1 dW 1

3

6 7 6 7 6  7 6 W 2 Pn 7 6 dW 2 þ j¼1 aj2 Pj2 7 6 7 6 7 .. 6 7 . 6 7 B¼6 7 6 7 6 i P 7 6 W þ n a P 7 6 dW i j¼1 ji ji 7 6 7 6 7 . .. 6 7 4  5 Pn Wn þ a P j¼1 jn jn dW n

(31)

The solution of (28) gives the synchronisation frequency of the network and the phase difference between all nodes and the first one, in the synchronous state. By using (26), the phase difference between any pair of nodes can be obtained. Adding the equations, the network synchronisation frequency is calculated as Pn  i W =dW i Ws ¼ Pi¼1 n i i¼1 1=dW

(32)

As (32) shows, it is possible to conclude that the network synchronisation frequency does not depend on the filters’ cut-off frequencies and on the network connection matrix. IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 495– 508 doi: 10.1049/iet-cds:20080116

www.ietdl.org It is a function of the central frequencies and the lock-in ranges of the nodes. It must be clear that (32) does not mean that synchronisation occurs, independent of the connection matrix, it only guarantees that if synchronisation is achieved, the synchronisation frequency will be independent of the choice of connection gains. This equation cannot be used for the synchronisation frequency determination without verifying if the absolute values of the obtained Gj1 are lower than 0.5. As a matter of fact, it is not possible to guarantee that the synchronous state is reachable but, if it is, the network synchronisation frequency is given by (32). Furthermore, the system given by (28) depends on the values of parameters a. Then, for each set of values of aji the equations are solved and the solution coherence must be verified. For instance, considering a32 ¼ 1, if G21 and G31 obtained do not satisfy G31  G21 , 0:5, the solution is not considered. For an n-node network, there are (n2  n)=2 elements aji , so that aji ¼ aij and aj1 ¼ 0 for j ¼ 2, . . . , n. Therefore there are (n2  3n)=2 þ 1 as to be determined and they can assume three different values: 21, 0 and 1. Consequently, to determine all the possible synchronous states for a n-node network, K linear algebraic equations systems with n equations need to be solved, with K given by 2 K ¼ 3ð(n 3n)=2þ1Þ

As follows, topological considerations have to be assumed to guide the thinking concerning the design parameters. Thus, they are presented before the analysis.

4.1 Considerations about the 4-node network In previous works [38, 39], analytical results about the 4-node were obtained. By using the general model developed here, these results are confirmed as shown in the study that follows. If all the hypotheses about the connection matrix of Section 3 are taken into account, 2- and 3-node networks have all the connection gains determined. To observe the influence of the connections in the phase differences between the nodes in the synchronous state, a 4-node network is studied. Considering a symmetric connection matrix with null main diagonal elements, there are (n2  n)=2 elements to be calculated. As there are n equations guaranteeing that sum of the gains corresponding to each node input equal to 1, the number of gains to be determined in an n-node network is (n2  3n)=2. For the 4-node network, all the connection matrix elements are expressed in function of 2 of them. Choosing P12 and P13 as the 4-node network connection matrix, P is determined.

(33)

For n ¼ 3, K ¼ 3 but for higher values of n, the number of systems to be solved become too high. For instance, for n ¼ 10, K ¼ 336 , that is, K ’ 1, 5  1017 . It is important to notice that the stability of the synchronous states is not analyzed here, but could be studied by using Lyapunov methods as shown in [29, 30].

4

that is, the network synchronisation frequency is the mean value of the central frequency of the nodes.

For a network with an arbitrary number of nodes, it is not possible to consider all the synchronous states. Then, it is assumed that aji ¼ 0 8i, j. In this section, a condition about dW guaranteeing the existence of a synchronous state for the network, so that aji ¼ 0 8i, j, is derived. In other words, given this restriction, the obtained criterion is sufficient for the existence of the synchronous state for the network. Therefore system (28) can be simplified as

Lock-in range of the nodes

In Section 3, the expression for the network synchronisation frequency and conditions for the existence of the synchronous state were derived, depending on the lock-in range of the nodes. Here, the lock-in range of the nodes is studied, and a condition for the lock-in range that guarantees the existence of the synchronous state is presented, being a design parameter when mutually connected architecture is used to the distribution of clock signals. A simplifying but realistic condition is to consider all the nodes with the same lock-in range. Consequently, expression (32) becomes Pn Ws ¼



i i¼1 W n

IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 495– 508 doi: 10.1049/iet-cds:20080116

(34)

2

1=dW

6 1=dW 6 6 4 1=dW 1=dW

P12

P13

1 P12 þ P13  1 P12 þ P13  1 1

P13 2  3 1 6W 7 6 dW 7 7 2 3 6 6 2 7 Ws 6W 7 7 6G 7 6 7 6 21 7 6 d W 6 6 7¼6  7 4 G31 5 6 3 7 7 6W 7 6 7 G41 6 dW 7 6  7 4W4 5 dW

P12

P12 þ P13  1 P12 P12

3 7 7 7 5

1

(35)

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www.ietdl.org resulting in 

G21 ¼







(1 þ P13 )(W 2  W 1) þ (1  2P12  P13 )(W 3  W 4 ) 4(P12 þ P13 )(1  P12 )dW 







(1 þ P12 )(W 3  W 1 ) þ (1  P12  2P13 )(W 2  W 4 ) G31 ¼ 4(P12 þ P13 )(1  P13 )dW 

G41 ¼







(2  P12  P13 )(W 4  W 1 ) þ (P12  P13 )(W 2  W 3 ) 4(1  P12 )(1  P13 )dW (36)

4.2 Phase difference for an n-node network with equal gain connections Following the described procedure, for an n-node network, P ji ¼ 1=(n  1) if i = j, and Pji ¼ 0 if i ¼ j; dW 1 ¼ dW 2 ¼    ¼ dW n ¼ dW and aji ¼ 0 8i, j. The phase difference between two nodes, u and v, is calculated considering that (25) is written for them, isolating the phase difference terms 

G1u þ G2u þ    þ Gnu

(n  1)(Ws  W u ) ¼ dW

G1v þ G2v þ    þ Gnv

(n  1)(Ws  W v ) ¼ dW

Considering that G32 ¼ G31  G21 and G43 ¼ G41  G31 









(2  P12  P13 )(W 3  W 2) þ (P12  P13 )(W 1  W 4) G32 ¼ 4(1  P12 )(1  P13 )dW 







(1 þ P13 )(W 4  W 3 ) þ (1  2P12  P13 )(W 1  W 2 ) G43 ¼ 4(P12 þ P13 )(1  P12 )dw (37) The solution obtained corresponds to a real synchronous state if the phase difference between any pair of nodes has an absolute value lower than 0.5. Therefore expressions (36) and (37) can be used as a criterion to design the lock-in range of the nodes if the gains of connections are known.

Subtracting the equations given in (39) (G1u  G1v ) þ (G2u  G2v ) þ . . . þ (Gnu  Gnv ) 



(n  1)( W v  W u ) ¼ dW

(40)

Multiplying (40) by 21, replacing the relations (26) and considering aji ¼ 0 8i, j, it is possible to obtain 

Setting equal values for the connection gains, P12 ¼ P13 ¼ 1=3 in this case, expressions (36) and (37) assume the same form given below   3 (Wj Wi ) Gji ¼ 4dW

(38)

This form of the phase difference equations is useful to determine the lock-in range of the nodes, because the maximum central frequency difference is defined as node central frequencies are known. It can be argued that a specific choice of dW that gives phase differences lower than 0.5 for a given connection matrix does not guarantee that the synchronisation condition holds for any other connection matrix. On the other hand, observing (36) and (37), it can be noticed that for a given set of central frequencies, there are always sets of gains satisfying the synchronisation condition. In this way, a connection matrix composed of equal gains can be used to estimate the lock-in range but, to choose the connection gains, the synchronisation condition must be numerically verified solving (35). Considering the results for the 4-node network, the procedure to estimate the lock-in range of the nodes in an n-node network is to suppose a connection matrix with all the elements equal, except in the main diagonal where they are equal to zero. The chosen value guarantees the synchronous state existence for the network. The solution of (28) gives the connection gains for different network conditions. 502 & The Institution of Engineering and Technology 2008

(39)

Gvu



(n  1)( W u  W v ) ¼ ndW

(41)

Expression (41), giving the phase difference between nodes v and u, allows the derivation of a criterion for designing the lock-in range for the network, because jGvu j, in this case, needs to be lower than 0.5, so that there is a reachable synchronous state for the network, as shown in Section 3.3. A practical issue about (41) is that the skew in the recovered clocks can be reduced increasing the lock-in range of the nodes.

4.3 Lock-in range design criterion As it was shown, the choice of the lock-in range can be made considering a connection matrix with all elements equal to 1=(n  1), except for the main diagonal elements that are supposed to be zero. Besides, the lock-in range of all nodes is considered to have the same value, so that the phase difference between any two nodes is lower than 0.5. Then      u v   (n  1)W  W  G  ¼ , 0:5, 8u, v ¼ 1, . . . , n (42) vu ndW that can be written in the form       (n  1)W u  W v    maxGvu  ¼ max , 0:5 u,v u,v ndW

(43)

IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 495– 508 doi: 10.1049/iet-cds:20080116

www.ietdl.org ji

Therefore,

dW .

    2(n  1)   maxW u  W v  u,v n

(44)

If D indicates the maximum central frequency difference in the network, the design criterion for the lock-in range is 2(n  1) D dW . n

(45)

Equation (45) shows how to choose the lock-in range of the nodes of a mutually connected PLL network and it only depends on the number of nodes and on their central frequencies. This criterion is sufficient to have at least one synchronous state for the whole network and the solution of (28) must be verified if a different connection matrix is considered.

5

Filter cut-off frequency

Observing the results obtained here, related to the static behaviour of the system, it is possible to conclude that the existence of the synchronous state, the value of the network synchronisation frequency and the lock-in range of the nodes do not depend on the filter cut-off frequencies and apparently, they are not an important design feature. Nevertheless, the main function of the filter in the DPLLs is to reject possible transmission noise. Here, a dynamical measure of the synchronisation quality depending on the external signal and on the filter cut-off frequencies is developed, providing a tool to complete the design of a mutually connected network by choosing the filters. It is the worst-case analysis, considering the effect of a perturbation that triggers a transition in the detector for the i-node filter that compares the node internal signal with the signal from node j. All the network nodes are considered to be synchronised with the unitary normalised frequency and the phase differences Gji are given.

ji

Consequently, if vi and vd have logical level 0 when a ji transmission error occurs, if vi is in the logical level 1, the detector output has an up transition and has a new down transition only when vis has a new down transition. Then, for a certain time interval, the detector output remains in logical level 1 when the correct logic level is 0, even if the transmission error affects just one bit. Fig. 5 shows the described situation in the worst case, that is, when the transmission error causes an up transition in the output of the detector just after its down transition. The filter outputs are shown in the situations with and without transmission error. As the network is considered to be in the synchronous state, it is possible to conclude that if the filter output is corresponding to the situation without transmission error, the period of node i will be unitary. Then, in order to calculate the effect of this error in the node i period, it is assumed that: † The effects that the period variation in node i causes to the other nodes are not considered, because they are compensated by the rest of the network. † The period error in node i is calculated considering that the filter output remains incorrect for a time equal to the original period of the signals. From this point on, the filter output without transmission error is denoted by vpji and the filter output with transmission error, by vep ji , as indicated in Fig. 5. Furthermore, the interval between the detector output down transition and the transmission error occurrence is neglected. The time scale to be considered implies t ¼ 0 for the transmission error instant. The curves vpji and vep ji are evaluated for 0  t  1. Considering (21 –24) obtained in Section 3.2, with the adequate algebraic manipulations, it is possible to conclude

This is a realistic hypothesis, because the phase differences in the synchronous state do not depend on the filter cut-off frequencies.Besides, node i has lock-in range dW i , central frequency W i and the connection gain between nodes j and i is denoted by Pji . To explain the effect of the transmission noise in the synchronisation of the network, it is necessary to see how the PD works. As already explained, the two input signals, ji (vi ), from node j, and inverted i-node internal signal i, ji i (vo ), are compared. The detector output, vd , has an ji ji up transition when vi has an up transition. vd has a down transition when vsi has a down transition. IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 495– 508 doi: 10.1049/iet-cds:20080116

Figure 5 Worst-case transmission error: effect in the filter output 503

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www.ietdl.org that vpji (t)

¼ Vdd

! 1  eFc (0:5þGji ) Fc t , e 1  eFc

0  t  0:5  Gji

!

vjip (t) ¼ Vdd

(46) !

eFc (0:5Gji )  eFc  1 eFc (t0:5þGji ) þ 1 , 1  eFc

0:5  Gji , t  1

(47)

and ji

vep (t) ¼ Vdd

! ! 1  eFc (0:5þGji ) Fc t 1 e þ1 , 1  eFc

0t1

(48)

Figure 6 One-period node error due to transmission errors

The next step is to determine how this filter output difference causes error in the transition instant of node i. In order to conduct the reasoning, the normalized VCO model described in Section 2 is considered and, by definition

phase, due to the input arriving from node j. As the period of node i is unitary

_ ¼ F ji

dW i vpji Pji Vdd

DFji ¼ dW i Pji (49)

corresponding to the contribution to the derivative of node i

ð1 0

vpji Vdd

dt

(50)

corresponding to the one-period phase variation of node i due to the signal arriving from node j. Consequently,

Figure 7 Simulation results for the 4-node network with W1 ¼ 0.85, W2 ¼ 0.95, W3 ¼ 1.05 and W4 ¼ 1.15 a Phase differences between all nodes and node 1 b Time interval between transitions for each of the four nodes In dotted lines, the values G21 ¼ 0:125, G31 ¼ 0:25 and G41 ¼ 0:375 obtained by analytical methods for the synchronous state are indicated dW ¼ 0.6 and Fc ¼ 1

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www.ietdl.org

Figure 8 Circuit-level simulation results for the 4-node network with W1 ¼ 0.85, W2 ¼ 0.95, W3 ¼ 1.05 and W4 ¼ 1.15 a Phase differences between all nodes and node 1 b Time interval between transitions for each of the four nodes In dotted lines, the values G21 ¼ 0:125, G31 ¼ 0:25 and G41 ¼ 0:375 obtained by analytical methods for the synchronous state are indicated dW ¼ 0.7 and Fc ¼ 1

considering the filter output in the case of transmission error, the described phase variation is

~ ¼ dW i P DF ji ji

ð1

v~ pji

0 Vdd

dt

(51)

As the network is considered to be in the synchronous state, ~  DF . the one-period phase variation error is given by: DF ji ji The expression for the function time interval error for a unitary time interval is

TIE(1)ji ¼ dW i Pji

ð1 0

v~ pji  vpji Vdd

dt

As Fig. 6 shows, it is better to choose low cut-off frequencies. Furthermore, the values of the phase difference is important to evaluate the effect of the transmission errors. Assuming that dW i ¼ dW and by using Fig. 6 to verify that the maximum transmission error occurs for Gji ¼ 0:5, (53) gives the maximum transmission error, Ejitrans Ejitrans ¼ max TIE(1)ji ¼ Gji

E trans ¼ max i, j

TIE(1)ji eFc  eFc (0:5þGji ) ¼ 0:5  G þ ji dW i Pji Fc

(53)

Fig. 6 shows TIE(1)ji =dW i P ji for Gji between 20.5 and 0.5, and Fc between 0 and 10 with a colour scale representing the synchronisation quality. IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 495– 508 doi: 10.1049/iet-cds:20080116

(54)

Therefore the highest possible value of error, due to transmission noise is

(52)

Replacing (46 – 48) in (52), performing the integrations and algebraic manipulations

 dWPji  Fc þ eFc  1 Fc

 dWPji  Fc þ eFc  1 Fc

(55)

E trans may be calculated for a given network configuration and can be used as an evaluation criterion for the synchronisation quality.

6

Numerical experiments

In this section, some numerical experiments are conducted to validate the theoretical results, simulating a 4-node mutually connected DPLL network with the following parameters:     W 1 ¼ 0:85, W 2 ¼ 0:95, W 3 ¼ 1:05 and W 4 ¼ 1:15; 505

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Figure 9 Simulation results for the 4-node network with W1 ¼ 0.85, W2 ¼ 0.95, W3 ¼ 1.05 and W4 ¼ 1.15 a Phase differences between all nodes and node 1 b Time interval between transitions for each of the four nodes d W ¼ 0.6 and Fc ¼ 1 A critical transmission error is forced between nodes 1 and 4 after the tenth transition of node 4 In dotted lines, the values G21 ¼ 0.125, G31 ¼ 0.25 and G41 ¼ 0.375 obtained by analytical methods for the synchronous state are indicated The value E trans 14 ¼ 0:0721 corresponding to the maximum error in the time interval between transitions of node 4 caused by a transmission error in the signal coming from node 1 is indicated with a dotted line

dW i ¼ dW ¼ 0:6 8i; Fci ¼ Fc ¼ 1 8i and Pij ¼ 1=3 for i = j and Pii ¼ 0. Solving system (28) for these parameters, one can conclude that in this case there is just one possible synchronous state for the network corresponding to a43 ¼ a42 ¼ a32 ¼ 0, which corresponds to Ws ¼ 1, G21 ¼ 0:125, G31 ¼ 0:25 and G41 ¼ 0:375. The network was simulated considering the model given by (17) by using Euler’s algorithm with integration step 0.001. Fig. 7a shows the phase differences between all nodes and node 1, as a function of time. Dotted lines indicate the expected values obtained analytically. It can be observed that the simulation results are according to the analytical ones except for an oscillation of the phase differences present in the synchronous state. To verify the importance of this oscillation, in Fig. 7b, only the time interval between transitions for each of the four nodes of the network is plotted, showing that the oscillation of the phase differences does not affect the achievement of synchronisation. The same network was simulated in circuit level to verify the validity of model (17). The simulation was conducted by using 506 & The Institution of Engineering and Technology 2008

the model of commercial PLL CD4046 present in PSPICE libraries of ORCAD 9.2, in spite of the limitations of their macro-models. Filters were implemented with simple RC circuits and phase comparators with two type-D flip-flops and one operational amplifier. The operational amplifier was used to guarantee that the comparator output remains between 0 and Vdd . For the implementation of connection matrix and of summation operations, only operational amplifiers were used. Central frequencies of the nodes were set to 42.5, 47.5, 52.5 and 57.5 kHz, all nodes’ lock-in ranges were set to 35 kHz and all cut-off frequencies of filters are 50 kHz so that the normalised values are equal to the desired ones. Initial phases were all set to zero. Phase differences between nodes, calculated with the time differences between transitions of nodes are shown in Fig. 8a and the time interval between transitions is shown in Fig. 8b. Dotted lines indicate the expected values obtained analytically. Concerning synchronous state reachability and steady-state phase differences, the simplified model (17) presented here is in accordance with the circuit level simulations, as shown in Figs. 7 and 8, although circuit-level simulation took about 1000 times more. The adjustment of the central frequencies in the PSPICE simulations was obtained setting the values of two resistors and one capacitor from the external circuit coupled to the IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 495– 508 doi: 10.1049/iet-cds:20080116

www.ietdl.org CD 4046. These values were calculated based on the datasheet information with the central frequencies and ranges being strongly nonlinear with the values of the components. Consequently, the PSPICE simulation results (Fig. 8) are slightly different from those obtained by pure numerical simulation (Fig. 7).

As a concluding remark, the theoretical results derived here are useful for practical purposes when the performance of the clock distribution system has to be estimated during the design and the fully connected digital architecture is chosen. Additionally, expressions of synchronous state and lock-in range, combined with expression (55) and Fig. 6, permit the simulation of limit situations in advance, evaluating their effects.

To verify the effect of transmission noise in the network behaviour, an error was forced in the signal transmitted from node 1 to node 4 in the critical situation described in Section 5.

8

According to the notation used in the derivation of (55), in this case i ¼ 4, j ¼ 1, dW ¼ 0:6, Pji ¼ 1=3, Fci ¼ 1 and Gji ¼ G14 ¼ G41 ¼ 0:375. With these values, the error in the time interval between transitions of node 4 should trans ¼ 0:0721. not be greater than E14

9

Fig. 9a shows the phase differences between nodes for the transmission error happening after the tenth transition of node 4 and Fig. 9b shows the time interval between transitions for all nodes, in the same case. The value of trans is indicated in the figure, showing that the simulated E14 network behaves in accordance with the analytical results.

7

Conclusions

The use of clock distribution systems with a mutually connected architecture is increasing in many engineering areas. The nodes can be cheap and reliable if DPLLs are used as time regenerating devices. Nevertheless, due to the inherent nonlinear characteristics of the PDs, the system is composed of nonlinear oscillator nodes with nonlinear coupling between them. The work developed here is a contribution to modelling and designing this kind of system. In Section 2, starting with a single node DPLL, a complete model for the whole network is presented, and by using it, designers can simulate the dynamical behaviour of the clock distribution system choosing node parameters and connection weights. Besides, in Section 3, analytical conditions for the existence of network synchronous state are derived in Section 3.3 depending on the node central frequencies, lock-in ranges and connection weights. In Section 3.2, the oscillations around the synchronous state are expressed by (24) and (25) that are useful to evaluate the synchronisation quality, in the steady state. As it was shown, the node lock-in ranges are decisive to the existence of the synchronous state, being one of the most important design parameters in this kind of architecture. Expression (45) is helpful to the designers, in order to guarantee the synchronisation of the network. Furthermore, expression (55) and the abacus of Fig. 6 are tools to specify the performance of the whole time distribution set, providing a method to choose the filter parameters. IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 495– 508 doi: 10.1049/iet-cds:20080116

Acknowledgment

JRCP is supported by FAPESP and CNPq, RC is supported by CNPq.

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